anon, pa reine Herel OFT inom maxing ha 860 -twoetit Pan HOME > TECHNOLOGY > PROCESSING > cHIPS& SoCs Importance of Hierarchical DFT implementation in maximizing the SoC - throughput ? Part - I November 24,2020 story Advanced Design For Test(DFT) techniques provides efficient test solutions to deal with higher S test cost, higher power consumption, test area, and pin count at lower geometries. Advanced Design For Test(DFT) techniques provides efficient test solutions to deal with higher test cost, higher power consumption, test area, and pin count at lower geometries by improving the controllability and observability of the sequential flops. In turn, this improves the yield on SoC. Reliability and testability are important factors in today's ASIC world. SoCs are nothing but integrated circuit that integrate multiple processor cores, microcontrollers, interfaces, DSPs (digital signal processors), and memories on a single silicon substrate. In this era, it is one of the most important parts of any digital system because it helps in saving power, cost, and space. A core is nothing but intellectual property or IP Cores of the SoC design companies. SoC design companies supply tests for the core and the SoC designer provides the test access to a core embedded on the chip. It is. the hierarchical level at which wrapper chains are inserted by inserting the wrapper structure with test logic. We can minimize the core test problem and can reduce the top-level pin count of the SoC. This paper gives a brief about the importance of Hierarchical DFT techniques, which utilizes wrapper chains to overcome the problems of testing large SoC design. It significantly reduces the ATPG test time, memory footprint, and pin count. Ultimately, it reduces the time to market, Test Core Wrapper For DFT, each core can be tested separately before SoC level integration. While performing integration, when they are configured in internal test mode, the core’s internal logic can be tested separately or in a group. However, when configured in the external test mode, the surrounding logic of the core can be tested. By doing so, our main concern is to divide the SoC test in a different configuration, to greatly reduce the pattern generation effort and in turn to reduce test time. Wrapper Cell Structure wor ereccezonpungsentuctnaypocaerptansancnostannaltecicaldhinsrerttenninanptesecro atFigure{1-3] Shared Wrapper Cell Figure{2-b] Dedicated Wrapper Cell ‘Test wrapper modes Inward-facing or INTEST mode In INTEST mode, by driving the inputs from the input wrapper cells, we test the partition and outputs are captured through output wrapper cells. This is completed by disabling the scan chain outside the core. It facilitates the isolated testing of the partitioned core with ATPG. During capture, input wrapper cells are shifted with a separate input wrapper scan enabled signal, which avoids x capturing from outside the partition. Whereas output wrapper cells capture the internal state of the partitions, ones ui -—— (Figure 21 Inward Facing (ntest) Mode) Outward-facing or EXTEST mode In EXTEST mode, wrappers are enabled and configured to drive and capture data outside of the design. It essentially disables the internal chains by bypassing it in this mode. Hence, it reduces ATPG test time as well. To test the top-level logic between the partition and unwrapped logic, we can use this mode. During the capture stage, values are being captured by input wrapper cells outside the partition and the output wrapper cells shift during capture to avoid capturing x's from inside the partition’s un-driven internal scan chains. anne | | vmemteneen secon J ri TP cemsnscenennetrot (Figure [3}: Outward Facing Extest) Mode) Hierarchical DFT Methodology (Figure (4: Hierarchical DFT Implementation (From Core to Chip level) worereccezonpuingantuctngybosaarptiansanaastannaltecicaldhingnerttensinanptesee raat