ECE_2161 Digital System Design Lab Manual III Semester B.Tech (Electronics & Communication Engineering)CONTENTS, Expt. No. Experiments 1. _| Arithmetic circuits 2 Multiplexers & Demultiplexers Encoders & Decoders Counters Shift Registers Introduction to VIVADO tool- simulation, synthesis and implementation 8.__| Implementation of Full adder in all abstraction levels 9.___| Design and verification of Encoders and Decoders 10. _| Design of Flip-flopsusing behavioral modelling, 11, __| Design of Counters using behavioral modellingCOURSE OUTCOMES At the end of the program the students will be able to: COL: Design and Test combinational circuits CO2: Design and Test flip-flops and counters CO3: Design and test synchronous sequential circuits using Flip-Flops and logic gates CO4: | Write Verilog code for digital circuits using behavioural and dataflow style COS: Write Verilog cade for digital circuits using structural style EVALUATION PLAN [I] Internal Assessment Internal Assessment Marks: 60% (60 Marks) The weekly evaluation scheme is as follows: (10 Evaluations) (Conduction of experiment ~ 4*10 = 40 Marks (ii) Lab record book ~ 4*10 = 40 Marks (ii) Exercise problems ~ 2*10 = 20 Marks Total marks will be scaled to 60 Marks [II] End semester Assessment End semester Assessment Marks: 40% (40 Marks) (i) Write up -10 Marks (ii) Conduction/execution ~10 Marks (ul) Viva- Voce -10 Marks (iv) Result -10 Marks PRE-LAB PREPARATION Each lab experiment requires the preparation that may involve a signil cant amount of work, The pre-lab work must be completed before arrival atthe lab. The pre-lab work will be part of your lab grade and will be evaluated every week. The student must revise concepts related to Logic design and Verilog Programming before coming to labLABJOURNAL, ‘The students have to maintain Lah Journals and need to submit the same to the faculty at start of each lab. Each experiment must be written neatly and include the following details as applicable. Experiment Number and Date Experiment Title and Objective ‘Truth table, Logic equation and circnit diagram for combinational circnits State diagram/state table and circuit diagram for sequential circuits Verilog constructs used ifany Verilog code for each exercise problem Simulation results and analysis Conclusion Solution to additional assignment problems if any given by facultyExperiment No. 1: ARITHMETIC CIRCUITS Aim: © To design, implement and test half adder and half subtractor, Full adder and Full subtractor. © To study 4-bit parallel adder — IC 7483 © To design, implement BCD code arithmetic circuits using IC 7483 Equipment & Components Required: © ICs 7408, 7432, 7404, 7400, 7486, 7410, 7433 @ IC trainer kit, Connecting wires A. Half adder: Truth Table Taput Output A|B[>c|S en =) s oj] of 070 B+ of1fofi i CO I T T 0 [ S-F.BtA.B CAB B. Half Subtractor: Truth Table x, -—) >» Input ‘Output Y. x [y [DIB o0[o foo a 1 B Tpoyiyo 1/i1ftoTo D=XOY B-XY C. Full adder: Truth Table: Taput ‘Output A_[ B [Gn [Cou] S 0 0 0 0 0 oO oO 1 0 1 0 1 O 0 1 0 qT T q 0 1 oO oO 0 1 1 oO 1 1 0 1 1 0 1 0 1 1 1 1 1S-ADBBCn Cout ~ABYBCint Gn D. Full Subtractor: Truth Table: Taput ‘Output XY [BT D [Bu % ofoy,ofolfo ¥% ofo;ifPifti oftyof1fi Ba ofi1yi1fofi rfTo,of1tfeo i 1[1];o};ol|o TtrpryPi ti D=-X®Y@Bin Bout ~X®Y BintX Y E, 4-Bit adder /2’s complement subtractor: BB BBWhen control (Cis) input is 0, input B = Bs Bz By Bo is added to input A= As Az Ai Ao When control (Cin) input is 1, 2°s complement of B is added to input A. (ie, A-B) Difference is available at Ss Sz Si So, borrow output at Cou. BCD adder: 7489 83828180 ‘When two 4- bit BCD numbers are added, if the sum exceeds 9 or if there is a carry then 6 is added to the sum and a carry is generated to the next decimal digit. Carry from the addition of 6 (if any) is neglected Exercises: 1, Implement a full adder using two half adders and one OR gate. 2. Implement a full subtractor using two half subtractors and any additional gate. 3. Implement a2 bit binary multiplier using AND gates, half adder and full adder blocks. 4, Implement a single digit Excess-3 adder using 7483,Experiment No. 2: MULTIPLEXERS AND DEMULTIPLEXERS Aim: © To design and implement various multipleser circuits and to generate logic functions using multiplexers © To design and implement Demultiplexer. ‘Components & Equipment Required: © ICs 74151, 74153 © Logic gates © IC trainer kit, connecting wires A. 4:1 Multiplexer using only NAND gates Function Table: +L faim S| So Y 0 0 Do 0 1 Di De I 0 Dz 1 1 Ds Dy oe S,SgDo + S\SoDr + SSoD2 + SSoDs UUUU B. Implement f= Em (0, 3, 5, 7, 8, 10, 14) using i) Function Table :1 MUX ii) 4:1 MUX and additional gates ; Using Using AYP Le | PF | sameux | armux 0 0 0 a T =D ope poe prt * 19=CED 0 0 1 0 [0 h=D 0 0 1 1 1 0 1 0 a) bel b=D 0 1 0 1 I n-D 0 1 1 a =D 0 1 1 1 i 1 0 0 0 r y=) — I 0 0 1 0 H bh=-D I 0 1 0 i 15-D 1 0 1 1 0 I I 0 a) 7 15-0 = I 1 0 1 0 ° -CD 1 1 1 0 i hed 1 1 1 1 0Eg AB he LI b G > ‘SiS0 | t ol, O24 I i 1A ZAI \ ; = rs [) 3A +—— i, 3 —0B c—s 1B p—s 28 A—S _|38 74151 74153 na 1 to 4 Demux using basic gates. Select | Data ‘Output lines S |S |D>w[ VV] hw] Y o[ofoi;pfofole o[ifwipofpfols r[ofonfo}o|py|o« r[1fontofofolp Exercises: 1, Implement f (a,b,c) -ab+ac%abe using (i) 8:1 MUX (ii) 4:1 MUX 2. Implement a full adder using 4:1 MUX and 8:1 MUX. 3. Implement 8:1 MUX using 2:1 multiplexer. 4. Design a 3-bit binary to gray code converter using 4:1 MUX. 5, Implement F = Ym(0,5,7,11,15,16,18,25,29 ) using two 8:1 and one 2:1 MUX. Using 8:1 MUX D Using 4:1 MUXExperiment No. 3 ENCODERS AND DECODERS, Aim: © To design and implement Decoders and Encoders, Components & Equipment Required: © ICs 74139, 74138, 74154, 74148 Logic gates © IC wainer kit, connecting wires A. Design and implement 2 to 4 decoder using basic gates: Function Table: A 8 INPUT OUTPUT A |B [Do] Di[ Dr] Ds ofolifolfofo (0a) 15 |0s|ans|a0n|E0i 1[ofofolifo T[1fofofoft LT {+ » J- Ds B. Design and implement 2 to 4 decoder with enable input using only NAND gates Function Table Taput Output E [A |B | Do| Di] Ds| Ds o;x~x}ififi[i T{ofolo|ifi{i © Tpovt{i1fofiyt PF Do Tftfoli{i pols 5 tfififrfififo Lt > D2 Ss YDC. Design and implement Octal to Binary Priority encoder using basic gates, ‘Truth Table: A= Ds + Ds + De + Dz B=D2z+ Ds + Dg+ Dr C= Di + D3 + Ds + Dr Dy D. Dy De Ds Ds Dy Inputs Outputs Do | Di Ds | Di} Ds| De| Dr] A} BI C an-||40, 0-|-0-|0:|0'| 0: | 01} 0 | 0 oft o}ofo}ojolo}fo}1 o}o 05 | 205 |/f0= | 05 | 08-101 eitr=|/-0) o}o 1} ofolofo}o}jijf. o}o On| ale On| a0 n | On| G a |:0) o|}o o}ofifofolifo}.4 o}o (0) 205 |/ 08 | elie |p 08-|ieds- lati | 20) o}o (0 | se |g] 0's | ries ia eat aeExercises: Implement a 2:4 priority encoder using basic gates with MSB having the highest priority Implement f-ab+be+ Gbé using 74138 and additional gate. Design and implement a 4 to 16 decoder using two 74138 decoders. Implement f(A, B, C, D) = Y(0, 3, 5, 9) using two 74138 ICs and additional gate. Implement a2 bit magnitude comparator using 3 to 8 decoders and additional gates. yeeNeExperiment No. 4 STUDY OF FLIP-FLOPS, Ai © To study the operations of SR Flip-flop, D Flip-flop, JK Flip-flop, T Flip-flop. © To study the IC -7474 & IC — 7473, Components & Equipment Required: ©@ ICs 7400, 7473, 7474, 7404, 7408, 7432, 7410 © IC wainer kit, connecting wires © Cathode Ray Oscilloscope A. SK Flip-flop using NAND gates: | De ; can | Feu | 4 [ Note : Apply high-going mono pulse to CLK. ‘Truth table: INPUT OUTPUT CLK S| RJ Qnet ae Qn Rising Edge | 0 | 0 Qn = Qn Rising Edge | 0 | 1 0 1 Rising Edge | 1 | 0 1 0 Rising Edge | 1 [| 1 Not AllowedR._D Flip-flop using NAND gates: ‘Truth table: D o—_+—_—_s | INPUT OUTPUT CLK D | Qi Quer leuk cai x | 2 2. ising Edge ° ' Rising R Edge | | ' ° Note: Use NAND gates to implement SR Flip-flop C. JK Flip-Flop using NAND gates: Jj Q cLK Qa K Truth Table: INPUT OUTPUT CLK J One 1 ee Qe 1 Rising Edge | Qn _ Qn Rising Edge | 0 0 1 Rising Edge | 1 1 0 Rising Edge | 1 = Qn enD. T Flip-Flop using NAND gates: T P| ‘Truth table: INPUT OUTPUT ck] T | Qu: Qa Low | xX 2, 2, mete | 2 | am EES 1 Toggling E, Study of IC 7474: Positive edge triggered dual D Flip-flops with preset and clear. Truth table: PRESET | CLEAR | CLOCK | DATA 0 PR CLR CLK D ia On 1 0 1 x x 1 0 1 0 x x 0 1 1 1 0 x Qn = On 1 1 | Rising Edge 1 1 0 1 1 | Rising Edge | 0 0 1F. Study of 74LS73A: Negative edge triggered dual JK Flip-flops with clear Truth table: CLK Ont —_— Qn+ 1 o xX oO 1 1 Falling Edgi 0; — alling Edge Qn On 1 Falling Edge 1 0 L Falling Edge 0 1 1 Falling Edge = Qn Qn 1 1 Qn = Qn G. Conversion of Flip- flops: (a) Convert D to SR Flip-flop S| R | | Qi] D o{ofo|o|o ofofi 1 1 (Os et = nO Oe | of[i/fif[ol|[o T[o foi 1 oe Oe T 1 1[1fo[x]Tx rtTi1tilTx [x Using K map we get the expression for D D=S+RQ Exercise: 2, 3, 4 Convert D flip-flop to T Flip- flop Convert JK flip-flop to SR Flip-flop. Construct a gated SR flip-flop using NOR gates. Implement a positive edge triggered D Flip-“lop using only NAND gates.Experiment No. 5: COUNTERS Aim: © To convert IC — 7473 to work as i. Divide by two counter ji, Divide by four counter © To design and test 4 bit asynchronous up-counter using IC 7473. © To design and test 4-bit synchronous up counter using IC 7473. © To test Johnson and Ring counters. Components & Equipment Required: @ ICs 7408, 7473, 7474 © iC tramer kat, connecting wires © Cathode Ray Oscilloscope A. Divide by 2 and divide by 4 counters using 7473 Sv cro + o kHz 7473 men} ck ob aR Inovt wovetoom Ovtout movetor Divide by 2 counter circuit and waveformsv a Divide by 4 tke Output exn> fo wowetorm Onide oy 2 Oia oem Di ide by 4 counter circuit and waveform B. Four bit Asynchronous up counter using two 7473 ICs Ea cu ux. cK gpcuk ae am mm amInput Outputs Clock pulse Q@ Q@ Q Qo 0 1 2 15 C. 4-bit Synchronous up Counters © In the Excitation table shown above Qu and Quit are present and next state outputs. For a 4-bit counter, it is required to count from 0 to 15, which requires 4 JK Flip-Flops. Excitation Table of JK Flip-Flop Qu | Qn+i [J TK 0 o fo x 0 I 1 x i 0 [x i i sae [Xs 0 © Let the outputs of these Flip-Flops be Qo, Qc.Qu,Qa respectively and Js,Ka be the inputs ofFlip- Flop A. Jn,Kn of Flip-Flop B & 50 on. State Table Q» [Qe | Os [em | aT QcH | QB | att [Jol Ko [Je | Ke | Je [ Ko [Ja] Ka ofolofo| o 0 0 1 |o[x;o|xfo|x|i|[x ofolo/i|o 0 1 o [ol xfo[x| 1 /x{[x[t ofol[ifo|o 0 1 1 [o[x]o/x{[x]o]i/ x ofolit iyo 1 0 o- fol x ti Txt x ti txt ofi[ofo|o 1 0 1 [ol x|xfofo|[x]i[x ofifoli{o 1 1 o [ol xt x TotiTx{xtt ofi[ifolo I 1 1 [ol x{x]o/[x To fi[x ofi{[i]i{[t 0 0 0 [atx txt7 yxy itt rlofolo[t 0 0 1 [xfol[o/[xfo|[x]i[x rfPofoviyt 0 1 o [xfo ToT x| 7 [x{x[t 1lofitott 0 1 1_[xfo [oT x]x7o fit x rtotititt 1 0 oT xfo ti Txt x ta xt Tl1folfoyt 1 0 1[x~Po|[x]ofo/x]fi[x 1[1foli{tt 1 I o [xfoTxfoli[x{xti 1f1{[ifott 1 1 1 | xfo|x/o[x]o]i[x tli {i{i{o 0 0 0 [xa Txt [xt 7 [xt Draw K-maps for various Js & Ks and simplify. Implement the logic circuit and verify.Procedure: Connect the circuit. 2. Momentarily clear all the inputs by giving CLR = 0 & then make it permanently high by giving CLR=1. 3. Verify the circuit by observing the output for each clock pulse. After the 15" clock pulse (i.e. for the 16" clock pulse) output QoQcQuQa = 0000. Tabular Column CLK | Qo | Q | Qe | Qa sfele|afofu} a] efro}—|o} ui 2 3B 14 5D. Ring counters: CLR Sequence Table: CLK] Qv |] Qe | Qu] Qa alate) -lelo]o}— elele|-|o} olol-lolo el-lolole E. Johnson Counter: ‘Sequence Table: CLK | Qo | Qe | Qu] Qa aul a fea) no] | ef-}-|-|-lo] -|-|-|-|>]6) -|-|-le]e}o} -|-lelele}o|Exercises: 1. Design and implement a ripple decade counter and verify its operation. 2. Design a 2-bit up-down synchronous counter using JK Flip-Flop. 3. Design and test Synchronous counter for the sequence 0, 1, 3, 2, 6, 7, 5,4, 0. 4 Design a 3-bit Johnson and Ring counters using JK Flip-Flop.Experiment No. 6: SHIFT REGISTERS Aim: © To design and test the following Shift register topologies. 1. Serial-in Serial-out. 2. Serial-in Parallel-out. 3. Parallel-in Serial-out, 4, Parallel-in Paralle!-out. © To study the operation of IC 7495 Components & Equipment Required: © 10-1474, IC 1408, IC 1400, IC 1495, IC 14164 © IC Trainer kit, connecting wires A. SISO,SIPO SHIFT REGISTER: Circuit diagram: Q@ Q@ Q Data in DQ] el CLK Procedure: 1. Connect the circuit as shown in the circuit diagram permanently logic! Enter any 4-bit serial input using clock pulse for every bit. For example, to enter 1011 First make serial input =I, apply a clock pulse, Make serial input=1, again apply a clock pulse, Make serial input-0 again apply a clock pulse, Make serial input =1, apply a clock pulse. This ensures that the register has word 1011 stored in it 10. Observe the data at the output of each shift register simultaneously 11, This constitutes parallel output data. PeIrawew Data out Switch on & momentarily clear all the Flip-Flops by giving low to the clear input, Then make it 12. To observe the output data in serial fashion, apply clock pulse by keeping serial input data zero. B. PISO,PIPO SHIFT REGISTER: 1. Make the clear and parallel enable low ie. CLR=0, PEO.2, To load the input data in parallel fashion, apply 4-bit data (D C B A) and make the parallel enable PEO 3. To read the output data in parallel fashion, make parallel output enable =1 ie PE=1 4, To read the output data in serial fashion, make parallel output enable =0 i.e. PE=0 & CLR=1. Then apply clock pulse making serial input data=0. Data gets shifted from left Flip-Flop to right Flip-Flop for each clock pulse. D Cc B A "—t—-—4] C. To study the operation of IC 7495 7495 IC is a 4-bit shift register. It has serial data input (Ds) and four parallel data inputs (Do- Ds) and four parallel outputs (Qo-Qs). Two separate clocks are available for serial transfer and parallel transfer (Refer IC manual for more details) Observations: MODE INPUTS OUTPUTS Do Di D2 D3 Ds QW Aa @ Parallel Load (Serial) Shift Right Exercises: 1. Implement a 3-bit PISO using mux and D filp-flops. 2. Implement a 3-bit universal shift register with four modes of operation namely HOLD,SHIFT LEFT, SHIFT RIGHT and PARALLEL LOAD.Experiment No. 7: Introduction to VIVADO tool — simulation, synthesis and implementation Aim: © To study the simulation of Verilog code vs Introduction: Xilinx Tool is a suite of software tools used for the implementation of digital circuits using Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic Device (CPLD). The desizn procedure consists of (a) design entry, (b) synthesis and implementation of the design, (c) functional simulation and (d) testing and verification. Digital design can be entered in various ways - using schematic entry tool, using a Hardware Description Language (HDL) - Verilog or VHDL or a combination of both. Here, we will consider the Verilog HDL based design flow. The CAD tools enable the design of combinational and sequential circuits starting with HDL design specifications. The steps involved in the design procedure are listed below: [a] Create Verilog design input file(s) using template driven editor. {b] Compile and implement the Verilog design file(s). {c] Create the test-vectors and simulate the design (functional simulation) without using a PLD (FPGA or CPLD). {d] Assign input/output pins to implement the design on a target device. [e] Download bit stream to an FPGA or CPLD device, [f] Test design on FPGA/CPLD device A Verilog input file typically consists of the following segments: © Header: module name, list of input and outpat ports. © Declarations: input and output ports, registers and wires. ‘© Logic Descriptions: equations, state machines and logic functions * End: endmodule All the designs must be specified using the above given Verilog input format.Getting Started To start VIVADO, double-click the desktop icon,, or start VIVADO from the Start menu by selecting: Start All Programs VIVADO 2020—+ Project Navigator Note: Your start-up path is set during the installation process and may differ from the one above. Create a New Project Double click on the Vivado icon on your desktop to open up the welcome window of the development tool (as shown below). Three main sections can be observed in this window: “Quick Start”, “Tasks”, and “Learning Center”. vivapo* € XILINX Create a new project which will target the FPGA device on the demo board. To create a new project: 1. In the opening menu, as soon as the VIVADO opens it notifies the Quick start option. Quick Start>Create Project... The New “Create a New VIVADO Project” Wizard appears.2. Type Next, immediately, you see a below screen. Name your project, ‘tst_1” and it will be in thefolder. # New Project B Project Name Ht: fe stored Projectname: tst_t Projectlocation: E/SKT Create project subdirectory Project willbe created at EvSKTASt_1 Fig.1.1: The New Project Wizard 3. In the Project Name field enter the desired Project Name. Enter or browse to a project location(directory path) for the new project, check the box project subdirectory, and press next 4. A new window will open which shows the project type. Click on RTL project. In the nextwindow, choose “RTL Project” as the project type and click next.Project Type spectyne ype ot peo wet, & @) BTLProject ‘You willbe abe to ad sources, create lock desions in IP integrator generate IP run RTL anaysis, synthesis, implementation, design planning and analysis, | Do not specify sources at his time Jeu. Yuu mil Ue ately add suuices, em Uevos fesuules 1 Danot specty sources at this ume {YO Planning Project DDo net spect design sources. You will abe to view partpackage resources, Imported Project Fig. 1.2: Project Type “9 New Projet Las ‘Add Sources Sect OL als eck Dssion andi es, reds covtangtose SS 19 agaioyour pec Cree anen soe eon Sek and 30080" ile] 4 Use Ada Files, Ata Directories or Create File butons below ‘sd Fes AgaDindories || Greate Fle Sem NN Targetianguage: Vetlog —_v | Sinulatorlanguage: Verilog @ coe] Ec | [eae Fig 1.3: Add Sources5. In the Add sources window click on create source to create a new Verilog file. If the Verilogfile already exists, then click on add file and browse folder file. Create a new source file and addito your project. Eleype: | @ Veriog Filename: fist Filglocation: | &: ie] oma | oar] Copy sources into p 7) Add sources rom su Fig.1.4(b): Create Source File6. In the create source file window specify the hardware language as Verilog. Specify the New file name and click ok. ‘kaa Constraint optional) Set cn cosa es pe mating cons & Fig.1.5: Add Constraints This is an optional window click on next. A New Prt = Detaurt Part x Catan At ~ | Pace |e9s206 | Tampuati|AlRemaning Fame ater ene g seach [O: ci at vOPIncount aladel08s LUTEIemens Fipfops GlecRals UNTER OSS GoTTansce erasing 236 08 zoo 180020 ° wo 2 rasoengns1 236 6 232500 smo 75 ° m2 Fig. 1.6: Default part7. Fill in the properties as shown in Fig, 6: to select the board for the project. + Product Category: All ¢ Family: Artix -7 # Speed: -1 + Package:epg?236 Click Next viVADo* © XILINX. ® New Project Summary © Anew RTL projectnamed tst_t willbe created. © No source files or sirectories will be added. Use Add Sources to add them ater. (© No constraints tes wi be added. Use Add Sources to add them ater © ‘The aetaut part ang product family forthe new project Default Part: xc7a36tep9236-1 Product: Ati-7 Family: Ati? Package: cpo236 Speed Grade:-1 ‘To create the project, click Finish Fig.1.7: New Project Window Click Finish to create the New Project. 8, New Project window will appear. Under Design sources of the Source window your file will appear in .y format. Then double click on the file to start writing your code, Ifyour file does not appear in the sources window, or if the Sources were not added previously then follow the below figure to add sources. After this step a new window will open, Click on Add Sources.EE RO Elle Edt Flow Tools Repgrts Window Layout View Help Or Quick Access B-c 7 8 BXP, BRE XK FS 1 sets : Qret 2 Sources Desi sources Fy Language Tempies oes > IP Catalog Y © Simulation Sources ¥ erarchy _Uncanes Compl Ozer © nirecRaroR Crete locxOes9n Properves 2-08% open Bock Design +\9\6 Generate Block Design ct an objectto see properties © SMULATION Run Simulation Fig.1.8: Selecting the source file. 9. Adding Sources: Click on add or create design sources and then click next. ‘Add Sources vivapo* he This guides yeu through te process of aang and creating source for our project ‘Addo crate constraints © dd orcreste design sources, @—————— ‘Addo create simulation sources © XILINX. @ Fig.1.9: Add Sources 10, Add or Create Design source window will open and click on create file. 11, Click Finish, 12, The Define module requests input and outputs for the module. Specify your input and outputvariables and Click OK,Define Module Deine a module an apecty 10 Pots oad our source | Fereach por specied iso and SS ves wi be nore nts fs Bus columns chectaa & Pots van lank nares tbe wien edule Detion Moaute name: st @ 0 Por betntions tote Fig.1.10: 10 port definitions. 13, Double click the created tst2 to get an editor window, in which we write our program. a oe Qiz|einieir|>lal® Fig.1.11(a): Writing the source code[Prosctsunmayx]eur x 7al E/SKTASL_tMst_1.stes/sources_tinewnsty Qk xBBXv EO z fodute eat Fig.1.11(b): Writing the source code 14. An example program has been shown here for reference: After writing the code save the file or press Ctrl+S, If there exists a syntax error in your code, it will appear in the source window. Check and remove the syntax errors before moving on to the next step. After writing the code click on Run simulation icon shown on the left. After Run simulation the top up window will ask Run Behavioral Simulation, Click on that Example code to get the timing diagrams has been shown below. PRORECT MANAGER 2 sacs 2-08 [romatmmay x]eue azet © | cusssimcetreseisecctt amt 2srasauess thew. 2¢ et “la xen xX EO os Pos, ‘source Pree 27-00% eu ° Fig. 1.12: Example codeExample-1,0: Write a dataflow Verilog code to realize the given logic function in POS form y(a, b, ¢) = 11 (0, 1, 6,7) and verify the design by simulation. Solution: yla,b,c) = (T +b +clT+b + Hath +cla+b +2) Verilog Code: module tst_2(input A,B,C, output F); wire Abar,Bbar,Cbar, assign Abar=~A; assign Bbar=-B; assign Cbar=~C; assign F=((Abar|Bbar|C)&(Abar|Bbar|Cbar)&(A|B|C)&(AIB|Cbar)); endmodule Run Simulation: Run Behavioral simulation, Fig. 1.13: Running the simulationUse force constant, and give the input values, A, B, C in this example. After forcing the values click the icon shown above to run the simulation, e ce Constant: /POS/A value, Assign iH Sweetman: Eorce value ° Fig. 1.14: Force value as input. In the figure shown below the input values are A Correspondingtiming diagram is s Untied 4 QmaeQ Pig Fig.1.1 Timing di am Instead of individually forcing all the input values, a test bench can be written in order to accompany all the combinations of input variablesExperiment No. 8: IMPLEMENTATION OF FULL ADDER IN ALL ABSTRACTION LEVELS Ai © Design full adder in data flow, gate level & behavioral modeling and verify the functionality by using stimulusblock or test bench. Logic gates Theory: Full adder is used to find the sum of two bits it gives sum and carry out as the result. Boolean equations: Sum = (A xor B xor C), Cout = AB+BC+CA FULL ADDER - Block Diagram: A >— TP Ca Full adder - Truth Table: SUM Carry Verilog program for Full adder in Gate level Modeling: module fulladder(a, b, cin, cout, y); input cin, a,b; output cout, y; wire wl, w2, w3; xor x1(wl, a, b); xor x2(y, wl, cin); and al(w2, a, b); and a2(w3, wl,or ol (cout, w2, w3); endmodule Verilog program for Full adder in Data Flow Modeling: module fulladder(a, b, cin, cout, y); input cin, a, b; output cout, y; assign {cout, y} = atbtcin; endmodule Verilog program for Full adder in Behavioral Modcling: module fulladder(a, b, cin, cout, y); input cin, a, b; output cout, y reg couty; always @(a or b or cin) begin case( {a,b,cin}) 0: begin y = 0; cout = Ocend 1 : begin y = 1; cout = 0:end 2: begin y= 1; cout = 0;end 3: begin y = 0; cout = I;end 4: begin y= 1; cout = 0;end 5 6 B begin y = 0; cout = I:end ), cout = 1;end cout = I:end Verilog test bench program for FULL ADDER : module tb_fulladder; reg cin, a, b; wire cout, y: fulladder uut(a, b, cin, cout, y); initial begin a=1;b=1;cin=0; #10 a= 0; b=1; cin=0; end initial begin Sdumpfile("test.ved"); Sdumpvais(1), #20 Sfinish; endendmodule Result: Design of full adder in data flow, gate level & behavioral modeling and verifying the functionality by using stimulus block or test bench is completed.4-BIT PARALLEL ADDER Aim: © Design 4-bit parallel adder using 1-bit adder (full adder) in structural modeling by instantiating full adder using named and position inst and verify the functionality of the design using test bench. Logie gates Theory: Pull adder is used to find the sum of two bits it gives oum and carry out as the result Boolean equations: Sum = (‘A EXOR b) EXOR cin) and cour=(A & B) & Cin 4-Bit Parallel Adder Block Diagram: AB A A: Bi r [i it Uf & al Full Adder CG] Full Adder | Cr C4 Full Adder 3 2 a o Se S Se Se FULL ADDER Truth Table: A B_ {Cin Sum Cout 0 0 0 0 0 0 0 1 1 oO 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 oO 1 1 1 0 0 1 1 1 1 1 1Verilog program for 4-Bit Parallel Adder using Position Inst: module fulladder(a, b, cin, cout, y); input cin, a, b; output cout, y. wire wl, w2, w3; xor x1(wl, a, b); xor x2(y, wl, cin); and al(w2, a, b); and a2(w3, w2, cin); or ol(cout, w2, w3); endmodule module adder4bit(a, b, cin, cout, y); input [3:0] a, b; input cin; output cout; output [3:0] y; wire [2:0] w; fulladder f1(a[0}, b[0], cin, w[0], y[0]); fulladder f2(a{1], b[1], w{0], w(1], y[1); fulladder f3(a[2], b(2}, wii], wih yI2); falladder £4(a[3], b[3], w[2], cout, y{3]); endmodule Verilog program for 4Bit Parallel Adder using Named Inst: module fulladder(a, b, cin, cout, y); input cin, a, b; output cout, y; wire w1, w2, w3; xor x1(wl, a, b); xor x2(y, WI, and al(w2, a, b); and a2(w3, w2, cin); or ol (cout, w2, w3); endmadulemodule adder4bit(a, b, cin, cout, y); input [3:0] a, bs input cin; ‘output cout; output [3:0] y; wire [2:0] w; fulladder f1(.a(a[0), .b(b{0)), .cin(cin), .cout(w{0)), -y(y{0))); fulladder 2 b(bLI), cin(wlO), .couttw{1), .y(¥LI), alal1))s fulladder £3(.b(b[2]), .cin(w[1]), .cout(w[2}), -y(yI2]), .a(al2])); fulladder f4(-b(b{3]), .cin(w{2}), .cout(cout), y‘y{3)),.a(al3))); endmodule Verilog Test bench program for Parallel Adder: module tb_adder4bit; reg [3:0] a, b; reg cin; wire [3.0)y; wire cout, adder4bit uut(a, b, cin, cout, y); initial begin Sdumpfile("test.ved"); Sdumpvars(1); #20 Sfinish; endmodule Result: Design of 4-bit parallel adder using 1-bit adder (full adder) in structural modeling by instantiating fulladder using named and position inst and verifying the functionality of the design using test bench is completed,Experiment No.9: DESIGN AND VERIFICATION OF ENCODERS AND DECODERS 3x8 DECODER USING 2x4 DECODER Ai © Design 3 to 4 decoder in gate level modeling with enable input and inst it 3 to 8 decoder using structural modeling and verify the functionality of design with the help of test bench, DECODER Theory: A decoder is a combinational logic circuit which is used to change the code into a set of signals. It is the reverse process of an encoder. A decoder circuit takes multiple inputs and gives multiple outputs. A decoder circuit takes binary data of ‘n’ inputs into ‘2” unique output. In addition to input pins, the decoder has a enable pin, This enables the pin when negated, makes the circuit inactive. 3 to 8 DECODER - Block Diagram: (2) 2 ‘a F fe, S 3 To 8 DECODER - Truth Table: S2 Si_[S0 E[D7 [Dé [DS [D4 [D3 [D2 [Di | DO x[ x x} ol 0 of of 0 of of of 0 ol o of if o of of 0 of of of a of 0 Tf] 1{ 0 of of 0 of of tf 0 0 1 of 10 of oto 0 r{/_ot_o 0 1 Tf] 1{ 0 of of 0 1 o| of 0 r]_0 o; 10 of oft of of of 0 ij o if ito of if o of of of 0 1 1 of a{ 0 1 o|_o of of of o 1 1 Toa ee of ot of 0Verilog program for 3 x 8 DECODER: module dec2to4(in, en, y); input [1:0] in; input en; output [3:0] ys wire [1:0] w; wire w1,w2,w3,w4: not n1(w{0], in[0]); not n2(w{1], in[1]); and al(w1, w{0], w[1]); and a2(y{0], wl, en); and a4(y[1], w2, en); and aS(w3, wf0], in[1]); and a6(y[2], w3, en); and a7(we, in[0], in[1]); and a8(y[3], w4, en); endmodule module dec3to8(in, y); input [2:0] in; output [7:0] y: wire w; not nl (w, in{2]); dec2tod dl (in{1:0], w, y[3:0]); dec2to4 d2(in[ 1:0], in[2], y[7:4]); endmodule Verilog test bench program for 3 x 8 DECODER: module th_dec3t08; reg[2:0] in; wire [7:0] y; integer i; dec3to8 uut(in, y); initial begin for(i=0; 18; 1=1+1) begin fin} = ig20; initial beginSdumpfile("test.ved"); Sdumpvars(1); #200 Sfinish; end endmodule Result: Designing of 3 to 4 decoder in gate level modeling with enable input and inst it 3 to 8 decoder using structural modeling and verifying the functionality of design with the help of test bench is completed4x16 DECODER USING 2x4 DECODER Ai © Design 2 t0 4 decoder in dataflow modeling with enable input and inst it to design 4 to 16 decoder using structural modeling and verify the functionality of the design using test bench, DECODER Theory: A decoder is a cou iativnal logic circuit which is used to change the code into a set of signals. It is the reverse process of an encoder. A decoder circuit takes multiple inputs and gives multiple outputs.A decoder circuit takes binary data of ‘n’ inputs into “2°n’ unique output. In addition to input pins, the decoder has a enable pin. This enables the pin when negated, makes the eireuit inactive. 4 To 16 DECODER Block Diagram: a vl vo}, Law ae al = [ror a vel 0 sh oe fe 20) wo * rl a wa be [oe au st ae [wot Oo rm 1 wen at w oe tual “ [ust 4 (016 Decoder - Truth Table: Tas Ta2] Tal] Tn0] en YUIS0] x = x x 0 (0000000000000000 0 0 0 0 I 0900000000000001 ov 0 a T T ‘0900000000000010 v v T 7 T THOTHHOOOVVVOTOD 0 0 1 i 1 0000000000010. 0 T 0 o I ‘0900000000010000 0 T 0 T I ‘ToOHHHOOOOTOOOOT 0 T T 7 T ‘THOHHHOOOTOOOOO, 0 T 1 T T ‘0000000070000000 T 7 v 7 T THHTHHOTOOVVOVT0000001000000000 ‘0000010000000000 0000100000000000 ‘0001000000000000 ‘0010000000000000 | =|-|_]elele H|-lele]a}Hle Sesocce 0100000000000000 T000000000000000 Verilog program for AND gate: module dec2to4(in, en, y); input [1:0] in; input en; output [3:0] y; assign y[0] = ((~in[0}) & (~in[1]) & en); assign y[1] = ((in{0]) & (~in[1]) &en); assign y[2] =((in[1]) & (~in[0]) & en); assign y[3] = ((in[0]) & (in{1]) & en); endmodule module dec4to16(in, y); input [3:0] in; output [15.0] y, wire [3:0]w; dec2to4 d(in[3:2], 1, w); dec2to4 d2(in{1:0], wl], y[3:0]); dec2io4 d3(in[1:0], w{1], yf7:4]); dec2to4 d4(in{ 1:0}, w(2], y{11:8]): dec2tod d5(in{1:0], w[3], y{15:12]); Verilog test bench program for AND gate: module th_dec4to16; reg [3:0] in; wire [15:0] y; integer i; dec4to16 uut(in, y); initial begin for(i=0; i<16; i= i+1) begin {in} =i; #20; endegin Sdumpfile("test.ved"); Sdumpvars(1); #4008finish; end endmodule Result: Designing of 2 to 4 decoder in dataflow modeling with enable input and inst it to design 4 to 16 decoder using structural modeling and verifying the functionality of the design using test bench is completed8x3 ENCODER © Design 4 to 2 encoder in dataflow modeling with enable input and inst it to design 8 to 3 encoder using structural modeling and verify the functionality of the design using testbench. Logic gates Theo An Encoder is a combinational circuit that performs the reverse operation of Decoder. Ithas maximum of 2°n input lines and ‘n’ output lines, hence it encodes the information from 2/n inputs into ann-bit code. It will produce a binary code equivalent to the input, which is active High. Therefore, the encoder encodes 2”n input lines with ‘n’ bit. & x 3 ENCODER - Block Diagram v— >| us >| [pw — . 8:3 Encoder |}———>"" v——>| rv——>| [0 n ——>| yo} 8x3 ENCODER - Truth Table: INPUTS ‘OUTPUTS a ) | a TTT Tee e777 Verilog program for 8x3 ENCODER gate: module ene4to2(in, en, y, v); input [3-0] in: input en; output [1:0] y; output v; assign y[1] = (in{3] +in[2])*en; assign y[0] = (in[3] | in[1])*en;assign v= (in[0] + in[1] + in[?] + in[3])"en: endmodule module enc8to3(in, en,y); input [7:0] in; input en; output [3:0] y; wire [1:0] wl,w2; wire w; enedto2 e2(in{7:4], en, w1[1:0}, y{2)); encdta? el (in[3:0], en, w2[1:0], w); assign y[0] = wl [0] + w2{0]; assign y[1] = wi[1] + w2[1]; endmodule Verilog test bench program for 8x3 ENCODER gate: module th_enc8to3; reg [7:0] in; reg en; wire [2:0ly; enc8to3 uut(in, en, y); integer i; initial begin en = 0; for(i=0; i<8; i=i+1) begin #20 en = 1; {in} =2**i; end end initial begin Sdumpfile("test.ved"); Sdumpvars(1); #180 Sfinish, End endmodule ing of 4 to 2 encoder in dataflow modeling with enable input and inst it to design 8 103 encoder using structural modeling and verifying the functionality of the design using testbench is completed.Experiment No. 10: DESIGN OF FLIP-FLOPS USING BEHAVIORAL MODELLIN' Aim: © Design JK-FF, SR-FF, D-FF and T-FF with synchronous reset and asynchronous reset using behavioral modeling andverify the functionality of the design using test bench. Flip FlopsTheory: A flip-flop is a circuit that has two stable states and can be used to store state information. The circuit canbe made to change state by signals applied to one or more control inputs and will have one or two outputs. Itis the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks ofdigital electronics systems used in computers, communications, and many othertypes of systems Boolean equations: JK- Flip-Flop: Qn+1=Qn’J+Qnk’ SR- Flip-Flop: On+1=S+QnR” T — Flip-Flop: Qn+1=T*Qn D - Flip-Flop: Qn+1=D Block Diagram: J Qa Qa a i : > y . y a a ‘a IK Q JK-FIipFlop SR: FilpFlop Bemipniop T-FlipFlop Truth Tables: JK- FF SR- FF T-FF Clk | T yn ] X| QnFLIP-FLOPS WITH SYNCHRONOUS RESET JK Fliy Flop with Synchronous Reset Verilog test bench program for JK FlipFlop: Verilog program for JK FlipFlop: module th_jkff; reg j,kelk.rst; wire q.qbar: jkfF uut(j kyelk,rst,q.qbar); always #5 clk=~clk: initial begin clk=0; rst=0; j=0;k=0; #20 rst=1; #20 rst=0; #20 {j,k}=2'01; #10 {j,k}=2'b10;, #10 {j.k}=2’b11; end Initial begin Sdumpfile("test.ved"); Sdumpvars(1); #100 $finish; end endmodule module jkff(j,k,clk.rst,q.qbar); input j,k,clk,rs output q,qbar; reg 4; always@(posedge clk) begin iffrst) q=1'b0; else case({j,k}) 2600: q=q: 2'b01: q=0; 2'b10:q=1 2'b1L 5 default: q=1'bx; endease end assign qbar—~q; endmoduleSR Flip-Flop with Synchronous Reset Verilog test bench program for SR Flip-Flop: Verilog program for SR Flip-Flop: module th_srff, reg s,r,clktst; wire q.qbar; srff uut(s,t,clk,tst,q,qbar); always #5 clk=~clk; initial begin clk=0: rst=0; s=0; 0 rst #20 rst-0; #20 {s,r}=2'b01; #20 {s,r}-2'b10; #20 {s,r}=2'b11; end initialbegin Sdumpfile("test.ved"); Sdumpvars(1); #120 Sfinish; end endmodule module stff(s,r,clk,rst,q,qbar); input s,relk,rst, output q.qbar; reg q; always@(posedge clk)begin iffest) q=1'b0; else case( {s.t}) 200: q=q 2'b01:q-0; 2'b10: q= 2'b11: qrl'bx; default: ¢=1'bx; endease end assign qbar=~q; endmoduleD Flip-Flop with Synchronous Reset Verilog test bench program for D Flip-Flop: Verilog program for D Flip-Flop: module tb_dffireg d,clk,rst, module Dff(d,elk,rst,q,qbar); wire q.qbar; input d.clkrst, Déff uut(dclk,rst,q,qbar), output q.qbar, always #5 clk=~clk; reg q; initial always@(posedge clk) begin be clk=0; rst=0;d=0;420 rst=1; if(rst) q=1"b0; #20 rst-0; else case(d) #10d-1'b0; 1'b0: q-0; #10d=I'b1; Vbl:q=1; #40 d=1'b0; default: q=1'bx; #40 d=1'b1; endcase end end Initial begin assign qbar=~q; Sdumpfile("test. ve Sdumpvars(1);#200 Sfinish; endmodule end endmodule1 Flip-Flop with Synchronous Reset Verilog test bench program for T Flip-Flop: Verilog program for T Flip-Flop: module tb_tff, module Tiitt.clk,tst,q,qbar); reg t,clk,tst input telk,rst; wire q,qbar; output q,qbar, reg q; Tif uut(t.clk,tst,q,qbar); always@(posedge clk) always #5 clk=~clk; begin initial iffest) begin q=l'b0; clk=0; rst=0;t=0; else 0 rst=1; case(t) #20 rst-0; 1'00: g=q; 1'b1: q=~a; #10 t=1'b0; default: q=1"bx; #10 t=I'bl; endcase #40 end #40. assign qbar=- end initial endmodule begin Sdumpfile("'test.ved"); Sdumpvars(1); #200 Sfinish; end endmoduleFLIP-FLOPS WITH ASYNCHRONOUS RESET JK Flip-Flop with Asynchronous Reset Verilog test bench program for JK Flip-Flop Verilog program for JK Flip-Flop: moduletb_jkff, reg j,k,clk.rst;wire q,qbar; jkfF uut(j,k,clk.rst,q,qbar); always #5 clk—~clk; initial begin clk=0; rst=0;j=0; k=0; #201st=1; #20 rst=0; #20 {j,k}=2'b01; #20 {j,k}=2'b10; #20 {j,k}=2°b11; end initial begin Sdumpfile("test.ved"); Sdumpvars(1); #150 Sfinish; end endmodule module jkff(j.k,clk,tst,q,qbar); input jk,clk,rst; output q,qbar, reg q; always@(posedge clk or posedge rst) begin if{rst) q=I'b0; else case({j,k}) 2'000:q=9; 2'bO1: q=0; 210: q=1; 211: gq; default: q-1'bx; endcase end assign qbar—~q; endmoduleSR Flip-Flop with Asynchronous Reset Verilog test bench program for SR Flip-Flop: Verilog program for SR Flip-Flop module module srfifs,t.clk,rst,q,qbar); tb_srff, input s.r,clk,rst; reg sstelk,rst; output q,qbar; wire q,qbar; reg q; srff uut(s,r,clk,tst,q,qbar); always@(posedge clk or posedge rst) always #5 clk=~clk; begin snittal ifftst) q=1'b0; begin else clk=0; rst=0; s=0;1=0; case({s.t}) #20 1st-1; 2000: q-4; #20 rst=0; cr oe #20 {s,r)-2'b01; La a tee 2'b1 1: g=I'bx; ee default: q=1'bx; #20 {sr} endease ea end initial begin assign qbar=~q;, Sdumpfile("test.ved"); Sdumovars(); endmodule #120 Sfinish; end endmoduleD Flip-Flop with Asynchronous Reset Verilog test bench programfor D Flip-Flop Verilog program for D Flip-Flop’ moduletb_dffireg d.clk,rst; module Dff(d,clk,tst,q,qbar); wire q.qbar; input d.clk,rst; Déf uut(dclk,rst,q,qbar), output q.qbar; always #5 elk—~clk; reg q; initial always@(posedge clk or posedge rst) begin begi clk=0; rst=0;4=0; if{rst) q=I'bO; #9 rst=| else #10 rst=0; case(d) #10d=1'b0; 1'b0: g=0; #10d=1'bl; V'bl:q=1; #40 d=1'b0; default: q=1'bx; #40 d=1'bl; endcase end end initial begin assign qbar=~q; Sdumpfile("test.ved" Sdumpvars(1); endmodule #200 Sfinish; end endmoduleT Flip-Flop with Asynchronous Reset Verilog test bench program for T Flip-Flop: Verilog program for T Flip-Flop module th_tff; module Tfi(t,clk,rst,q,qbar); reg tclk,tst; input telk,rst; wire q.qbar; output q.qbar: reg q; TH uut(t,clk,rst,q,qbar); always @(posedge clk or posedgerst) always begin #5 clk—~clk, iffrst) initial q=l'b0; begin else clk=0; rst=0;t=0; case(t) #20 rst=1; iH I a ae aeeuale quis: q endease #10 1'b1; #40 t-1'b0; #40 11; end end assign qbar—~q; initial ee endmodule Sdumpfile("test.ved"); Sdumpvars(1); #200 Sfinish; end endmodule Result: IK, SR, D, T flip-flops with synchronous and asynchronous reset with behavioral modeling are designed and verified the functionality.Experiment No. 11: DESIGN OF COUNTERS IN BEHAVIORAL MODELLI Aim: © To design an up counter, down counter and up-down counter, decade counter, modN counter and ringcounter in behavioral modelling and verifythe functionality using Test bench. Theory: Up counters count upwards or incrementally. Down counters count downwards or in a decremental manner. Up-down counters can count bothupwards as well as downwards. Decade counter counts from 0 to 9 ‘The 2-bit ripple counter is called as MOD-4 counterand 3-bit ripple counter iscalled as MOD- 8 counter. So, in general, an n-bit ripple coumeer is called as modulo-N counter. Where, MOD number=2". Ring counteris a typical application of Shift resister. Ring counteris almost sameas the shift counter. The only change is that the output of the last flip-flop is connected to the inputof the first flip-flop in case of ringcounter. ‘Truth Table: Down counter: MSBQD_| OC g gl DecimalValue =e le [2[e F211] [2 []9 elelele/ leilaUp counter: ‘Nini 0 u 2 “ cy Up-down counter: c eS * ° « S a 3 3Decade counter- Mod 10: Clock Output bit Pattern: D oe Do ec BC QA, Value 1 ° ° o ° ° 2 ° o ° 1 1 3 ° ° 1 ° 2 4 ° ° 1 1 3 s ° 1 ° ° 4 6 ° 1 ° 1 5 a ° 1 1 ° 6 8 0 1 1 1 7 9 1 ° o ° 8 10 1 ° o 1 ° u Counter Resets its Outputs back to Zero Ring counter: 1 |oO |o/0 o [1 [o|o Oo |0|1 0 o fo fo]fi Verilog code: Up counter: Design: Module upcounter(clk,tst,q); input clk,rst; output[3:0] q; reg[3:0] q; always@(posedge clk) begin if{est) q-4'b0000; else «rq*4'b0001; cud endmoduleTest bench: module tb_upcounter; reg clk.rst; wire[3:0] q; always #5 elk=~clk; upcounter uut(clk,tst,q); initial begin clk-0; tial begin Sdumpfile("test.ved"); Sdumpvars(1);#200 Sfinish; End endmodule Down counter: Design: module downcounter(clk,tst,q); input clk,rst; output{3:0] q; reg[3:0] q; always@(posedge clk) begin ifrst) q=4'b0000; else q=q-4'b0001; end endmodule ‘Test bench: module tb_downcounter; reg clk,tst, wire[3:0] 4; always #5 elk=~clk; downcounter uut(clk,st,q); initialbegin clk=0; 18-0, initial begin Sdumpfile("test.ved"); Sdumpvars(1); #200 Sfinish; end endmodule UP-DOWN counter: Desig module updowncounter(cikst,inode,q), input clk,tst,mode; output[3:0] q; reg[3:0] q: q-a-4'00001; else ra 4'b0001; end endmodule ‘Test bench: module tb_updowncounter, reg clk,tstmode; wire[3:0] 4: always #5 elk—~clk; updowncounter uut(clk,rst,mode,q); initial begin clk=0; rst=0; mode-0; #10 1st=1; #10 sst-0; #60 mode=1; end initial begin Sdumpfile("test.ved"); Sdumpvars(1); #300 Sfinish;end endmodule Decade counter: Design: module decade_connt(clk,rst.q): input elk.rst; output{3:0] q; reg[3:0] q; always@(posedge clk) begin if(rst | q-—4'b1001)q~4'b0000; else =q*4'00001; end endmodule Test bench: module tb_decade_count; reg clk,rst; wire[3:0] 4: always #5 elk—~clk; decade_count uut(clk,tst,q); initial begin clk=0; rst=0; #10 rst=1; #10 rst=0; end initial begin Sdumpfile("test.ved"); Sdumpvars(1); #200 Sfinish; end endmodule Ring counter: Desig module ringcounter(clk,tst,q); input clk,rst; output{3:0] q; reg[3:0] q; always@(posedge clk) beginif(rst || q==4'b0001)q=4'b 1000; else rel: end endmodule Test bench: module th_ringcounter;reg clk.rst; wire[3:0] always #5 clk=~clk; ringcounter uut(clk,rst,q); initial begin clk=0; rst=0; #10 rstI; #10 rst-0; end initial begin Sdumpfile("test.ved"); Sdumpvars(1); #200 Sfinish; end endmodule Mod N counter: Desig module modN_count(clk,rst,mod,q); output{3:0] q; reg[3:0] q: always@(posedge clk) begin if(rst || q==(mod-1))q=4'b0000; else q-q+4'b0001; end endmoduleTest bench: module th_modN_count;reg clk,rst; reg[3:0] mod; wire[3:0] q: always #5 clk=~clk; modN_ count wut(clk,rst,mod,q); initial begin clk=0; 13t0; mod=4'b1 110; #10 rst=1;, #10 rst-0; end initial begin Sdumpfile("test.ved"); Sdumpvars(1); #200 Sfinish; end endmodule Result: Designing ofan up counter, down coun + and up-down counter, decade counter, mod N counter ad ring counter in behavioral modelling and verifying the functionality using test bench is complete.