Sri Sai Cherukuri

Gainesville, FL | (205) 899-0252 | srisai.cherukuri@ufl.edu | https://www.linkedin.com/in/srisai-cherukuri/

Summary: Electrical and computer engineering master's graduate with a specialization in VLSI. In-depth knowledge of digital IC design and physical design,
showcasing a comprehensive understanding of hardware systems. Proficient in HDL coding, silicon design, EDA tools, Front End development (designing and verifying
chips), and FPGA prototyping. Skilled in utilizing simulation and synthesis tools like Xilinx Vivado and ISE Design flow. Also, practical experience in semiconductor
fabrication and a successful internship in RTL design. Enhanced by effective interpersonal skills for seamless team collaboration. Certified in Python by Microsoft in
2021 (MTA: Introduction to Programming Using Python).
EDUCATION
Master of Science, Electrical and Computer Engineering Aug 2021 – May 2023
University of Florida Gainesville, FL
• Academic Achievement Award Scholarship Recipient.
• Coursework: Advanced VLSI Circuits and Technology, System-on-Chip(SoC) Design, Computer Architecture, Re-configurable Computing,
Introduction to RF Circuits, Analog IC Design, Future of Microelectronics Circuits, Semiconductor Device Fabrication Laboratory.
Bachelor of Technology, Electronics and Communication Engineering Jul 2016 – Jun 2020
Amrita School of Engineering Bengaluru, India
• Student Band ambassador for Amrita TBI (A non-profit startup incubator and accelerator).
• Coursework: VLSI System Design, Solid State Devices, Linear Integrated Circuits, Microprocessors, Computer Programming, Digital IC Desi gn,
Signal Processing, Embedded Systems, Microprocessor and Microcontroller.
TECHNICAL SKILLS
• Hardware Description Languages(HDLs): Verilog, VHDL and System Verilog. • Development Tools: Xilinx (Vivado and ISE Design Suite), ModelSim, Cadence
• Skills: ASIC Design, FPGA Prototyping, Static Timing Analysis, Low Power Virtuoso (DRC & LVS), Synopsys Design Complier, LabVIEW, and LTspice.
Design (power gating, clock gating), Timing, Power & Area Optimization, • Operating System: Linux and Windows.
Synthesis, VLSI Fundamentals, Verification using Testbench (System Verilog), • Programming Language: C, C++ and Python.
AMBA Protocol, and Basics of Fabrication.
WORK EXPERIENCE
Maven Silicon Jul 2020 – Sep 2020
RTL Design Intern Bengaluru, India
• Architected and executed the design of a SoC-based AHB – APB Bridge utilizing Verilog(ModelSim), ensuring seamless communication between AHB and APB
bus protocols.
• Translated complex design architectures and specifications into actionable development plans, demonstrating strong analytical and critical thinking ski lls.
• Performed a breakdown of the design into diverse components, including AHB slave, AHB-APB Bridge Top, AHB master, APB interface and FSM controller.
• Synthesized (Quartus) each block individually and simulated using the sequential style of coding and block instantiation individually.
• Conducted comprehensive testing and verification of the AHB to APB bridge design, performing read a nd write transfers to validate data bus functionality.
• Demonstrated expertise in Verilog HDL, ensuring robust RTL system coding, verification by creating testbenches, and enhancing proficiency in digital design
methodologies and adherence to specification standards.
• Prepared detailed technical documentation, including design specifications and test results, ensuring transparency in project progress and outcomes.
Bharat Heavy Electricals Limited May 2018 – Jun 2018
Summer Intern Hyderabad, India
• Conducted an in-depth study on Programmable Logic Controllers (PLCs) and their diverse applications in industrial machines.
• Explored a range of industrial scenarios where PLCs are employed, such as CNC machines, manufacturing lines, and robotic systems.
• Collaborated with a multidisciplinary team of engineers to ensure the successful integration of PLC technology into CNC machines.
• Created detailed documentation outlining PLC programming methodologies, integration steps, and machine performance improvements.

PROJECTS
Verification environment for SoC employing UVM - SystemC library Jan 2023 – May 2023
• Designed and verified a System-on-Chip using UVM (Universal Verification Methodology) and SystemC with a team of four students.
• Devised verification plans, designed test patterns, and implemented VIPs and the UVM environment for SoC design.
• Drafted technical reports, capturing intricate design specifications, and delivering detailed descriptions of the verification flow, facilitating seamless
collaboration across teams, and enabling efficient troubleshooting.
• Skills acquired are Hardware, UVM, Makefile and SystemC to keep up to date with the verification methodologies and design tools.
Floating point multiplier employing a combination of Karatsuba and UT algorithm Jan 2022 – Apr 2022
• Developed an efficient method to optimize delay and area for 32-bit IEEE754 floating-point multiplication using Verilog HDL and synthesized the design utilizing
Xilinx ISE Design Suite considering performance and efficiency by using a very efficient combination of Karatsuba and Urdhva-Tiryakbhyam algorithms.
• Researched various multiplication algorithms, including Karatsuba and Urdhva-Tiryakbhyam algorithms, to create an optimized multiplier design.
• Enhanced proficiency in Verilog programming, writing testbenches and digital logic design, as well as an understanding of multiplication algorithms.
Design and Analysis of SRAM block using 45nm technology node Aug 2021 – Dec 2021
• Designed a fully functional 5x4 SRAM cell schematic(CMOS) and layout using Cadence Virtuoso Tool with GPDK 45nm technology.
• Conducted comprehensive stability tests and measurements for a 5x4 SRAM cell design using the Cadence Virtuoso Tool, adhering to expected limits.
• Develop methodology and infrastructure to drive Performance, Power, and Area (PPA) improvements. Gate-level simulation and debugging.
• Mastered expertise in Silicon design, Cadence-Virtuoso, utilized Schematic and Layout design, implemented integrated circuits, and improved PPA.
Implementation of 1-D Time Domain Convolution that exploits parallelism in FPGA Aug 2021 – Dec 2021
• Architected and built an FPGA system utilizing VHDL, data(128 bit) retrieval from external memory residing in a separate time domain, executing Convolution
operations in parallel, and seamlessly saving processed data back to external memory.
• Developed an Address Generator with Counter, Signal and Kernel Buffers(128-bits) using required FIFO and Handshake protocols; enhanced system
performance by reducing data latency. Used predefined FIFO and necessary IP blocks.
• Acquired proficiencies in VHDL, FPGA design, CDC (clock domain crossing) and STA, ensuring the system met the required timing constraints.