4----------4----------------------------------------------------------------------

-- Nombre:Ronald Enrique Peña Sánchez

-- Documento:1010178276
-- Fecha:11/10/2023
-- Proyecto:Alto nivel
--------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity design is

Port ( A_Alu, B_Alurada1: in STD_LOGIC_VECTOR (1 downto 0);

Sel_Alu : in STD_LOGIC;
F_Alu > : out STD_LOGIC_VECTOR (1 downto 0)
);
end design ;

architecture Behavioral of design is

component Suma
Port ( A,B : in STD_LOGIC_VECTOR (1 downto 0);
F : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;

component Resta
Port ( A,B : in STD_LOGIC_VECTOR (1 downto 0);
F : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;

component Multiplexor
Port ( M0,M1 : in STD_LOGIC_VECTOR (1 downto 0);
Sel :in STD_LOGIC;
Z : out STD_LOGIC_VECTOR (1 downto 0)
);
end component;

-- Señales internas
signal Suma, Resta : STD_LOGIC_VECTOR (1 downto 0):= (others => '0');

begin

UO: Suma port map (

A => A_Alu,
B => B_Alu,
F => Suma
);

U1: Resta port map (

A => A_Alu,
B => B_Alu,
F => Resta
);
U2: Multiplexor port map (
M0 => Suma,
M1 => Resta,
Sel => Sel_Alu,
Z => F_Alu
);

end Behavioral;