ON Semiconductor

TL071C,AC
Low Noise, JFET Input TL072C,AC
Operational Amplifiers TL074C,AC
These low noise JFET input operational amplifiers combine two
state–of–the–art analog technologies on a single monolithic integrated LOW NOISE, JFET INPUT
circuit. Each internally compensated operational amplifier has well matched
high voltage JFET input device for low input offset voltage. The BIFET OPERATIONAL AMPLIFIERS
technology provides wide bandwidths and fast slew rates with low input bias
SEMICONDUCTOR
currents, input offset currents, and supply currents. Moreover, the devices
TECHNICAL DATA
exhibit low noise and low harmonic distortion, making them ideal for use in
high fidelity audio amplifier applications.
These devices are available in single, dual and quad operational
amplifiers which are pin–compatible with the industry standard MC1741,
8
MC1458, and the MC3403/LM324 bipolar products. 8 1
1

• Low Input Noise Voltage: 18 nV/ Hz Typ P SUFFIX D SUFFIX

• Low Harmonic Distortion: 0.01% Typ
PLASTIC PACKAGE
CASE 626
PLASTIC PACKAGE
CASE 751
• Low Input Bias and Offset Currents (SO–8)
• High Input Impedance: 1012 Ω Typ PIN CONNECTIONS
• High Slew Rate: 13 V/µs Typ
• Wide Gain Bandwidth: 4.0 MHz Typ Offset Null 1 8 NC
Inv + Input 2 7 VCC
• Low Supply Current: 1.4 mA per Amp
Noninvt Input 3 + 6 Output
VEE 4 5 Offset Null
TL071 (Top View)

Output A 1 8 VCC
2 7 Output B
Inputs A –
+
3 – 6
+ Inputs B
VEE 4 5
TL072 (Top View)

N SUFFIX
PLASTIC PACKAGE
CASE 646
14
(TL074 Only)
1

PIN CONNECTIONS

Output 1 1 14 Output 4
2 13
Inputs 1 –
+
–
Inputs 4
+
3 1 4 12
VCC 4 11 VEE
ORDERING INFORMATION
5 + + 10
Op Amp Operating Inputs 2 Inputs 3
Function Device Temperature Range Package 6
–
2 3 –
9
TL071CD SO–8 Output 2 7 8 Output 3
Single TA = 0° to +70°C
TL071ACP Plastic DIP TL074 (Top View)
TL072CD SO–8
Dual TA = 0° to +70°C
TL072ACP Plastic DIP
Quad TL074CN, ACN TA = 0° to +70°C Plastic DIP

 Semiconductor Components Industries, LLC, 2002 1 Publication Order Number:

March, 2002 – Rev. 2 TL071C/D
 TL071C,AC TL072C,AC TL074C,AC

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC 18 V
VEE –18
Differential Input Voltage VID ±30 V
Input Voltage Range (Note 1) VIDR ±15 V
Output Short Circuit Duration (Note 2) tSC Continuous
Power Dissipation
Plastic Package (N, P) PD 680 mW
Derate above TA = 47°C 1.0/θJA 10 mW/°C
Operating Ambient Temperature Range TA 0 to +70 °C
Storage Temperature Range Tstg –65 to +150 °C
NOTES: 1. The magnitude of the input voltage must not exceed the magnitude of the supply voltage or
15 V, whichever is less.
2. The output may be shorted to ground or either supply. Temperature and/or supply voltages
must be limited to ensure that power dissipation ratings are not exceeded.
3. ESD data available upon request.

ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = Thigh to Tlow [Note 1])

Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k, VCM = 0) VIO mV
TL071C, TL072C – – 13
TL074C – – 13
TL07_AC – – 7.5
Input Offset Current (VCM = 0) (Note 2) IIO nA
TL07_C – – 2.0
TL07_AC – – 2.0
Input Bias Current (VCM = 0) (Note 2) IIB nA
TL07_C – – 7.0
TL07_AC – – 7.0
Large–Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL V/mV
TL07_C 15 – –
TL07_AC 25 – –
Output Voltage Swing (Peak–to–Peak) VO V
(RL ≥ 10 k) 24 – –
(RL ≥ 2.0 k) 20 – –
NOTES: 1. Tlow = 0°C for TL071C,AC Thigh = 70°C for TL071C,AC
0°C for TL072C,AC Thigh = 70°C for TL072C,AC
0°C for TL074C,AC Thigh = 70°C for TL074C,AC
2. Input Bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.

Figure 1. Unity Gain Voltage Follower Figure 2. Inverting Gain of 10 Amplifier

10 k

1.0 k
- -
VO Vin VO
+ +
Vin

RL = 2.0 k CL = 100 pF RL CL = 100 pF

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 TL071C,AC TL072C,AC TL074C,AC

ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit
Input Offset Voltage (RS ≤ 10 k, VCM = 0) VIO mV
TL071C, TL072C – 3.0 10
TL074C – 3.0 10
TL07_AC – 3.0 6.0
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 10 – µV/°C
RS = 50 Ω, TA = Tlow to Thigh (Note 1)
Input Offset Current (VCM = 0) (Note 2) IIO pA
TL07_C – 5.0 50
TL07_AC – 5.0 50
Input Bias Current (VCM = 0) (Note 2) IIB pA
TL07_C – 30 200
TL07_AC – 30 200
Input Resistance ri – 1012 – Ω
Common Mode Input Voltage Range VICR V
TL07_C ±10 15, –12 –
TL07_AC ±11 15, –12 –
Large–Signal Voltage Gain (VO = ±10 V, RL ≥ 2.0 k) AVOL V/mV
TL07_C 25 150 –
TL07_AC 50 150 –
Output Voltage Swing (Peak–to–Peak) VO 24 28 – V
(RL = 10 k)
Common Mode Rejection Ratio (RS ≤ 10 k) CMRR dB
TL07_C 70 100 –
TL07_AC 80 100 –
Supply Voltage Rejection Ratio (RS ≤ 10 k) PSRR dB
TL07_C 70 100 –
TL07_AC 80 100 –
Supply Current (Each Amplifier) ID – 1.4 2.5 mA
Unity Gain Bandwidth BW – 4.0 – MHz
Slew Rate (See Figure 1) SR – 13 – v/µs
Vin = 10 V, RL = 2.0 k, CL = 100 pF
Rise Time (See Figure 1) tr – 0.1 – µs
Overshoot (Vin = 20 mV, RL = 2.0 k, CL = 100 pF) OS – 10 – %
Equivalent Input Noise Voltage en – 18 – nV/ √ Hz
RS = 100 Ω, f = 1000 Hz
Equivalent Input Noise Current in – 0.01 – pA/ √ Hz
RS = 100 Ω, f = 1000 Hz
Total Harmonic Distortion THD – 0.01 – %
VO (RMS) = 10 V, RS ≤ 1.0 k, RL ≥ 2.0 k, f = 1000 Hz
Channel Separation CS – 120 – dB
AV = 100
NOTES: 1. Tlow = 0°C for TL071C,AC Thigh = 70°C for TL071C,AC
0°C for TL072C,AC Thigh = 70°C for TL072C,AC
0°C for TL074C,AC Thigh = 70°C for TL074C,AC
2. Input Bias currents of JFET input op amps approximately double for every 10°C rise in junction temperature as shown in Figure 3. To maintain
junction temperature as close to ambient temperature as possible, pulse techniques must be used during testing.

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 TL071C,AC TL072C,AC TL074C,AC

Figure 3. Input Bias Current Figure 4. Output Voltage Swing

versus Temperature versus Frequency
100 35
RL = 2.0 k

VO, OUTPUT VOLTAGE SWING (Vpp )

30 TA = 25°C
IIB , INPUT BIAS CURRENT (nA)

VCC/VEE = ±15 V VCC/VEE = ±15 V (See Figure 2)

10
25

20 ±10 V
1.0
15

10 ±5.0 V
0.1
5.0

0.01 0
-100 -75 -50 -25 0 25 50 75 100 125 150 100 1.0 k 10 k 100 k 1.0 M 10 M
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz)

Figure 5. Output Voltage Swing Figure 6. Output Voltage Swing

versus Load Resistance versus Supply Voltage
40 40

VO, OUTPUT VOLTAGE SWING (Vpp )

RL = 2.0 k
VO, OUTPUT VOLTAGE SWING (Vpp )

VCC/VEE = ±15 V
TA = 25°C TA = 25°C
30
(See Figure 2) 30

20
20
10

10
5.0

0 0
0.1 0.2 0.4 0.7 1.0 2.0 4.0 7.0 10 0 5.0 10 15 20
RL, LOAD RESISTANCE (kΩ) VCC, |VEE| , SUPPLY VOLTAGE (±V)

Figure 7. Output Voltage Swing Figure 8. Supply Current per Amplifier

versus Temperature versus Temperature
40 2.0
VCC/VEE = ±15 V
VCC/VEE = ±15 V 1.8
VO, OUTPUT VOLTAGE SWING (Vpp )

ID , SUPPLY DRAIN CURRENT (mA)

35
(See Figure 2)
1.6
30 RL = 10 k
1.4
25 1.2
RL = 2.0 k
20 1.0

15 0.8
0.6
10 0.4
5.0 0.2
0 0
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)

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 TL071C,AC TL072C,AC TL074C,AC

Figure 9. Large Signal Voltage Gain and Figure 10. Large Signal Voltage Gain
Phase Shift versus Frequency versus Temperature
108 1000
VCC/VEE = ±15 V VCC/VEE = ±15 V
107 VO = ±10 V
RL = 2.0 k

VVOL, VOLTAGE GAIN (V/mV)

RL = 2.0 k

PHASE SHIFT (DEGREES)

VVOL, OPEN-LOOP GAIN

106 TA = 25°C
100
105
104 0°
Gain
103 45° 10
102 90°
Phase Shift
101 135°

1.0 180° 1.0

1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M -100 -75 -50 -25 0 25 50 75 100 125 150
f, FREQUENCY (Hz) TA, AMBIENT TEMPERATURE (°C)

Figure 11. Normalized Slew Rate Figure 12. Equivalent Input Noise Voltage
versus Temperature versus Frequency

en, EQUIVALENT INPUT NOISE VOLTAGE ( nV/ √ Hz )

1.20 70
VCC/VEE = ±15 Vdc
1.15 60 AV = 10
RS = 100 Ω
NORMALIZED SLEW RATE

1.10
50 TA = 25°C
1.05
40
1.0
30
0.95

0.90 20

0.85 10

0.80 0
-75 -50 -25 0 25 50 75 100 125 0.01 0.05 0.1 0.5 1.0 5.0 10 50 100
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz)

Figure 13. Total Harmonic Distortion

versus Frequency
1.0
THD, TOTAL HARMONIC DISTORTION (%)

VCC/VEE = ±15 V
0.5 AV = 1.0
VO = 6.0 V (RMS)
TA = 25°C
0.1

0.05

0.01

0.005

0.001
0.1 0.5 1.0 5.0 10 50 100
f, FREQUENCY (Hz)

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 TL071C,AC TL072C,AC TL074C,AC

Representative Schematic Diagram

(Each Amplifier) Bias Circuitry
Output Common to All
Amplifiers
VCC
Q4 Q5 Q2
Q3 Q1

Q6
- J1 J2
Inputs
2.0 k
+ Q17

Q20
J3
Q15 Q19 Q23
10 pF 24
Q14
Q21
Q22
Q24
Q12 Q13 Q16

Q10 Q9 Q8 Q25
Q11
Q7

Q18
Offset
Null 1.5 k 1.5 k
(TL071
only) VEE

Figure 14. Audio Tone Control Amplifier

10 k 100 k 10 k
Input

0.033 µF 0.033 µF VCC

10 k
-
TL071 Output
+
3.3 k
68 k VEE
0.033 µF 0.033 µF Turn-Over Frequency = 1.0 kHz
Bass Boost/Cut ±20 dB at 20 Hz
100 k Treble Boost/Cut ±19 dB at 20 kHz

Figure 15. High Q Notch Filter

-
R R TL071
Input +
C1

R1 f o
 1 
 350Hz
2
RC
R
 2R1
 1.5M
C C C
 C1
 300pF
2

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 TL071C,AC TL072C,AC TL074C,AC

OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K

8 5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
1 4 SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
F MILLIMETERS INCHES
DIM MIN MAX MIN MAX
NOTE 2 –A– A 9.40 10.16 0.370 0.400
L B 6.10 6.60 0.240 0.260
C 3.94 4.45 0.155 0.175
D 0.38 0.51 0.015 0.020
F 1.02 1.78 0.040 0.070
C G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
–T– J K 2.92 3.43 0.115 0.135
SEATING N L 7.62 BSC 0.300 BSC
PLANE M --- 10
--- 10

M N 0.76 1.01 0.030 0.040
D K
H G
0.13 (0.005) M T A M B M

D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE S

NOTES:
A D 1. DIMENSIONING AND TOLERANCING PER ASME
C
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
8 5 3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
E H 0.25 M B M
5. DIMENSION B DOES NOT INCLUDE MOLD
1 PROTRUSION. ALLOWABLE DAMBAR
4 PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
h X 45


MILLIMETERS
B e DIM MIN MAX
A 1.35 1.75
A A1 0.10 0.25
C B 0.35 0.49
SEATING C 0.18 0.25
PLANE D 4.80 5.00
L E 3.80 4.00
0.10 e 1.27 BSC
H 5.80 6.20
A1 B h 0.25 0.50
L 0.40 1.25
0.25 M C B S A S

0
7

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 TL071C,AC TL072C,AC TL074C,AC

OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE M NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M --- 10
--- 10

H G D 14 PL M N 0.015 0.039 0.38 1.01

0.13 (0.005) M

ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right
to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any
and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must
be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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TL071C/D
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