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Chapter 6 Crosstalk and Noise

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6.1 Overview
6.2 Crosstalk Glitch Analysis
6.2.1 Basics
6.2.2 Types of Glitches
6.2.3 Glitch Thresholds and Propagation
6.2.4 Noise Accumulation with Multiple Aggressors
6.2.5 Aggressor Timing Correlation
6.2.6 Aggressor Functional Correlation
6.3 Crosstalk Delay Analysis
6.3.1 Basics
6.3.2 Positive and Negative Crosstalk
6.3.3 Accumulation with Multiple Aggressors
6.3.4 Timing Correlation between attacker and victim network (Aggressor Victim Timing Correlation)
6.3.5 Aggressor Victim Functional Correlation
6.4 Timing Verification Using Crosstalk Delay
6.4.1 Setup Analysis
6.4.2 Holdup Analysis
6.5 Computational Complexity
6.6 Noise Avoidance Techniques
Zhihu Bible Link

This chapter describes the signal integrity (SI, Signal Integrity) issues of ASIC (Application Specific Integrated Chip) in nanotechnology . In deep
(submicron) technology, crosstalk plays an important role in the signal integrity of the design. Crosstalk noise refers to the unintentional coupling be
or more signals. Related noise and crosstalk analysis techniques, namely glitch analysis and crosstalk analysis, can be used in static timing ana
will be introduced in this chapter. These techniques can be used to make ASICs run stably.

6.1 Overview
Noise is considered an undesirable or unintentional phenomenon that affects the normal operation of a chip. In nanotechnology, noise can affect the
functions or devices.

Why noise and signal integrity?

Noise plays an important role in deep submicron technology for several reasons:

Increase in the number of metal layers : For example, a 0.25um or 0.3um process has four or five metal layers, while increasing to ten or mo
layers in 65nm and 45nm processes. Figure 4-1 in Chapter 4 has depicted the multi-layer structure of metal interconnect lines.

Vertically dominant metal aspect ratio : This means traces are both thin and tall, as opposed to being wider in earlier process geometries. Th
larger proportion of the capacitance is composed of sidewall coupling capacitance, which is the trace-to-trace capacitance between adjacent si

Higher wiring density : Due to finer geometry, more metal lines can be physically close together.

A large number of interactive devices and interconnect lines : More standard cells and signal traces are packed into the same silicon area
more interactions.

Faster waveform switching due to higher frequencies : Fast edge rates lead to more current spikes and greater coupling effects to adjacen
cells.
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Lower supply voltage : Reduction in supply voltage results in smaller noise margin.
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In this chapter, we specifically study the effects of crosstalk noise. Crosstalk noise refers to the unintentional coupling between two or more signals.
noise is caused by capacitive coupling between adjacent signals on a chip, which causes high and low switching of one network, causing unintende
the coupled signals. The affected signal is called the victim , and the affected signal is called the aggressor . Note that two coupled networks
each other, and often one network may be both a victim and an attacker.

Figure 6-1 shows an example of several signal traces coupled together, depicting the distribution of the extracted coupled interconnects.RC As wel
drive units and fan-out units. In this example, the networkn 1andN 2The coupling capacitance betweenC c 1 + C c 4,andC c 2 + C c 5It's the
andN 3coupling capacitance.

Broadly speaking, crosstalk introduces two types of noise effects: glitches , which are noise on a stable victim signal due to coupling of adjace
level switches; and timing changes (crosstalk delta delays). , cross-talk delta delay) caused by the coupling of victim level switching and
level switching . The next two sections describe these two types of crosstalk noise.

6.2 Crosstalk Glitch Analysis

6.2.1 Basics

A stable signal network may have glitches (positive or negative) due to charge transferred through the coupling capacitor when the attacker level sw
Figure 6-2 shows the positive glitch caused by crosstalk caused by the rising edge level switching of the attacker's network. Describe the coupling c
between two networks as a lumped capacitanceC cRather than distributed coupling capacitance, this is to simplify the following explanation withou
generality. In a typical representation of the extracted netlist, the coupling capacitances can be distributed across multiple segments, as shown prev
Section 6.1.

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In this example, the NAND gate unitU N A N D 0level switches and charges its output network (labeled "attacker"). Some charge also passes th
coupling capacitorC cis transferred to the "victim" network and causes positive glitches . The amount of charge transferred versus the coupling ca
between attacker and victimC cD. The charge transferred to the ground capacitance of the victim network causes glitches on that network. Due to t
unitI N V 2The pull-down structure transfers the charge and therefore restores a stable value (in this case a low level) on the victim net.

The magnitude of the glitch depends on a variety of factors, some of which are:

Coupling capacitance between attacker and victim: The larger the coupling capacitance, the larger the glitch amplitude;

The slew of the attacker's network: The greater the slew on the attacker's network, the greater the magnitude of the glitch. Typically, faster slew
the higher output drive strength of the unit driving the attacker's network;

Victim network ground capacitance: The smaller the ground capacitance on the victim network, the greater the magnitude of the glitch;

Victim network driving strength: The smaller the output driving strength of the unit driving the victim network, the greater the magnitude of the g

Overall, while stability is restored on the victim network, glitches still impact circuit functionality for the reasons stated below:

The glitch magnitude may be large enough that the fan-out unit can perceive it as a different logical value (e.g., logical0May be considered logi
fan-out unit1). This is especially important for sequential logic cells (flip-flops or latches) or memories, where glitches on the clock or asynchron
set/reset pins can severely impact design functionality. Similarly, glitches in the data signal at the latch input can cause incorrect data to be latc
glitches when inputting data can also have catastrophic consequences;

Even if the victim net does not drive the sequential logic unit, a wide/large glitch may propagate through the fan-out unit of the victim net to the
sequential logic unit, which will have catastrophic consequences for the design;

6.2.2 Types of Glitches

Burrs come in many different varieties.

Rise and Fall Glitches

The discussion in the previous subsection illustrates a rise glitch on a victim network that has been settling into a low level. A similar situation is the
of negative glitches on stable high-level signals. The attacker's network with level drop switching will cause falling glitches (Fall Glitch) on stable hig
signals.

Overshoot and Undershoot Glitches

What happens when a rising attacker network is coupled with a stable high-level victim network? There will still be a glitch that causes the voltage v
victim network to exceed its stable high level. This glitch is called an overshoot glitch. Similarly, when a declining attacker network is coupled to a st
level victim network, it will cause an undershoot glitch on the victim network.

All four glitch situations caused by crosstalk are shown in Figure 6-3:

As mentioned in the previous subsection, the glitch is determined by the coupling capacitance, the attacker's slew, and the drive strength of
network . The calculation glitch is based on the amount of current transferred
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2 by the

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networkRC interconnects, and the output impedance of the units driving the victim network. The detailed glitch calculation is based on the library m
relevant noise model is part of the standard cell library model described in Chapter 3, and the output dc_current model in Section 3.7 is related to th
impedance of the cell (3.7.3 Crosstalk Noise Analysis ( models for crosstalk noise analysis) ).

6.2.3 Glitch Thresholds and Propagation

How to determine if a glitch on the network can propagate through a fan-out unit? As mentioned in the previous subsection, whether glitches caused
attacker network coupling can propagate through fan-out cells depends on the fan-out cell and glitch properties (such as glitch height and glitch wid
analysis can be based on direct current (DC) or alternating current (AC) noise thresholds. DC noise analysis only examines glitch amplitude and is m
conservative, while AC noise analysis examines other properties such as glitch width and fan-out unit output loading. Various threshold criteria used
AC analysis of glitches are described below.

DC Threshold

DC noise margin is a check of glitch amplitude and refers to the DC noise limit of the input unit while ensuring correct logic functionality. For examp
as the input to the inverter unit remains atV I Lbelow the maximum value, the output can remain high (higher thanV O H minimum value). Simila
as the input remains atV I H above the minimum value, the output of the inverter unit can be held low (belowV O Lmaximum value). These limits
basedD C Transfer properties are obtained and can be recorded in the cell library.

V O H is considered logical1or high level output voltage range,V I Lis considered logical0or low level input voltage range,V I H is considered l
input voltage range,V O Lis considered logical0output voltage range. Figure 6-4 shows the input-output of an inverter unitD C Transmission chara
diagram:

V I L ma xandV I H minalso known asD C DC margin limits, based onV I H andV I LofD C The margin is the steady-state noise limit and
can be used as a basis for determining whether glitches will propagate through the fan-out unit. DC noise margin limits apply to each input pin of the
usually,D C The margin limits are separate for rising glitches (input low level) and falling glitches (input high level). The model for DC margin can be
as part of the cell library description. Glitch below the DC margin limit (for example, below the fanout pin'sV I L ma xrising glitches) cannot propa
through fan-out, regardless of the width of the glitch. Therefore, conservative glitch analysis checks whether the peak voltage level (of all glitches) m
fanout unit'sV I LandV I H level. Even if any glitches occur, as long as all networks can meet the requirements of the fan-out unitV I Lan
level, it can be concluded that the glitch has no impact on the functionality of the design (because the glitch does not cause any change
output) .

Figure 6-5 showsD C Example of margin limit. For all networks in the design,D C The noise margin can be fixed to the same limit value. You can se
maximum tolerable noise (or glitch) amplitude above which noise can propagate through the unit to the output pins. Typically, this check ensures tha
level is less thanV I L ma xor greater thanV I H min. Glitch height is usually expressed as a percentage of the power supply. Therefore, if the
margin is set to30 %, it indicates that any height greater than the voltage swing30 %of glitches will be identified as potential glitches that may prop
through the unit and affect design functionality.

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Not all amplitudes greater thanD C A glitch in the noise margin can change the unit's output. The width of the glitch is also an important consideratio
determining whether the glitch will propagate to the output. Narrow glitches at the input of a unit usually do not have any effect on the output of the u
D C The noise margin only uses a constant worst-case value regardless of the signal noise width. The example in Figure 6-6 provides a noise supp
level that is a very conservative estimate of the cell's noise margin.

AC Threshold

As mentioned in the above subsection, glitch analysisD C Margin limits are conservative because they are designed analytically under worst-case c
D C Margin limits do not check burr width and do not affect the proper operation of the design.

In most cases, the design may not pass conservativeD C Noise analysis. Therefore, the effect of the glitch must be verified against the glitch width
output loading of the unit. Typically, if the glitch is narrow or the output capacitance of the fan-out unit is large, the glitch will not affect normal functio
operation. The effects of glitch width and output capacitance can both be explained by the inertia of the fan-out unit. Typically, a single stage unit wil
input glitches that are much narrower than the delay through the unit. This is because in the case of a narrow glitch, the glitch will end before the fan
can respond, so a very narrow glitch will have no effect on the unit. Since the output load increases the delay through the cell, the effect of increasin
output load is to minimize the effect of glitches on the input, although this increases the cell delay.

AC noise suppression is shown in Figure 6-7 (for fixed output capacitance). Black shaded areas represent good or acceptable burrs because these
too narrow or too short, or both, and therefore have no impact on the functional behavior of the unit. Lightly shaded areas represent undesirable or
unacceptable glitches because these glitches are too wide or too tall, or both wide and tall, and therefore such glitches at the input of the unit affect
of the unit. In the extreme case of a wider glitch, the glitch threshold corresponds toD C Noise margin, as shown in Figure 6-7.

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For a given unit, increasing the output load increases the noise margin because it increases the inertial delay and the width of the glitches that can p
through the unit. The following example illustrates this phenomenon. Figure 6-8(a) shows an unloaded inverter cell with a positive glitch at its input.
glitch is higher than the unit's DC headroom and therefore causes glitches at its output. Figure 6-8(b) shows the same inverter unit with a certain loa
output end. At this time, the same input glitch at the input end will cause a much smaller glitch at the output end. If the output load of the inverter un
as shown in Figure 6-8(c), the output of the inverter unit will not have any glitches. Therefore, increasing the load on the output makes the unit more
noise propagating from the input to the output.

As mentioned above, it can be ignored belowA C Threshold glitches (in Figure 6-7A C noise suppression region), or the fan-out unit can be consid
immune to such glitches.A C The threshold area is dependent on the output load and glitch width. As mentioned in Chapter 3, noise immunity mode
other noise models ) include the aboveA C Effects of noise suppression, the model introduced in Section 3.7, propagated_noise in addition to mod
propagation through the unit, also includesA C The impact of noise threshold ( 3.7.3 models for crosstalk noise analysis ).
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If the burr is larger thanA C What happens to the threshold? When the burr amplitude exceedsA C In the case of a threshold, a glitch at the cell inp
produce another glitch at the cell output. The height and width of the output glitch are a function of the width and height of the input glitch and the ou
This information is represented in a cell library that contains detailed tables or functions for the output glitch amplitude and width as a function of the
glitch amplitude, glitch width, and output pin loading. Glitch propagation will be described in the model in the library propagated_noise , which has
introduced in detail in Chapter 3 propagated_noise .

In the above, we calculated glitches (and the propagation of glitches) at the output of the fan-out unit, performed the same checks on the fan-out ne
so on.

Although we have used the generic term "burr" in the discussion above, it should be noted that this applies separately to all types of burrs mentione
previous subsection: rising burrs (modeled by or in earlier models), propagated_noise_high falling noise_immunity_high burrs (modeled by
propagated_noise_low or in earlier models noise_immunity_low ), overshoot glitches (modeled by noise_immunity_above_high ) and undersho
(modeled by noise_immunity_below_low ( propagated noise; 3.7.4 other noise models) ).

In summary, different inputs to the unit have different limits on glitch threshold, which is a function of glitch width and output capacitance
high (glitch transition to low level) and input low level (glitch transition to high level) glitch), these limitations are independent. Noise analysis examin
peak as well as its width and analyzes whether it can be ignored or propagated into the fanout.

6.2.4 Noise Accumulation with Multiple Aggressors

Figure 6-9 illustrates the coupling that introduces crosstalk glitches on the victim network due to a single attacker network level switching. Often, the
network can be capacitively coupled to many networks. When multiple networks switch levels simultaneously, the impact of crosstalk coupling noise
victim network will be more severe due to multiple attackers.

Most coupling analyzes caused by multiple attacker networks consider the glitch effect caused by each attacker network and calculate the cumulativ
the victim network. This may seem conservative, but it does show that the victim network worst case scenario. Another way is to useRMS (Root Me
root mean square) method, usingRMS In this method, the glitch amplitude of the victim network is calculated by taking the root mean square of the
caused by a single attacker network.

6.2.5 Aggressor Timing Correlation

For crosstalk caused by multiple attackers, the analysis must consider the timing correlation of the attacker's network and determine whether multip
can level switch simultaneously. The STA obtains this information from the timing window of the attacker's network. During the timing analysis pro
earliest (earliest) and latest (latest) level switching times of the network will be obtained. These times represent the timing window in whi
network can switch within one clock cycle . Level switching windows (rising and falling) provide necessary information about whether the attacke
can switch together.

Depending on whether multiple attackers can level switch simultaneously will determine whether glitches brought by a single attacker to the victim n
should be combined. In the first step, glitch analysis calculates four glitches (rising, falling, undershoot, and overshoot) for each potential attacker. T
step is to combine the effects of glitches from individual attackers, and multiple attackers can combine them separately for each different type of glit
example, consider an attacker networkA 1,A 2,A 3andA 4coupled victim networkV . During the analysis process, it is possibleA 1,A 2andA 4wi
and overshoot glitches, while onlyA 2andA 3Will cause undershoot and falling burrs.

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Consider another example, when any of the four attacker networks switches levels, it causes a rising glitch. Figure 6-10 shows the timing window an
amplitude caused by each attacker's network. Based on timing windows, glitch analysis identifies the worst-case attacker combination that could ca
largest glitch. In this example, the level switching window can be divided into four areas, each of which shows the attacker network that may perform
switching, and the glitch magnitude caused by each attacker is also shown in Figure 6-10 . area1attacker networkA 1andA 2Level switching will oc
may result in glitch amplitudes of0.21
= 0.11 + 0.10. area2attacker networkA 1,A 2andA 3Level switching will occur, which may result in glitch
of0.30 = 0.11 + 0.10 + 0.09. area3attacker networkA 1andA 3Level switching will occur, which may result in glitch amplitudes of0.20 = 0.11
area4attacker networkA 3andA 4Level switching will occur, which can result in0.32 = 0.09 + 0.23burr amplitude.

Therefore, the area4have0.32The worst burr amplitude in this case. Note that analysis without timing windows would predict a total glitch amplitude
0.11 + 0.10 + 0.09 + 0.23, which may be too pessimistic.

6.2.6 Aggressor Functional Correlation

For multiple attackers, timing windows reduce pessimism in the analysis by accounting for different time periods during which different networks ma
switch. Additionally, another factor to consider is the functional correlation between the various signals. For example, the scan control signal only sw
levels in scan mode (DFT test mode) and remains stable while executing the normal function or task mode of the design. Therefore, during function
scan control signal does not cause glitches on any other signals, and the scan control signal is a possible attacker only during scan mode. In some
test clock and the functional clock are mutually exclusive, so the test clock can only be active during testing when the functional clock is turned off. I
designs, the logic controlled by the test clock and the logic controlled by the functional clock create two independent and unrelated sets of attackers
case, an attacker testing clock control cannot be combined with other attackers of functional clock control to perform worst-case noise calculations.
example of functional correlation is when two attackers complement each other (logically opposite). In this case, it is not possible for the signal and
complement to level switch in the same direction for crosstalk noise calculations.

The network is shown in Figure 6-11n 1with three other networksN 2,N 3andN 4Example of coupling. In functional correlation analysis, the funct
the network needs to be considered. hypothetical networkN 4is a constant (for example, a mode setting network), so although it is related to the ne
Coupled but not a networkn 1attacker. hypothetical networkN 2It is part of the debug bus and is in a stable state in functional mode. Therefore, the
N 2Nor can it be a networkn 1attacker. hypothetical networkN 3To transmit functional data, you can only use the networkN 3treated as a network
potential attackers.

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6.3 Crosstalk Delay Analysis

6.3.1 Basics

Capacitance extraction from a typical net in a nanometer design includes the effects of many adjacent nets, some of which are ground capacitances
others are traces that are part of other signal nets. The ground capacitance and signal capacitance are shown in Figure 6-1. In basic delay calculati
taking into account any crosstalk), all these capacitances are considered part of the total capacitance of the network. When adjacent networks are s
not switch levels), the inter-signal capacitance can also be considered a ground capacitance. When an adjacent network switches levels, the chargi
through the coupling capacitor affects the timing of that network. The equivalent capacitance between the networks can become larger or smaller de
the direction of the attacker's network level switching, as is illustrated by a simple example below.

1through capacitorC ccoupled to an adjacent network (labeled as the attacker network), and via th
As can be seen from Figure 6-12, the networkn
C g Ground. This example assumes the networkn 1Have a rising level transition at the output and consider different scenarios depending on wheth
attacker network is level switching at the same time.

The capacitive charge required to drive the unit may vary in each case, as discussed below.

1The drive unit will provide the charge so thatC g andC cCharge tov _. T
The attacker network is in a stable state: In this case, the networkn
the total charge provided by the driving units of this network is(Cg
+ Cc) ∗ V dd。这种情况可以进行基本的延迟计算，因为在这种情况下未考
者网络的串扰。表6-13中为此情况下在网络N 1电平切换前后Cg 和Cc中的电荷量：

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