15/11/2023, 17:33 Literacy in Digital Backend Knowledge Points - CTS (Part 1) - CSDN Blog

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Literacy of digital back-end knowledge points - CTS (Part 1)
bendandawugui Modified on 2023-01-07 18:49:27 1.2k reads Collection 28 Number of likes
Classification column: Digital IC Article tags: SOC design

Digital IC The column contains this content 48 Subscribe 30 articles S

The back-end plays a very important role in IC design like the front-end. It can even be said that an entry-level front-end design engineer’s unde
of timing is far inferior to that of a back-end design engineer. Therefore, those who want to better understand the circuit’s timing need to do the back
Later, or in large-scale designs, how to implement clock driving of DFF on the backend requires learning and understanding CTS, and these are als
skills for an excellent front-end designer.

Today we will learn about clock tree synthesis (CTS). This article is learned from Zhihu blogger. The original link is: Basic skills of digital backen
(Part 1) - Zhihu (zhihu.com)

I have been thinking about how to introduce CTS for a long time, and finally decided to divide it into several articles to introduce the entire proc
step. However, since CTS is a relatively complicated job in large projects, there may be a lot more things needed besides this article. Back-end des
engineers should care about it, but I still hope that beginners, through the next few articles in this column, can have a general idea of ​the basic proc
methods of CTS, so as to avoid being stuck in the confusion of not knowing how to start after getting a design. passive.

Closer to home, in the entire P&R process, there are two decisive steps for the PPA (power performance area) of design: Floorplan and CTS. H
actual projects, many people may work for several years without having the opportunity to do a more comprehensive CTS. On the one hand, the rea
P&R tools, especially the current ICC2 and innovus, can handle relatively simple clock trees very well. On the other hand, the reason is that for mos
who do not have access to TOP, harden block The internal clock structure is most likely relatively simple, which leads some students to still be unab
with complex clocks after doing several projects.

In response to this phenomenon, this article hopes to introduce the basic ideas and methods of CTS to everyone based on my own experience
the content here to be helpful to practical work when encountering complex clocks in the future, this article will be honored.

Clock tree synthesis, as the name suggests, is to synthesize the clock tree of the design. The main purpose is to enable each clock to commun
the DFFs (registers) they drive in the shortest possible time. For CTS, we have three indicators. Be able to do your best.

The latency of each clock to reach the sink (DFF) it drives is as short as possible;

The skew within each clock and between clocks with a timing relationship should be as small as possible;

The common path of each clock should be as long as possible;

For most P&R tools, the flow of CTS can be summarized in the following form:

pr
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15/11/2023, 17:33 Literacy in Digital Backend Knowledge Points - CTS (Part 1) - CSDN Blog
There may be some names in the picture above that are not clear about their specific meanings, but these will be mentioned one by one in the
blog download study Community GitCode InsCode Log in Member 11.11 infor
introduction. Most of the words are not translated into Chinese here, so I hope you can remember these nouns for ease of reading. There are fewer
when using the English user guide.

CTS strategy

This is the first step of CTS. Although there are only a few words in the process, for complex clocks, it may take a lot of time to analyze the struct
clock, find out potential problems and bottlenecks, and target us The three indicators proposed above determine how to synthesize the clock tree. T
so important and easy to be ignored, so that some students have no way to analyze when they encounter complex clock problems, let alone how to
them. I will use an example below. To explain, what exactly is the CTS strategy?

Assume that the clock structure of a certain chip can be simplified to the following form:

The fucntion clock comes in from two PLLs and two IOs (one FCLK1, FCLK2), and the test clock comes in from two IOs (TCLK1, TCLK2). As can b
the figure, after the frequency division circuit, enter A and D clock is not shared with other modules.

At the same time, we assume that the floorplan of the chip can be expressed as follows (note the correspondence between the clock source an
position and the clock structure)

If the data flow relationship between modules is briefly described as follows:

Block B <—> Macro 1

Block C <—> Macro 2

Macro 1 <—> Macro 2

Block A/D is an independent module

Considering the above clock structure, floorplan and timing relationship, how should we decide the CTS strategy?

Before considering the strategy, let us first recall the three goals of CTS: latency is as short as possible ; skew is as small as possible ; commo
as long as possible; pr
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Let’s start with the simplest: Since Block A/D is an independent module, they do not have a timing relationship with other modules. At the same time
clock structure diagram, we can see that the clock entering A/D does not intersect with other modules after selection. Therefore, we only need to ma
clocks of A and D as short as possible.

We can also leave everything to the EDA tool, but the result of this cannot guarantee that we will get the results we want. The best way is to divide
selectors entering the two Blocks A and D and other clock frequency dividers. The logic is fixed near these two blocks (purple area in the figure belo
not only allows the clock line to reach the block in the shortest distance possible, but also increases the length of the common path as much as pos

Next, consider Block B/C and Macro1 and 2. In view of the temporal relationship between them, we hope that the skew between them should be as
possible, and the common path should be as long as possible. We can see that they are visited on the floorplan. In a symmetrical form, the simples
direct way is to fix all the logic related to these in the middle of the two Macros (assuming that the clock port is in the yellow marked part), as shown
box in the figure below Shown:

So far we have determined the logic that needs to be preplaced and the area where it is placed. Next we need to consider how to implement our vis
first task is to define the sdc of CTS.

For CTS tools, a necessary prerequisite for clock tree synthesis is the definition of clock. Back-end designers can adjust the definition of clock acco
own strategies. Let us discuss the structure diagram of clock again. .

For the above structure, there are two commonly used methods to define Clock (time unit ps)

1: Define directly from the source of all clocks. This method can basically copy the definition of clock directly from the sdc of func/test:

creat_clock-period xxx -name PLL_CLK [get_pins PLL1/CLK];

2: Use the segmented CTS method, because most clock structures are relatively simple starting from the selector, so we can define a series of cloc
output end of the selector and balance the parts that have some relationship; then start from Each clock source is defined and stopped at the
selector when the clock tree is synthesized. The clock definition of this method can be roughly divided into the following two parts.
pr
The first section: Selector output—>Each Block bendandawugui focus on

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15/11/2023, 17:33 Literacy in Digital Backend Knowledge Points - CTS (Part 1) - CSDN Blog
create_clock-period xxx -name MUXCLK1 [get_pins MUX1/Y]
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create_clock-period xxx -name MUXCLK1 [get_pins MUX2/Y]

........

Second paragraph: clock source —> each selector

creat_clock-period xxx -name PLL_CLK [get_pins PLL1/CLK];

........

As for how to make the tool stop at the selector, we will continue to discuss it in the next article. At the same time, we will reflect the above ideas an
through real scripts and commands. I hope everyone will continue to pay attention.

In addition, the design designed in this article can understand the relatively detailed clock structure through the above pictures, but in actual design,
know the structure and timing relationship of the clock in advance? Generally speaking, for large companies with well-established processes, drawin
detailed overall structure is one of the tasks of front-end design. However, in actual projects, the clock structure diagram of most designs may be ve
even completely absent. This is At this time, back-end engineers need to be more patient to analyze the design, and actively communicate with the
constraint designers, so as to quickly grasp the clock structure of the design.

At this point, the CTS strategy is basically completed. In the following articles, we will continue to discuss in detail the implementation methods of th
strategies and how to view the results of the debug clock.

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