A Low-Power Programmable DLL-Based Clock Generator

with Wide-Range Anti-harmonic Lock

Yongtae Kim Phi-Hung Pham Woonhyung Heo and Jabeom Koo

Department of Electrical and Faculty of Electronics and Department of Electronics and
Computer Engineering Telecommunication Computer Engineering
Texas A&M Vietnam National University Korea University
Texas, USA Hanoi, Vietnam Seoul, Korea
fcore4@tamu.edu hungpp@vnu.edu.vw hwh, kjb@kilby.korea.ac.kr

increase the operating frequency range. The proposed anti-

Abstract— A delay-locked loop (DLL)-based clock generator for
dynamic frequency scaling has been developed in a 0.13um harmonic circuit uses only two clock phases of a single
CMOS technology. The proposed clock generator can generate a
wide-range of the multiplied clock signals ranging from 125MHz
to 2GHz. In addition, thanks to the proposed anti-harmonic lock
block, the clock generator can change the frequency dynamically
in one cycle time of the reference clock. The proposed DLL-based
clock generator occupies 0.019mm2 and consumes 21mW at
2GHz. The ratio of power consumption to frequency of the
proposed clock generator is smaller than those of conventional
ones.

Keywords- Anti-harmonic lock, Frequency multiplier

I. INTRODUCTION
There has been a great deal of interest in low power and
low-jitter clock generators. In recent years, delayed-locked
loop (DLL)-based clock generators have been used in portable
mobile applications, clock and data recovery, and
microprocessors, because they exhibit less jitter and phase
noise compared to phase-locked-loop (PLL)-based counter
parts [1]-[9]. However, in conventional DLL-based clock
generators, the power consumption of the frequency multiplier
is large compared to the other blocks; it may use almost half
of the total power [5]. Also, it requires many AND gates to
generate the multiplied clock, which results in poor jitter
performance and a large area. In this paper, a simple
frequency multiplier is proposed to decrease the power
consumption and to reduce the accumulated jitter through the
frequency multiplier itself.
To avoid a harmonic locking, the initial delay of the
voltage controlled delay line (VCDL) must be located between
0.5Tref and 1.5Tref independent of the initial control voltage of
the VCDL, where Tref represents the reference signal period
[7]. In a conventional anti-harmonic lock block, only the
locations of the multiphase clocks are checked. If the number
of clock phases is increased, power consumption is also
increased. Also, if the delay range of the VCDL is large so
that the input clock can be delayed to 3Tref or more, then it is
hard for the anti-harmonic lock block to recognize if the DLL
is locked correctly or not. In addition, the anti-harmonic lock
detector is often a bottleneck for high-speed operation. In this
paper, a wide-range anti-harmonic lock block is proposed to
Figure 1. Block diagram of the proposed DLL based Frequency Multiplier.
multiphase clock and it can detect whether the DLL is in the
harmonic lock state or not over a wide range. Furthermore, as
the proposed anti-harmonic lock block uses only two
multiphase clocks, it reduces the power consumption.
The overall architecture of the proposed clock generator is
described in Section II and its implementations are presented in
Section III. In Section IV, experiments results, a die photo, and
a performance comparison are presented. Finally, the paper is
concluded in Section V.
II. OVERALL ARCHITECTURE
The block diagram of the proposed DLL-based clock
generator is shown in Figure 1. The DLL-based clock
generator consists of the proposed anti-harmonic lock block
and a frequency multiplier.
The VCDL consists of nine delay cells, each implemented
differentially for better noise rejection. When the DLL locks,
the VCDL generates uniformly spaced clocks which are
buffered for the input of the frequency multiplier. The
proposed clock generator can generate four kinds of multiplied
output clocks and by using the 2-bit control signals, one clock
signal is selected. Among the nine buffered clocks, the B4 and

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 B9 clocks are selected as inputs for the anti-harmonic lock
block to detect whether the DLL is harmonically locked or
not. The proposed anti-harmonic lock block generates two
signals (forceup and forcedn) that make the phase detector
(a)
(b)
Figure 2. (a) The frequency multiplier block (b) Timing diagram of the
frequency multiplier.
generate UP or DOWN signals respectively. These signals
increase or decrease the control voltage of the VCDL so that
the B9 clock is located between 0.5Tref and 1.5Tref, and then
the forceup and forcedn signals go low to make the phase
detector operate normally.
III. IMPLMENTATION
A. The proposed frequency multiplier.
The proposed frequency multiplier uses the phase delay of
the multiphase clocks. When the DLL is locked, there are
multiphase clocks and the delay of each of the adjacent clocks
is the same and this delay is used for generating a pulse. As
shown in Figure 2, the rising edge of the first multiphase clock
(B<0>) makes the D flip-flop output go ‘High’ until the rising
edge of the second multiphase clock (B<1>) activates the reset
of the D flip-flop. When the reset is activated, the output of
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the D flip-flop returns to zero. Otherwise, the rising edge of
the second multiphase clock (B<1>) makes the other D flip-
flop output go “Low” and the third rising edge of the
multiphase clock (B<2>) activates the reset. This reset forces
the output of the other D flip-flop to go ‘High’. These
operations create the pulses (Q1 and Q2), which are fed to the
NMOS or PMOS of the combination block. When combining
these pulses, the conventional multiplier used many logic
gates [4],[5]. The proposed frequency multiplier needs less
logic, so it can decrease the area and power consumption. As
mentioned previously, the phase delay of adjacent multiphase
clocks is used to generate pulses. This pulse width is identical
to the phase delay. These pulses are selected by the control
logic and fed to the combining circuit as shown in Figure 2.
T1 and T2 are the pulse width of Q1 and Q2 respectively. The
Q1 pulse is fed to the gate of one of the NMOS transistors.
During the T1 pulse width, the NMOS turns on and discharges
the output until the output node voltage reaches ‘0’. For the T2
pulse width, the Q2 pulse goes to the gate of the pmos and
charges the output node to the 1.2V supply voltage. The
operation stated above generates the multiplied clock. To
match the loading on Q1, Q2 … Q8, dummy buffers are added.
Decoupling capacitors are added to the frequency multiplier to
reduce the power supply noise.
This DLL-based clock generator does not have any duty
correction circuit. Hence, it seems that it cannot guarantee a
50% duty ratio; however, when the DLL locks so that each
phase delay is identical, the pulse widths are also equal, which
guarantees a 50% duty ratio, which means that the pulse
widths of T1 and T2 are identical. The 50% duty ratio can be
achieved by all frequency multiplication ratios of the proposed
DLL. Of course, if the DLL is in the harmonic lock state, then
the pulse width changes and when the DLL does not lock, the
pulse widths can be overlapped. That does not guarantee the
50% duty ratio and it is possible that the nmos and pmos can
turn on simultaneously. In that case, the power consumption
can be large because a static current flows from the supply to
ground. The anti-harmonic lock block is very important to
achieve 50% duty ratio, especially when multiphase clocks are
needed. Only rising times of multiphase clocks (B<0>,B<1>,
etc) need to be matched because falling edges are not used.
Rising edge mismatch may affect duty ratio in 0.13um
technology within a tolerable range.
In the conventional DLL-based clock generators [4],[5],
the frequency multiplier needs many AND gates to combine
eight pulses when it needs to generate the clock that is four
times faster than the reference clock. These AND gates make
the jitter worse and consume a great deal of power. The
frequency multiplier block can consume nearly half of the
entire block’s power [5]. The proposed block does not need
these AND gates, so the path between the pulse generator (Q1,
Q2 and so on) and the combining circuit is decreased. This
enhances the jitter characteristics, and the power consumption
is also very small. This fact will be presented again in the
presentation of the results from the experiment.
B. The proposed anti-harmonic lock block
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 The main role of the DLL is to lock the input clock to the
reference clock. It does not matter whether the input clock
locks in one period of the reference clock or in two periods of
Figure 3. (a) Timing diagram of the correct locking state (b) Timing diagram
of the harmonic locking state.
Figure 4. The operation of the anti-harmonic lock.
the reference clock. However, in the frequency multiplier, it
uses the multiphase clocks to multiply the reference clock.
To generate the exactly multiplied clock, it is important to
lock the input clock to one period of the reference clock
(B<0>). Figure 3 (a) shows the normal operation of the
frequency multiplier when the input clock or multiphase clock
(B<8>) locks to one period of the reference clock (B<0>). As
shown in Figure 3 (b), if the multiphase clock (B<8>) locks to
two periods of the reference clock (called harmonic lock), the
amount of delay between the multiphase clocks increases. This
results in an increase in the multiplied clock period. To avoid
harmonic lock, the multiphase clock (B<8>) should be located
between 0.5 Tref and 1.5 Tref period of the reference clock
(B<0>). The conventional anti-harmonic lock blocks mainly
sees if the rising edges of two or three multiphase clocks are
located in the right place or not [4],[10]. In this case, if one
multiphase clock is located in the wrong position due to the
phase error, the anti-harmonic block generates the wrong
information. To avoid this problem, the proposed anti-
harmonic lock checks the amount of each phase delay one by
one as shown in Figure 4. In this case, two multiphase clocks
are selected. The condition of the input clock (B<8>) can be
expressed as Eq.(1).
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If one third is multiplied to each side of equation (1),
equation (1) can be changed to equation (2).
As the amount of delay variation of B<3> is one third of
B<8> with the same control voltage variation, B<3> phase
delay should not exceed a half period of the reference clock
(B<0>) as described in Eq.(3).
The anti-harmonic lock considers only the rising edges as
shown in Figure 4. The anti-harmonic lock can operate from
DC to 2.1GHz. If the operating frequency is over 2.1GHz,
short pulse generators cannot generate the pulses suitable for
operating the D-FFs.
IV. EXPERIMENTAL RESULTS
The proposed anti-harmonic, DLL-based clock generator
has been fabricated in a 0.13um CMOS technology. Figure 5
shows a microphotograph of the prototype chip. The amount
of load that each cell of the VCDL drives should be equal, so
several dummy inverters are used.
The test chip occupies 0.019mm2 and uses a 1.2V supply
voltage. The DLL-based frequency multiplier dissipates
21mW at 2GHz. The proposed frequency multiplier consumes
only 4.8mW. The portion of the conventional frequency
multiplier power dissipation was about half of the entire clock
generator’s power consumption. The proposed block decreases
the portion of the frequency multiplier’s power consumption
and active area. The multiplication ratio of the DLL-based
clock generator is programmable (0.5x, 1x, 2x, and 4x) and a
2-bit multiplication factor control used to change the
multiplication factor on-the-fly.
The 2GHz multiplied clock can be obtained in this DLL-
clock based clock generator where the reference frequency is
500MHz and the multiplication factor is four. When the
multiplication factor of two is activated, a 2x faster clock than
the reference clock can be obtained. If the input frequency is
500MHz, then the multiplied output clock frequency is 1GHz.
The measured peak-to-peak jitter of the 2x multiplied output
clock @ 1GHz is 19ps as shown in Figure 6. The enhanced
jitter is obtained primarily through the frequency multiplier.
The operating frequency of this work is not very high, but the
active area is the smallest (0.019mm2), and the power
consumption is decreased as stated above.
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Figure 5. The Micrograph of the prototype chip.
Figure 6. The measured jitter histogram.
V. CONCLUSION
The proposed DLL-based clock generator occupies a small
area and has a small jitter due to the simplicity of the
frequency multiplier. The proposed frequency multiplier uses
two kinds of D flip-flops. One is a flip-flop in which the
output goes to zero when the reset is activated. The other is a
flip-flop in which the output goes to ‘High’ when the reset is
activated. The frequency multiplier uses only 4 NMOS and
PMOS pairs, so it can decrease the active area and power
consumption significantly. As the proposed frequency
multiplier’s signal path from input to output is shorter than in
the conventional clock generators, the jitter generated through
VCDL and its accumulation is reduced. The proposed DLL-
based clock generator is implemented in a 0.13um CMOS
technology and the measured power consumption to frequency
ratio is only 0.11mW/MHz. This DLL-based clock generator
can produce output clock without any risk of harmonic locking.
The output clock frequency range can be programmable from
120MHz to 2GHz, so it can be used in portable mobile
applications and microprocessors with dynamic frequency
scaling where the low-power consumption and wide operating
frequency range are needed.
ACKNOWLEDGMENTS
This work was sponsored by ETRI SoC Industry Promotion
Center, Human Resource Development Project for IT SoC
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Architect. And the authors would like to thank IC Design
Education Center (IDEC) and the Korea Ministry of
Knowledge Economy(MKE) for the fabrication of the chip.
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