ASSESMENT TEST-I- KEY

Program: M.Tech Branch: VLSI Design

Course: FPGA Based System Design Course Code:
Semester: I Year: I
Time: 90 Min Max.Marks: 50
Answer All Questions
Q1 Give the result of each Verilog expression (in binary) for the following inputs: (4)
A = 4b’1001, B = 5’b10010, and C = 5b’11010. Assume A is a 4-bit wire and B and C
are each 5-bit wires. Show your results using Verilog notation.
i)A & (B | C);
ii) ^ B;
iii) (A < B) ? A : B
iv) {2{A},3{B},C}

Solution:
i)A & (B | C); =01000
ii) ^ B; = 0
iii) (A < B) ? A : B = 1001
iv) {2{A},3{B},C} = 1001100110010100101001011010

Q2 Write the Verilog HDL code for 1 bit full adder with a and b inputs, cin carry-in input, (6)
sum and cout outputs. Design 4 bit adder using 1 bit full adder and map the ports by name
Solution:

module fulladder (a,b,cin,sum,cout);

input a,b,cin;
output sum,cout;
wire sum,cout;
assign sum= a ^ b ^ cin;
assign cout= (a & b) | (b & c) | (c & a);
endmodule

// Four- Bit Adder

module full_fourbit(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0]sum;
output cout;
wire c1,c2,c3;
 fulladder f1( .a(a[0]), .b(b[0] , .cin(cin), .sum(sum[0]), .cout(c1));
fulladder f1( .a(a[0]), .b(b[0] , .cin(c1), .sum(sum[0]), .cout(c2));
fulladder f1( .a(a[0]), .b(b[0] , .cin(c2), .sum(sum[0]), .cout(c3));
fulladder f1( .a(a[0]), .b(b[0] , .cin(c3), .sum(sum[0]), .cout(cout));
endmodule
Q3. Why a nonblocking assignment should be used for sequential logic and what would (5)
happen if a blocking assignment were used? Compare it with the same code in a
combinatorial block.
Solution:
The main difference between the blocking and nonblocking assignment is that, in the
blocking assignment, the RHS immediately gets assigned to the LHS, whereas for
the nonblocking assignment, the assignment to the LHS is scheduled after the RHS
is evaluated.
The following illustrate the different scenarios of using blocking and nonblocking in
a sequential code.

In the above example, the assignments to the reg1, reg2, reg3,out1 have been made
as blocking assignments. The synthesized result is a single FF, with the d input of
in1, and q output of reg3, as shown in the following figure:
This is because the intermediate results between in1 and out1 were stored in reg1,
reg2, and reg3 in a blocking format. As a result, the evaluation of the final result to
out1 didn’t require waiting for all the events of the RHS to be completed. Rather,
they were immediately assigned to the LHS in the order specified. Observe that the
signals reg1, reg2, and reg3 have been optimized away by synthesis.
Using nonblocking statements in a sequential logic

In the above example, the assignments to the reg1, reg2, reg3, out1 have been made
as nonblocking assignments. The synthesized result is the inference of as many FFs
as specified in the always block [in this case,4 FFs].

This is because the intermediate results between in1 and out1 were stored in reg1,
reg2, and reg3 in a nonblocking format. As a result, the evaluation of the result to
each individual reg required waiting for all the events of the RHS to be completed.
In this case, it was the output of the previous register controlled by the clk event. As
a result, the output is a shift register.
Q4. Write behavioral Verilog code to count the sequence 0001, 0010, 0100, 1000, 0001, 0010, (5)
0100…..
Solution:
module shift_1 (clk,rst,dout);
input clk,rst;
output [3:0]dout;
reg [3:0]dout;
always @(posedge clk)
if (rst)
dout <=4'b0001;
else if (dout == 4'b1000)
dout<=4'b0001;
else
dout = dout <<1;
endmodule
Q5. Write Verilog description for full subtractor using function (5)
Solution:
module fullsubtractor(a,b,c,Bo,Di);
input a,b,c;
output Bo,Di;
reg Bo,Di;
always @(a,b,c)
begin
Bo = fs1(a,b,c);
Di = fs2(a,b,c);
end
function fs1;
input a,b,c;
begin
Bo= a ^ b ^ c;
end
endfunction
function fs2;
input a,b,c;
begin
Di= (((~a) & b) | ((~a) & c) | (b & c));
end
endfunction
 endmodule

Q6. a) Fill in the table showing the values for the three registers at the given times. Legal (5)
answers are 0, 1, x, z, and indeterminate.

reg q, r, s, t;
initial begin
q = 1’b0;
t <= #1 1’b0;
q <= #1 1’b1;
s = 1’b1;
end
always
begin
r = 1’b1;
s = 1’b0;
wait (t === 1’b0)
q = 1’b0;
r = 1’b0;
q <= #10 1’b1;
end

Solution:

b) This doesn’t seem to stop executing! Why? If you interrupted the simulator, what
would the virtual time be? List all pending events at this time — i.e., ones that have been
scheduled but not yet executed.
The always will never stop after it first stops for the wait, while t is set to 0 at time 1
and does not change any more. An event (the update of q) will be in the event list for
time 11.
Q7. Develop ALU description in Verilog. The ALU has three inputs: two 16-bit A and B (10)
signed values and a 3-bit control signal that determines which operation the ALU should
perform. The ALU has a single 16-bit signed output, which is the result of the operation.
The ALU can perform eight operations as follows. Verify the logic by writing test bench.

Control Operation
C2C1C0
0 0 0 Addition
0 0 1 Subtraction
0 1 0 Bitwise AND
0 1 1 Bitwise OR
1 0 0 Bitwise XOR
1 0 1 Bitwise XNOR
1 1 0 Logical shift right by1 bit
1 1 1 Logical shift left by1 bit

Solution:
module ALU ( ctrl,A,B,dout);
input [15:0] A,B;
input [2:0] ctrl;
output [16:0] dout;
always @ (*)
begin
case(ctrl)
3’b000: dout= A + B;
3’b001: dout = A-B;
3’b010: dout = A & B;
3’b011: dout = A | B;
3’b100: dout = A ^ B;
3’b101; dout = ~ (A ^ B);
3’b110: dout = begin
dout=A<<1;
dout=B<<1;
end
3’b111:begin
dout= A>>1;
dout= A>>1;
end
endcase
endmodule
Q8. Draw the hardware will it generate for the following code (5)

module example3(clk,Merge,ER,Xmit,FDDI,Claim);
input clk,Merge,ER,Xmit,FDDI;
output Claim;
reg Claim;
reg FCR;
always@(posedge clk)
begin
FCR<= ER | Xmit;
if(Merge)
Claim <= FCR & FDDI;
else
Claim<= FDDI;
end
endmodule

Solution:

Q9. a) When to use wire and reg with examples. (2)

Solution:

When connecting gates, macros, memories or user defined fuctional
block to the other module block, the output of the block need to be
declared wire.

When there is sequential execution of the expression then the output

variable data type must be register.

b) Are the following are legal strings? If not write the correct strings. (1)
i. “out = in1 + in2”
Solution: legal
ii. “please ring bell \007”
Solution: legal
c) Draw the port connection rule
(2)