ATSAMA5D27 WLSOM1 Data Sheet ds60001590c-2256516

SAMA5D27 Wireless SOM1
ATSAMA5D27-WLSOM1
Introduction
The Microchip SAMA5D27 Wireless System-On-Module 1 (ATSAMA5D27-WLSOM1) is a small single-sided
SOM based on the high-performance System-in-Package (SiP) 32-bit Arm® Cortex®-A5 processor-based MPU
SAMA5D27, 2 Gb LPDDR2-SDRAM running up to 500 MHz, and Wi-Fi® plus Bluetooth® (Wi-Fi/BT) Wireless
module.
The ATSAMA5D27-WLSOM1 is built on a common set of proven Microchip components to reduce time to market by
simplifying hardware design and software development.
The ATSAMA5D27-WLSOM1 also limits design rules of the main application board, reducing overall PCB complexity
and cost. The ATSAMA5D27-WLSOM1 is delivered with a free Linux® distribution and bare metal C examples.
Figure 1. ATSAMA5D27-WLSOM1 Overview
© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 1

Features
• System-In-Package (ATSAMA5D27C-LD2G-CU) Including:
– Arm® Cortex®-A5 processor-based SAMA5D27 MPU
– 2 Gbit LPDDR2-SDRAM
• On-Board Power Management Unit (MCP16502AC-E/S8B)
• 64 Mb Serial Quad I/O Flash Memory (SST26VF064BEUIT-104I/MF) with Embedded EUI-48™ and EUI-64™
MAC Addresses
• IEEE® 802.11 b/g/n Wi-Fi plus Bluetooth (Wi-Fi/BT) Module (ATWILC3000-MR110UA)
• 10Base-T/100Base-TX Ethernet PHY (KSZ8081RNAIA)
• ATECC608B-TNGTLS Secure Element
• MEMS Oscillators for Clock Generation
• 40.8 x 40.8 mm Module, Pitch 0.8mm, Solderable Manually for Prototyping
• 94 I/Os
• Up to 7 Tamper Pins
• One USB Device, one USB Host and one HSIC Interface
• Shutdown and Reset Control Pins
• Independent Power Supplies Available for Camera Sensor, for SD Card and for Backup Depending on Voltage
Domains
• Operational Specifications:
– Main operating voltage: 3.0V to 5.5V ± 5%
– Temperature range: -40°C to 85°C
– Integrated oscillators, internal voltage regulators
– Multiple interfaces and I/Os for easy application development
Applications
• Industrial Control and Automation
• Smart Appliances
• Human Machine Interfaces (HMI)
• IoT Gateway
• Access Control Panels
• Security and Alarm Systems

Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 2
Applications.................................................................................................................................................... 2
1. Reference Documents............................................................................................................................ 5
2. Block Diagram.........................................................................................................................................6
3. Pinout ..................................................................................................................................................... 7
3.1. Pinout Overview........................................................................................................................... 7
3.2. Pin List..........................................................................................................................................7
4. Functional Description...........................................................................................................................21
4.1. MPU and Memory Subsystem....................................................................................................21
4.2. Power Management................................................................................................................... 25
4.3. LAN Subsystem..........................................................................................................................30
4.4. Voltage Threshold Detector........................................................................................................31
4.5. Radio Subsystem....................................................................................................................... 32
4.6. External Interfaces..................................................................................................................... 33
5. Electrical Characteristics.......................................................................................................................48
5.1. Absolute Maximum Ratings........................................................................................................48
5.2. Recommended Operating Conditions........................................................................................ 48
5.3. DC Characteristics..................................................................................................................... 48
5.4. Power Consumption................................................................................................................... 49
5.5. Radio Performance.................................................................................................................... 51
6. Mechanical Characteristics................................................................................................................... 52
6.1. Module Outline Drawings........................................................................................................... 52
6.2. Module Land Pattern (Host Board PCB Footprint)..................................................................... 54
6.3. Other Characteristics..................................................................................................................55
7. Assembly and Storage Information....................................................................................................... 56

7.1. Storage Condition.......................................................................................................................56
7.2. Motherboard Solder Paste......................................................................................................... 56
7.3. Motherboard Stencil Design....................................................................................................... 56
7.4. Bake Information........................................................................................................................ 56
7.5. Reflow Profile............................................................................................................................. 57
8. Regulatory Approval..............................................................................................................................59
8.1. United States..............................................................................................................................59
8.2. Canada.......................................................................................................................................60
8.3. Europe........................................................................................................................................61
8.4. Approved Antenna Types........................................................................................................... 63
9. Ordering Information............................................................................................................................. 66

10. Revision History.................................................................................................................................... 67

10.1. Rev. C - 03/2021........................................................................................................................ 67
10.2. Rev. B - 12/2019.........................................................................................................................67
10.3. Rev. A - 10/2019.........................................................................................................................68
The Microchip Website.................................................................................................................................69
Product Change Notification Service............................................................................................................69
Customer Support........................................................................................................................................ 69
Product Identification System.......................................................................................................................70
Microchip Devices Code Protection Feature................................................................................................ 70
Legal Notice................................................................................................................................................. 70
Trademarks.................................................................................................................................................. 71
Quality Management System....................................................................................................................... 71
Worldwide Sales and Service.......................................................................................................................72

Reference Documents
1. Reference Documents
The following reference data sheets are available on www.microchip.com:
Table 1-1. Reference Data Sheets
Document Title Available

KSZ8081RNA/RND www.microchip.com/wwwproducts/en/KSZ8081
SAMA5D2 SIP www.microchip.com/wwwproducts/en/ATSAMA5D27C-LD2G
SST26VF064BEUI www.microchip.com/wwwproducts/en/SST26VF064BEUI
MCP16502 https://www.microchip.com/wwwproducts/en/MCP16502
MIC841/2 https://www.microchip.com/wwwproducts/en/MIC842
DSC60XXB www.microchip.com/wwwproducts/en/DSC6000B
DSC61XXB www.microchip.com/wwwproducts/en/DSC6100B
ATWILC3000-MR110UA https://www.microchip.com/wwwproducts/en/ATWILC3000
ATECC608B-TNGTLS www.microchip.com/wwwproducts/en/ATECC608B-TNGTLS

Block Diagram
2. Block Diagram
The following figure shows the block diagram of the ATSAMA5D27-WLSOM1 module.
Figure 2-1. ATSAMA5D27-WLSOM1 Module Block Diagram
3.3V 1.8V
VDDFUSE VDDISC VDDANA VDDBU
600mA 900mA
MAIN
Voltage Monitor MIC842NYMT 64 Mbit Serial Quad I/O
3.0-5.5V
Flash Memory
VDD
Power Management Unit SST26VF064BEUIT-104I/MF
SDHC
MCP16502AC-E/S8B With MAC Address QSPI_CS
VLDO2 EUI-48 & EUI-64 Node Identity
300mA
CryptoAuthentication™ ECC608B-TNGTLS
JTAG & DBGU Interfaces
25 MHz DSC6102
24 MHz DSC6003
DEBUG
Disable Boot
10/100
7 * PIOBU Ethernet RMII PHY
BACKUP
RXD KSZ8081RNAIA
MPU
WAKEUP
RESET +
SYSTEM 2 Gb LPDDR2
SHUTDOWN
Wi-Fi/BT Module
32 kHz Crystal
nSTART_SOM
CLK_AUDIO SAMA5D27C-LD2G-CU
MISC
COMPP / COMPN
ATWILC3000
2 * USB -MR110UA
Up to 94 Mixable I/Os
Legend:
Mono PDMIC Interface

4 FLEXCOM Interfaces
Power Supply Input

SD-CARD Interface
SMC 8-bit Interface
18-bit LCD Interface
Up to 6 ADC Inputs
5 UART Interfaces
Camera Interface
2 QSPI Interfaces
64-channel Touch
CLASS-D Mono
eMMC Interface
2 SPI Interfaces
SSC Interface
CAN Interface
2 WILC Output LEDs
TWI Interface
I²S Interface
Power Supply Output
System Signal
Interface Signal

Pinout
3. Pinout
3.1 Pinout Overview

Figure 3-1. ATSAMA5D27-WLSOM1 Pin Assignment
NC_3-WILC - 83
ETH_RX_N - 86
ETH_TX_N - 88
ETH_RX_P - 87
ETH_LED0 - 84
ETH_TX_P - 89
VDDISC - 73
PC14 - 62
PC25 - 61
PC18 - 56
PC22 - 65
PC13 - 64
PC23 - 59
PC20 - 58
PC21 - 63
PC16 - 57
PC11 - 68
PC12 - 67
PC24 - 66
PC10 - 60
PC15 - 71
PC19 - 70
PC17 - 72
PB11 - 92
PB12 - 91
PA30 - 76
PA31 - 75
GND - 94
GND - 85
GND - 74
GND - 55
GND - 82
GND - 50
GND - 49
GND - 90
GND - 53
GND - 52
GND - 93
GND - 48
GND - 51
GND - 54
PC9 - 69
PB1 - 80
PB2 - 79
PB4 - 77
PB0 - 81
PB3 - 78
GND - 95 47 - GND
SCK_QSPI_PB5 - 96 46 - GND
SIO3_QSPI_PB10 - 97 45 - GND
SIO0_QSPI_PB7 - 98 44 - GND
SIO1_QSPI_PB8 - 99 43 - TXD_WILC_DBG
SIO2_QSPI_PB9 - 100 42 - RXD_WILC_DBG
NCS_QSPI - 101 41 - NC_20-WILC
QSPI1_CS_PB6 - 102 40 - GND
PD2 - 103 39 - PC28
PD3 - 104 38 - PC29
PD4 - 105 37 - PC26
PD6 - 106 36 - PC31
PD7 - 107 35 - PC27
PD8 - 108 34 - PC30
PD5 - 109 33 - PD0
PD9 - 110 32 - PD1
PD10 - 111 31 - GND
PD17 - 112 30 - PB30
PD18 - 113 29 - PB26
PD15 - 114 28 - PB28
PD16 - 115 27 - PB29
PD13 - 116 26 - PB31
PD14 - 117 25 - PB27
PD11 - 118 24 - PA17
PD12 - 119 23 - PA16
TWD_SOM_PD19 - 120 22 - PA15
GND - 121 21 - PA14
TWCK_SOM_PD20 - 122 20 - PC5
PD27 - 123 19 - PC4
PD28 - 124 18 - PC1
GND - 125 17 - PC2
MICROCHIP
GND - 126 16 - PC3
PD26 - 127 15 - PC0
GND - 128 14 - GND
ATSAMA5D27-WLSOM1
GND - 129 13 - VDD_3V3
1941000
PD30 - 130 12 - VDD_3V3
PD29 - 131 11 - GND
RevB.0 - 0000027
PD25 - 132 10 - SHDN
GND - 133 9 - GND
RXD - 134 8 - GND
PIOBU2 - 135 7 - NRST
PIOBU7 - 136 6 - GND
PIOBU3 - 137 5 - GND
PIOBU5 - 138 4 - VDD_MAIN
COMPP - 139 3 - VDD_MAIN
COMPN - 140 2 - VDD_MAIN
GND - 141 1 - GND
150 - VDDSDHC
151 - USBA_N
156 - HSIC_DATA
157 - HSIC_STROBE
168 - PA10
169 - PA4
147 - PIOBU4
148 - PIOBU6
153 - USBB_N
154 - USBB_P
165 - PA0
166 - PA2
175 - PA13
176 - PC6
162 - PA1
163 - PA5
172 - PA9
173 - PA7
149 - GND
155 - GND
159 - VDDANA
167 - PA8
185 - VDD_DDR
160 - GND
170 - PA12
144 - GND
145 - CLK_AUDIO
146 - PIOBU1
152 - USBA_P
164 - PA3
174 - PA11
171 - PA6
142 - GND
161 - VDDFUSE
158 - GND
178 - VTH
179 - GND
184 - GND
143 - VDDBU
181 - GND
182 - nSTART_SOM
187 - WKUP
177 - PC7
183 - GND
180 - VLDO2
186 - VDD_DDR
188 - GND
3.2 Pin List

The following tables provide the SAMA5D27-WLSOM1 module pin description.

Pinout
Important: Compared to SAMA5D2 Series devices, some PIO features are not listed. These features are
used internally on the SAMA5D27-WLSOM1 and cannot be shared with other PIOs for use with features or
for signal integrity.
3.2.1 PIOA Pin Description

Table 3-1. PIOA Pin Description
Primary Alternate PIO Peripheral Note

Pad No. Power Rail I/O Type Reset State (Signal, Dir, PU, PD, HiZ, ST)
Signal Dir Signal Dir Func Signal Dir IO Set
A SDMMC0_CK I/O 1
W11 VDDSDHC GPIO_EMMC PA0 I/O – – B QSPI0_SCK O 1 PIO, I, PU, ST
F D0 I/O 2
A SDMMC0_CMD I/O 1
R9 VDDSDHC GPIO_EMMC PA1 I/O – – B QSPI0_CS O 1 PIO, I, PU, ST
F D1 I/O 2
A SDMMC0_DAT0 I/O 1
W12 VDDSDHC GPIO_EMMC PA2 I/O – – B QSPI0_IO0 I/O 1 PIO, I, PU, ST
F D2 I/O 2
A SDMMC0_DAT1 I/O 1
V11 VDDSDHC GPIO_EMMC PA3 I/O – – B QSPI0_IO1 I/O 1 PIO, I, PU, ST
F D3 I/O 2
A SDMMC0_DAT2 I/O 1
W14 VDDSDHC GPIO_EMMC PA4 I/O – – B QSPI0_IO2 I/O 1 PIO, I, PU, ST
F D4 I/O 2
A SDMMC0_DAT3 I/O 1
V10 VDDSDHC GPIO_EMMC PA5 I/O – – B QSPI0_IO3 I/O 1 PIO, I, PU, ST
F D5 I/O 2
A SDMMC0_DAT4 I/O 1
B QSPI1_SCK O 1
W15 VDDSDHC GPIO_EMMC PA6 I/O – – D TIOA5 I/O 1 PIO, I, PU, ST Note (2)
E FLEXCOM2_IO0 I/O 1
F D6 I/O 2
A SDMMC0_DAT5 I/O 1
B QSPI1_IO0 I/O 1
W16 VDDSDHC GPIO_EMMC PA7 I/O – – D TIOB5 I/O 1 PIO, I, PU, ST Note (2)
F D7 I/O 2

Pinout
...........continued
A SDMMC0_DAT6 I/O 1
B QSPI1_IO1 I/O 1
V12 VDDSDHC GPIO_EMMC PA8 I/O – – D TCLK5 I 1 PIO, I, PU, ST Note (2)
F NWE/NANDWE O 2
A SDMMC0_DAT7 I/O 1
B QSPI1_IO2 I/O 1
V16 VDDSDHC GPIO_EMMC PA9 I/O – – D TIOA4 I/O 1 PIO, I, PU, ST Note (2)
E FLEXCOM2_IO3 O 1
F NCS3 O 2
A SDMMC0_RSTN O 1
B QSPI1_IO3 I/O 1
V14 VDDSDHC GPIO_EMMC PA10 I/O – – D TIOB4 I/O 1 PIO, I, PU, ST Note (2)
E FLEXCOM2_IO4 O 1
F A21/NANDALE O 2
A SDMMC0_VDDSEL O 1
B QSPI1_CS O 1
L18 VDD_3V3 GPIO PA11 I/O – – PIO, I, PU, ST
D TCLK4 I 1
F A22/NANDCLE O 2
A SDMMC0_WP I 1
T16 VDD_3V3 GPIO PA12 I/O – – B IRQ I 1 PIO, I, PU, ST
F NRD/NANDOE O 2
A SDMMC0_CD I 1
K18 VDD_3V3 GPIO PA13 I/O – – PIO, I, PU, ST Note (3)
A SPI0_SPCK I/O 1
B TK1 I/O 1
R19 VDD_3V3 GPIO_QSPI PA14 I/O – – PIO, I, PU, ST Note (3)
D I2SMCK1 O 2
A SPI0_MOSI I/O 1
B TF1 I/O 1
L17 VDD_3V3 GPIO PA15 I/O – – PIO, I, PU, ST Note (3)
D I2SCK1 I/O 2

Pinout
A SPI0_MISO I/O 1
B TD1 O 1
N19 VDD_3V3 GPIO_IO PA16 I/O – – PIO, I, PU, ST Note (3)
D I2SWS1 I/O 2
E FLEXCOM3_IO3 O 1
A SPI0_NPCS0 I/O 1
M16 VDD_3V3 GPIO_IO PA17 I/O – – D I2SDI1 I 2 PIO, I, PU, ST Note (3)
E FLEXCOM3_IO4 O 1
C SPI0_NPCS0 I/O 2
U12 VDD_3V3 GPIO PA30 I/O – – PIO, I, PU, ST Note (3)
D PWMH0 O 1
C SPI0_MISO I/O 2
U17 VDD_3V3 GPIO PA31 I/O – – PIO, I, PU, ST Note (3)
D PWML0 O 1
Notes:
1. Fixed feature due to the WLSOM1 internal connection.
2. Limited feature compared to SAMA5D2 due to the WLSOM1 internal use of specific functionality, for example,
QSPI, GMAC.
3. Limited feature compared to SAMA5D2 due to the use of a part of the functionality for other features in the
WLSOM1, for example, GMAC, ISC, FLEXCOM, etc.
3.2.2 PIOB Pin Description

Table 3-2. PIOB Pin Description
Reset State (Signal, Dir, PU, PD, HiZ,

Pad No. Power Rail I/O Type Primary Alternate PIO Peripheral Note
ST)
C SPI0_MOSI I/O 2
C7 VDD_3V3 GPIO PB0 I/O – – PIO, I, PU, ST Note (3)
D PWMH1 O 1
C SPI0_SPCK I/O 2
A9 VDD_3V3 GPIO PB1 I/O – – D PWML1 O 1 PIO, I, PU, ST Note (3)
F CLASSD_R0 O 1
D PWMFI0 I 1
A10 VDD_3V3 GPIO PB2 I/O – – PIO, I, PU, ST Note (3)
F CLASSD_R1 O 1
A URXD4 I 1
C IRQ I 3
D PWMEXTRG0 I 1
F CLASSD_R2 O 1
A UTXD4 O 1
A12 VDD_3V3 GPIO PB4 I/O – – C FIQ I 4 PIO, I, PU, ST Note (3)
F CLASSD_R3 O 1

Pinout
ST)
A TCLK2 I 1
A7 VDD_3V3 GPIO_QSPI PB5 I/O – – C PWMH2 O 1 PIO, I, PU, ST Note (2) Note (3)
D QSPI1_SCK O 2
A TIOA2 I/O 1
B7 VDD_3V3 GPIO PB6 I/O – – C PWML2 O 1 PIO, I, PU, ST Note (2) Note (3)
D QSPI1_CS O 2
A TIOB2 I/O 1
C5 VDD_3V3 GPIO_IO PB7 I/O – – C PWMH3 O 1 PIO, I, PU, ST Note (2) Note (3)
D QSPI1_IO0 I/O 2
A TCLK3 I 1
B8 VDD_3V3 GPIO_IO PB8 I/O – – C PWML3 O 1 PIO, I, PU, ST Note (2) Note (3)
D QSPI1_IO1 I/O 2
A TIOA3 I/O 1
B6 VDD_3V3 GPIO_IO PB9 I/O – – C PWMFI1 I 1 PIO, I, PU, ST Note (2) Note (3)
D QSPI1_IO2 I/O 2
A TIOB3 I/O 1
G6 VDD_3V3 GPIO_IO PB10 I/O – – C PWMEXTRG1 I 1 PIO, I, PU, ST Note (2) Note (3)
D QSPI1_IO3 I/O 2
C URXD3 I 3
B5 VDD_3V3 GPIO PB11 I/O – – PIO, I, PU, ST Note (3)
D PDMIC_DAT0 I/O 2
C UTXD3 O 3
D PDMIC_CLK0 O 2
C URXD0 I 1
G2 VDD_3V3 GPIO PB26 I/O – – D PDMIC_DAT0 I/O 1 PIO, I, PU, ST Note (3)
F ISI_D0 I 3
C UTXD0 O 1
H5 VDD_3V3 GPIO PB27 I/O – – D PDMIC_CLK0 O 1 PIO, I, PU, ST Note (3)
F ISI_D1 I 3
C FLEXCOM0_IO0 I/O 1
J2 VDD_3V3 GPIO PB28 I/O – – D TIOA5 I/O 2 PIO, I, PU, ST Note (3)
F ISI_D2 I 3
J3 VDD_3V3 GPIO PB29 I/O – – D TIOB5 I/O 2 PIO, I, PU, ST Note (3)
F ISI_D3 I 3

Pinout
ST)
A2 VDD_3V3 GPIO PB30 I/O – – D TCLK5 I 2 PIO, I, PU, ST Note (3)
F ISI_D4 I 3
C FLEXCOM0_IO3 O 1
J4 VDD_3V3 GPIO PB31 I/O – – PIO, I, PU, ST Note (3)
F ISI_D5 I 3
Notes:
QSPI, GMAC.
3.2.3 PIOC Pin Description

Table 3-3. PIOC Pin Description

C FLEXCOM0_IO4 O 1
T14 VDD_3V3 GPIO PC0 I/O – – PIO, I, PU, ST Note (3)
F ISI_D6 I 3
C CANTX0 O 1
D SPI1_SPCK I/O 1
R16 VDD_3V3 GPIO PC1 I/O – – PIO, I, PU, ST Note (3)
E I2SCK0 I/O 1
F ISI_D7 I 3
C CANRX0 I/O 1
D SPI1_MOSI I/O 1
E I2SMCK0 O 1
F ISI_D8 I 3
C TIOA1 I/O 1
D SPI1_MISO I/O 1
E I2SWS0 I/O 1
F ISI_D9 I 3
C TIOB1 I/O 1
D SPI1_NPCS0 I/O 1
P16 VDD_3V3 GPIO PC4 I/O – – PIO, I, PU, ST Note (3)
E I2SDI0 I 1
F ISI_PCK I 3

Pinout
C TCLK1 I 1
D SPI1_NPCS1 O 1
L19 VDD_3V3 GPIO PC5 I/O – – PIO, I, PU, ST Note (3)
E I2SDO0 O 1
F ISI_VSYNC I 3
D SPI1_NPCS2 O 1
R15 VDD_3V3 GPIO PC6 I/O – – PIO, I, PU, ST Note (3)
F ISI_HSYNC I 3
D SPI1_NPCS3 O 1
N15 VDD_3V3 GPIO_CLK PC7 I/O – – PIO, I, PU, ST Note (3)
F ISI_MCK O 3
A FIQ I 3
B2 VDDISC GPIO PC9 I/O – – C ISI_D0 I 1 PIO, I, PU, ST Note (2)
D TIOA4 I/O 2
A LCDDAT2 O 2
C ISI_D1 I 1
K5 VDDISC GPIO PC10 I/O – – PIO, I, PU, ST Note (2)
D TIOB4 I/O 2
E CANTX0 O 2
A LCDDAT3 O 2
C ISI_D2 I 1
C2 VDDISC GPIO PC11 I/O – – D TCLK4 I 2 PIO, I, PU, ST Note (2)
E CANRX0 I 2
F A0/NBS0 O 2
A LCDDAT4 O 2
C ISI_D3 I 1
D2 VDDISC GPIO PC12 I/O – – D URXD3 I 1 PIO, I, PU, ST Note (2)
E TK0 I/O 2
F A1 O 2
A LCDDAT5 O 2
C ISI_D4 I 1
K2 VDDISC GPIO PC13 I/O – – D UTXD3 O 1 PIO, I, PU, ST Note (2)
E TF0 I/O 2
F A2 O 2
A LCDDAT6 O 2
C ISI_D5 I 1
E TD0 O 2
F A3 O 2

Pinout
A LCDDAT7 O 2
C ISI_D6 I 1
B1 VDDISC GPIO PC15 I/O – – PIO, I, PU, ST Note (2)
E RD0 I 2
F A4 O 2
A LCDDAT10 O 2
C ISI_D7 I 1
E RK0 I/O 2
F A5 O 2
A LCDDAT11 O 2
C ISI_D8 I 1
C1 VDDISC GPIO PC17 I/O – – PIO, I, PU, ST Note (2)
E RF0 I/O 2
F A6 O 2
A LCDDAT12 O 2
C ISI_D9 I 1
L9 VDDISC GPIO PC18 I/O – – PIO, I, PU, ST Note (2)
F A7 O 2
A LCDDAT13 O 2
C ISI_D10 I 1
D1 VDDISC GPIO PC19 I/O – – PIO, I, PU, ST Note (2)
F A8 O 2
A LCDDAT14 O 2
C ISI_D11 I 1
L8 VDDISC GPIO PC20 I/O – – PIO, I, PU, ST Note (2)
F A9 O 2
A LCDDAT15 O 2
C ISI_PCK I 1
E3 VDDISC GPIO PC21 I/O – – PIO, I, PU, ST Note (2)
E FLEXCOM3_IO3 O 2
F A10 O 2
A LCDDAT18 O 2
C ISI_VSYNC I 1
E2 VDDISC GPIO PC22 I/O – – PIO, I, PU, ST Note (2)
E FLEXCOM3_IO4 O 2
F A11 O 2
A LCDDAT19 O 2
L7 VDDISC GPIO PC23 I/O – – C ISI_HSYNC I 1 PIO, I, PU, ST Note (2)
F A12 O 2

Pinout
A LCDDAT20 O 2
E1 VDDISC GPIO_CLK PC24 I/O – – C ISI_MCK O 1 PIO, I, PU, ST Note (2)
F A13 O 2
A LCDDAT21 O 2
L4 VDDISC GPIO PC25 I/O – – C ISI_FIELD I 1 PIO, I, PU, ST Note (2)
F A14 O 2
A LCDDAT22 O 2
D6 VDD_3V3 GPIO PC26 I/O – – D CANTX1 O 1 PIO, I, PU, ST Note (2)
F A15 O 2
A LCDDAT23 O 2
C PCK1 O 2
E7 VDD_3V3 GPIO PC27 I/O – – PIO, I, PU, ST Note (2)
D CANRX1 I/O 1
F A16 O 2
A LCDPWM O 2
B FLEXCOM4_IO0 I/O 1
J5 VDD_3V3 GPIO PC28 I/O – – PIO, I, PU, ST Note (2)
C PCK2 O 1
F A17 O 2
A LCDDISP O 2
C6 VDD_3V3 GPIO PC29 I/O – – B FLEXCOM4_IO1 I/O 1 PIO, I, PU, ST
F A18 O 2
A LCDVSYNC O 2
D7 VDD_3V3 GPIO PC30 I/O – – B FLEXCOM4_IO2 I/O 1 PIO, I, PU, ST
F A19 O 2
A LCDHSYNC O 2
B FLEXCOM4_IO3 O 1
C8 VDD_3V3 GPIO PC31 I/O – – PIO, I, PU, ST
C URXD3 I 2
F A20 O 2
Notes:
QSPI, GMAC.

Pinout
3.2.4 PIOD Pin Description

A LCDPCK O 2
B FLEXCOM4_IO4 O 1
J7 VDD_3V3 GPIO_CLK PD0 I/O – – C UTXD3 O 2 PIO, I, PU, ST
D GTSUCOMP O 2
F A23 O 2
A LCDDEN O 2
D8 VDD_3V3 GPIO PD1 I/O – – D GRXCK I 2 PIO, I, PU, ST
F A24 O 2
A URXD1 I 1
D GTXER O 2
J6 VDD_3V3 GPIO_CLK PD2 I/O – – PIO, I, PU, ST
E ISI_MCK O 2
F A25 O 2
A UTXD1 O 1
B FIQ I 2
M3 VDDANA GPIO_AD PD3 I/O PTC_ROW0 – D GCRS I 2 PIO, I, PU, ST
E ISI_D11 I 2
F NWAIT I 2
B URXD2 I 1
D GCOL I 2
L6 VDDANA GPIO_AD PD4 I/O PTC_ROW1 – PIO, I, PU, ST Note (2)
E ISI_D10 I 2
F NCS0 O 2
B UTXD2 O 1
D GRX2 I 2
E ISI_D9 I 2
F NCS1 O 2
A TCK I 2
D GRX3 I 2
J1 VDDANA GPIO_AD PD6 I/O PTC_ROW3 – PIO, I, PU, ST Note (2)
E ISI_D8 I 2
F NCS2 O 2
A TDI I 2
D GTX2 O 2
E ISI_D0 I 2
F NWR1/NBS1 O 2

Pinout
A TDO O 2
D GTX3 O 2
K1 VDDANA GPIO_AD PD8 I/O PTC_ROW5 – PIO, I, PU, ST Note (3)
E ISI_D1 I 2
F NANDRDY I 2
A TMS I 2
L3 VDDANA GPIO_AD PD9 I/O PTC_ROW6 – D GTXCK O 2 PIO, I, PU, ST Note (3)
E ISI_D2 I 2
A NTRST I 2
L1 VDDANA GPIO_AD PD10 I/O PTC_ROW7 – D GTXEN O 2 PIO, I, PU, ST Note (3)
E ISI_D3 I 2
A TIOA1 I/O 3
B PCK2 O 2
N3 VDDANA GPIO_AD PD11 I/O PTC_COL0 – PIO, I, PU, ST Note (3)
D GRXDV I 2
E ISI_D4 I 2
A TIOB1 I/O 3
M7 VDDANA GPIO_AD PD12 I/O PTC_COL1 – PIO, I, PU, ST Note (3)
D GRXER I 2
E ISI_D5 I 2
A TCLK1 I 3
N2 VDDANA GPIO_AD PD13 I/O PTC_COL2 – PIO, I, PU, ST Note (3)
D GRX0 I 2
E ISI_D6 I 2
A TCK I 1
D GRX1 I 2
E ISI_D7 I 2
A TDI I 1
B FLEXCOM4_IO3 O 2
D GTX0 O 2
E ISI_PCK I 2
A TDO O 1
B FLEXCOM4_IO4 O 2
D GTX1 O 2
E ISI_VSYNC I 2

Pinout
A TMS I 1
M2 VDDANA GPIO_AD PD17 I/O PTC_COL6 – D GMDC O 2 PIO, I, PU, ST Note (3)
E ISI_HSYNC I 2
A NTRST I 1
M4 VDDANA GPIO_AD PD18 I/O PTC_COL7 – D GMDIO I/O 2 PIO, I, PU, ST Note (3)
E ISI_FIELD I 2
M8 VDDANA GPIO_AD PD19 I/O – – B TWD1 I/O 3 PIO, I, PU, ST Note (1)
N1 VDDANA GPIO_AD PD20 I/O – – B TWCK1 I/O 3 PIO, I, PU, ST Note (1)
P8 VDDANA GPIO_AD PD25 I/O AD6 – A SPI1_SPCK O 3 PIO, I, PU, ST
A SPI1_MOSI I/O 3
P2 VDDANA GPIO_AD PD26 I/O AD7 – PIO, I, PU, ST
A SPI1_MISO I/O 3
N5 VDDANA GPIO_AD PD27 I/O AD8 – B TCK I 3 PIO, I, PU, ST
A SPI1_NPCS0 I/O 3
N4 VDDANA GPIO_AD PD28 I/O AD9 – B TDI I 3 PIO, I, PU, ST
A SPI1_NPCS1 O 3
B TDO O 3
R2 VDDANA GPIO_AD PD29 I/O AD10 – PIO, I, PU, ST Note (2)
C FLEXCOM2_IO3 O 2
D TIOA3 I/O 3
A SPI1_NPCS2 O 3
B TMS I 3
N10 VDDANA GPIO_AD PD30 I/O AD11 – PIO, I, PU, ST Note (2)
C FLEXCOM2_IO4 O 2
D TIOB3 I/O 3
Notes:
QSPI, GMAC.
3.2.5 System Pins Description

Table 3-4. System Pins Description
Pin No. Pin Name Power Rail Description
145 CLK_AUDIO VDD_3V3 Audio Main System Bus Clock Frequency Output
151 USBA_N VDD_3V3 USB Device High-Speed Data -

Pinout
Pin No. Pin Name Power Rail Description
152 USBA_P VDD_3V3 USB Device High-Speed Data +
157 HSIC_STROBE VDDHSIC (1.2V) USB High-Speed Inter-Chip Strobe
156 HSIC_DATA VDDHSIC (1.2V) USB High-Speed Inter-Chip Data
153 USBB_N VDD_3V3 USB Host Port B High-Speed Data -
154 USBB_P VDD_3V3 USB Host Port B High-Speed Data +
7 NRST VDDBU Module Reset
140 COMPN VDDBU External Analog Data Input
139 COMPP VDDBU External Analog Data Input
146 PIOBU1 VDDBU Tamper I/O #1
134 RXD VDDBU RXLP Receive Data Input
10 SHDN VDDBU Shutdown Control
187 WKUP VDDBU Module Wake-Up
178 VTH VDD_MAIN Low Voltage Threshold Detection Input
101 NCS_QSPI VDD_3V3 Embedded QSPI Chip Select Input
83 NC – Not connected
41 NC – Not connected
89 ETH_TX_P – Physical Transmit Signal (+ differential)
88 ETH_TX_N – Physical Transmit Signal (– differential)
87 ETH_RX_P – Physical Receive Signal (+ differential)
86 ETH_RX_N – Physical Receive Signal (– differential)
84 ETH_LED0 VDD_3V3 Programmable LED0 Output
182 nSTART_SOM VDD_MAIN Module Start-Up Control Input
42 RXD_WILC_DBG VDD_3V3 Used for Radio Debug. UART RXD
43 TXD_WILC_DBG VDD_3V3 Used for Radio Debug. UART TXD
3.2.6 Power Pins Description

Table 3-5. Power Pins Description
Pin No. Pin Name Power Rail Type Description
1, 5, 6, 8, 9, 11, 14, 31, 40, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 74, 82, 85, 90, 93, 94, 95, 121,
GND GND GND Ground
125, 126, 129, 133, 141, 142, 144, 128, 149, 155, 158, 160, 179, 181, 183, 184, 188
159 VDDANA VDDANA I Analog Voltage Input

Pinout
Pin No. Pin Name Power Rail Type Description
143 VDDBU VDDBU I Backup Voltage Input
161 VDDFUSE VDDFUSE I VDDFUSE Voltage Input
73 VDDISC VDDISC I VDDISC Voltage Input
2, 3, 4 VDD_MAIN VDD_MAIN I Main Input Voltage
12, 13 VDD_3V3 VDD_3V3 O 3.3V Voltage Output
180 VLDO2 VLDO2 O VLDO2 Output Voltage
150 VDDSDHC VDDSDHC I VDDSDHC Input Voltage
185, 186 VDD_DDR VDD_DDR O 1.8V Output Voltage

Functional Description
4. Functional Description
4.1 MPU and Memory Subsystem
4.1.1 SAMA5D27 System-In-Package

The SAMA5D27 System-In-Package (SiP) (ATSAMA5D27C-LD2G-CU) integrates the ARM Cortex-A5 processor-
based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM in a single package.
By combining the high-performance, ultra-low power SAMA5D2 with LPDDR2-SDRAM in a single package, PCB
routing complexity, area and number of layers is reduced. This makes board design easier and lowers the overall
cost of the bill of materials. Board design is more robust by facilitating design for EMI, ESD and signal integrity.
For more information about the SiP, see Reference Documents. The sole reference documents for product
information on the SAMA5D2 and the LPDDR2-SDRAM memory are provided in this section.
The ATSAMA5D27C-LD2G-CU is available in a 361-ball TFBGA package.
Connections of the supplies and the system pins of the ATSAMA5D27C-LD2G-CU are described in the following
schematics.
Figure 4-1. SAMA5D27 SiP Schematic
U2F SAMA5D27C-LD2G-CU
Y2 24MHz XIN_24MHz W5 W7 DIFF90
PD23 1 3 XIN_24MHz XIN HHSDPA USBA_P
OE OUT W4 V7 DIFF90
VDD_3V3 XOUT HHSDMA USBA_N
2 4 XIN_32KHz U1 W8 DIFF90
GND VDD XIN32 HHSDPB USBB_P
C38 XOUT_32KHz T1 V8 DIFF90
DSC6003HI2B-024.0000 XOUT32 HHSDMB USBB_N
0.1uF
6.3V W9
HHSDPDATC HSIC_DATA
0201 P4 W10
SHDN SHDN HHSDMSTRC HSIC_STROBE
U2 V1
GND GND WKUP WKUP COMPP COMPP
V2
COMPN COMPN
W3
NRST NRST
R4
PIOBU0 PIOBU0_PMIC
R1 R5
RXD RXD PIOBU1 PIOBU1
Y1 R3
PIOBU2 PIOBU2
XIN_32KHz XOUT_32KHz VDDANA T4
PIOBU3 PIOBU3
M9 U3
32.768 Hz ADVREFP PIOBU4 PIOBU4
C18 C19 T5
6pF PIOBU5 PIOBU5
U5
8pF 8pF PIOBU6 PIOBU6
T3 P5
50V 50V JTAGSEL PIOBU7 PIOBU7
0201 0201
W2
CLK_AUDIO CLK_AUDIO
T2 V6
TST VBG
R11
GND GND 10K C17 R12
1% 10pF 5.62K
DNP
0201 25V 0201
0201 1%
GND
GND

Figure 4-2. SAMA5D27 SiP Decoupling Schematic

VDDIODDR VDDCORE
U2E SAMA5D27C-LD2G-CU 0402 4.7uF C20 U2G SAMA5D27C-LD2G-CU
0402 4.7uF C21 B15 A14 0402 4.7uF C22
DDRM_VDD12 DDRM_VSS
0402 4.7uF C23 B17 A19 0201 0.1uF C24 C3 A1
DDRM_VDD12 DDRM_VSS VDDCORE GNDCORE
0402 4.7uF C25 B19 B14 0201 0.1uF C26 C9 D9
0201 0.1uF C27 D15 B18 0201 0.1uF C28 K3 K4
0201 0.1uF C29 D17 C14 0201 0.1uF C30 U9 K7
0201 0.1uF C31 D19 C18 0201 0.1uF C32 W6 J11
0201 0.1uF C33 F15 D14 0201 0.1uF C34 V5 W1
0201 0.1uF C35 F17 D18 0201 0.1uF C36 K8 V9
DDRM_VDD12 DDRM_VSS VDDCORE-04 GNDCORE
0201 0.1uF C37 F19 E14 VDDFUSE
DDRM_VDD12 DDRM_VSS
0201 0.1uF C39 H15 E18 0201 0.1uF C40 U15 N9
DDRM_VDD12 DDRM_VSS VDDFUSE GNDDPLL
0201 0.1uF C41 H17 F14 VDDCORE
DDRM_VDD12 DDRM_VSS
0201 0.1uF C42 H19 F18 0201 0.1uF C43 U7
DDRM_VDD12 DDRM_VSS VDDHSIC VDDIODDR DDR_VREF (0V6)
0201 0.1uF C44 K15 G14 VDD_3V3
DDRM_VDD12 DDRM_VSS
0201 0.1uF C45 K17 G18 0201 0.1uF C46 B4 D4
DDRM_VDD12 DDRM_VSS VDDIOP0 GNDIOP0
0201 0.1uF C47 K19 H14 0201 0.1uF C48 D5 A5
DDRM_VDD12 DDRM_VSS VDDIOP0 GNDIOP0
0201 0.1uF C49 M15 H18
0201 0.1uF C50 DDRM_VDD12 DDRM_VSS
0201 0.1uF C51 R9
M17
DDRM_VDD12 DDRM_VSS
N14 V13
VDDIOP1 GNDIOP1
W13 C11
0201 0.1uF C52 M19 N17 0201 0.1uF C53 V18 W19 1.5k
DDRM_VDD12 DDRM_VSS VDDIOP1 GNDIOP1 0.1uF
0201 0.1uF C54 P15 N18 R13 0402
6.3V
0201 0.1uF C55 P17
DDRM_VDD12 DDRM_VSS
P14
GNDIOP1
P13 C12 1%
DDRM_VDD12 DDRM_VSS GNDIOP1 0201
0201 0.1uF C56 P19 P18 0201 0.1uF C57 A8 B9 4.7uF
DDRM_VDD12 DDRM_VSS VDDIOP2 GNDIOP2 10V
0201 0.1uF C58 T17 R14
0201 0.1uF C59 DDRM_VDD12 DDRM_VSS 0402 R10
T19
DDRM_VDD12 DDRM_VSS
R18 VDDANA C16
DDR_VREF T18 0201 0.1uF C60 G1 F1 1.5k
DDRM_VSS VDDANA GNDANA 0.1uF
0201 0.1uF C61 M12 0402 4.7uF C101 0402
DDR_VREF-01 6.3V
0201 0.1uF C62 J10 0201 0.1uF C63 H6 G5 1%
DDR_VREF-02 VDDANA GNDANA 0201
0402 4.7uF C64 VDDIODDR GND VDDBU
0402 4.7uF C65 E8 E10 0201 0.1uF C66 V3 U4
VDDDDR GNDDDR VDDBU GNDBU
0201 0.1uF C67 E11 F8 VDDISC VDDISC
VDDDDR GNDDDR GND GND
0201 0.1uF C68 H10 G10 0201 0.1uF C69 G3 H3
VDDDDR GNDDDR VDDISC GNDISC
0201 0.1uF C70 J8 J9 VDDOSC_PLL
VDDDDR GNDDDR C99
0201 0.1uF C71 J13 L11 0201 0.1uF C72 R6 P6
VDDDDR GNDDDR 4.7uF VDDAUDIOPLL GNDAUDIOPLL
0201 0.1uF C73 L10 M13 VDDUTMII
VDDDDR GNDDDR 10V
0201 0.1uF C74 P12 N12 0201 0.1uF C75 R8 R7
VDDDDR GNDDDR 0402 VDDUTMI GNDUTMI
VDD_DDR VDDCORE
0201 0.1uF C76 B11 0201 0.1uF C77 T6 U6
DDRM_VDD18 VDDUTMI_CORE GNDUTMI_CORE
B13 GND VDDOSC_PLL
DDRM_VDD18
0201 0.1uF C78 D11 GND 0201 0.1uF C79 R10 T11
DDRM_VDD18 VDDOSC GNDOSC
D13 VDDPLLA
DDRM_VDD18
0201 0.1uF C80 K13 0201 0.1uF C81 P9 P10
DDRM_VDD18 VDDPLLA GNDPLLA
K16 C19 R19 240R VDDSDHC
DDRM_VDD18 ZQ
0402 4.7uF C82 0201 1% 0201 0.1uF C83 T7 T8
VDDSDMMC GNDSDMMC
0201 10nF C100 C100
GND GND 4.7uF
10V
0402 GND
GND GND
4.1.2 Power Management Unit

The MCP16502 is a full-featured PMIC optimized for Microchip MPU devices.
The MCP16502 integrates four DC-DC buck regulators and two auxiliary LDOs, and provides a comprehensive
interface to the MPU, which includes an Interrupt flag and an I2C interface.
All buck channels can support loads up to 1A. All bucks are 100% duty cycle capable.
Two 300 mA LDOs are provided such that sensitive analog loads can be supported.
The default power channel sequencing is built-in, according to the requirements of the Microchip MPU device.
The MCP16502 features a low no-load operational quiescent current, and draws less than 10 uA in full shutdown.
Active discharge resistors are provided on each output. All buck channels support safe start-up into pre-biased
outputs.
The MCP16502 is available in a 32-pin 5 mm x 5 mm VQFN package with an operating junction temperature range
from –40°C to +125°C. It is AEC-Q100 Grade 2 (TAMB=105°C) qualified.

Figure 4-3. Power Management Unit Schematic

VDD_MAIN
R1
100k
0201
3
Q1
1 BSS138
PIOBU0_PMIC
2 U1 MCP16502AC-E/S8B VDD_MAIN VDDUTMII (3V3)
FB1 180R
LPM 22 10
LPM PVIN1
C1
GND BLM18PG181SN1D C97
R2 10K 23 4.7uF
GND HPM 4.7uF
0201 1% 10V
10V
R3 1k 8 12 0402
SHDN PWRHLD PGND1 0402
0201 1% C2 VDD_3V3
22uF
GND 10V GND VDDOSC_PLL (3V3)
L1 L2
24 11 1.5uH 0603 R4 2.2R 10uH
nSTART_SOM nSTRT SW1
9 DFE252012P-1R5M=P2 max 1A 0201 5%
OUT1 MLZ1608N100LT000 C3
4.7uF
VDD_MAIN
10V
15
PVIN2 0402
C4
4.7uF
17 10V GND
SELV2
VDD_3V3 13 0402
PGND2
R5 C5
0R 22uF
R6 0201 GND 10V VDDIODDR (1V2)
L3 max 1A
10K 14 1.5uH 0603
SW2
1% 16 DFE252012P-1R5M=P2
OUT2
0201
GND
1 VDD_MAIN
INT_MCP16502_PC8 nINTO
26
PVIN3
2 C6
NRST nRSTO
4.7uF
7 10V
WKUP nSTRTO
28 0402
PGND3
C7
5 22uF
TWD_MCP16502_PD19 SDA
GND 10V VDDCORE (1V25)
L4 max 1A
6 27 1.5uH 0603
TWCK_MCP16502_PD20 SCL SW3
25 DFE252012P-1R5M=P2
OUT3
VDD_MAIN
VDD_MAIN VDDPLLA (1V25)
L5
31 R8 2.2R 10uH
PVIN4
C8 0201 5% MLZ1608N100LT000
C98
4.7uF
4.7uF
10V
10V
18 29 0402
SELVL1 PGND4 0402
C9
22uF
GND 10V GND VDD_DDR (1V8)
L6 max 1A
30 1.5uH 0603
SW4
32 DFE252012P-1R5M=P2
OUT4
VDD_MAIN VDD_MAIN
4 20
SVIN LVIN
C10 VLDO1 (3V3)
max 0.3A
4.7uF 19
LOUT1
10V VLDO2 (1.8V - 3V3)
max 0.3A
0402 3 21
SGND LOUT2
33 C13 C14 C15
EP
4.7uF 4.7uF 4.7uF
10V 10V 10V
0402 0402 0402
GND
GND
4.1.3 SQI Memory
4.1.3.1 Description and Schematic

The ATSAMA5D27-WLSOM1 embeds the SST26VF064BEUIT-104I/MF, a 64 Mb Serial Quad I/O Flash memory.
The SST26VF064BEUIT-104I/MF SQI features a six-wire, 4-bit I/O interface that allows for low-power, high-
performance operation in a low pin-count package.
The SST26VF064BEUIT-104I/MF also embeds EUI-48 and EUI-64 MAC addresses.
The SST26VF064BEUIT-104I/MF is available in 8-lead WDFN package with 6 mm × 5 mm dimensions.
For more information, refer to the product web page.
It is possible to deselect the Chip Enable of the embedded QSPI to use an external one. In this case, the NCS_QSPI
pin must be left floating and the signal QSPI1_CS_PB6 must be connected to an external QSPI Chip Select.

Figure 4-4. QSPI Memory Schematic
VDD_3V3
R36 R37 R38 R39 R40 R41

10K 10K 10K 10K 10K 10K
DNP DNP DNP DNP DNP
1% 0201 0201 0201 0201 0201
0201 VDD_3V3
U7
R44 22R 5 8
QSPI1_IO0_PB7 SI/SIO0 VDD
R45 22R 2
QSPI1_IO1_PB8 SO/SIO1 C96
R46 22R 3
QSPI1_IO2_PB9 WP/SIO2 0.1uF
R47 22R 7
QSPI1_IO3_PB10 HOLD/SIO3 6.3V
R48 22R 6 4
QSPI1_SCK_PB5 SCK VSS 0201
1 9
CE TPAD
SST26VF064BEUIT-104I/MF
GND
R49 22R SCK_QSPI_PB5
R50 22R SIO3_QSPI_PB10
NCS_QSPI
4.1.3.2 MAC Address

The SST26VF064BEUI is pre-programmed at the factory with globally unique EUI-48 and EUI-64 node identifiers.
The addresses are located in the Serial Flash Discoverable Parameters (SFDP) table and accessible via the SFDP
read instruction.
The 6-byte EUI-48 address value of the SST26VF064BEUI is stored in the SFDP table at address locations 0x261
through 0x266.
The 8-byte EUI-64 address value of the SST26VF064BEUI is stored in the SFDP table at address locations 0x268
through 0x26F.
4.1.4 Secure Element

The Microchip ATECC608B-TNGTLS is the Trust&GO secure element part of the Trust Platform for the
CryptoAuthentication family. The device comes pre-configured and pre-provisioned with default thumbprint
certificates and key. The cloud infrastructure, whether it is a public or private network, must accommodate device
authentication relying only on the thumbprint certificate from the ATECC608B-TNGTLS. This secure element
integrates ECDH (Elliptic Curve Diffie Hellman) security protocol - an ultra-secure method to provide key agreement
for encryption/decryption - along with ECDSA (Elliptic Curve Digital Signature Algorithm) sign-verify authentication
for the Internet of Things (IoT) market, including home automation, industrial networking, medical, retail or any TLS
connected networks.
Figure 4-5. ECC608B Secure Element Schematic
VDD_3V3
R42 R43
VDD_3V3 2.2K 2.2K
0201 0201
U6 ATECC608B-TNGTLSU 1% 1%
8 3
VCC NC
C95 1 6
NC SCL TWCK_ECC608_PD22
0.1uF 2 5
NC SDA TWD_ECC608_PD21
PAD
6.3V 4 7
GND NC
0201
9
GND
GND

4.2 Power Management
4.2.1 Power Architecture

Basic operation of the ATSAMA5D27-WLSOM1 requires a +5.0V input voltage supply and a VDDBU (+1.65V to
+3.6V) input voltage supply, generally ensured by a backup battery. +5.0V power is supplied to the VDD_MAIN
domain.
As a general design rule, it is recommended to connect all input supply pins, except VDDFUSE which
CAUTION
must be connected to GND by a 100 Ohms resistor if not used, to your power supply and at least a
matching number of ground (GND) pins. For the best EMI performance, it is recommended to connect ALL
ground pins of the ATSAMA5D27-WLSOM1 module to a solid ground plane.
Power-on is controlled through the nSTART_SOM signal. This signal must be provided by the host board; for
example, via an automated reset controller or a push-button.
The ATSAMA5D27-WLSOM1 module can operate from a single voltage supply (VDD_MAIN) with a value comprised
between +3.0V and +5.5V and, with the MCP16502 PMIC device, internally generates the voltage supplies required
by the SAMA5D2 processor and on-board components.
The PMIC on-board switching regulators generate the 3.3V, 1.20V, 1.25V and 1.8V voltage supplies required by the
SAMA5D27 processor and on-board components.
The ATSAMA5D27-WLSOM1 delivers external power supplies to the main board application, such as VDD_DDR
(1.8V with 900 mA current capability), VDD_3V3 (3.3V with 600mA output current capability) and VLDO2 output
(1.8V to 3.3V with 300 mA output current capability).
Figure 4-6. ATSAMA5D27-WLSOM1 Power Architecture
WILC
KSZ SST ECC DSC DSC
3000
8081 26 608B 6003 6102
Digital
VDD_3V3
Up to 600mA
VDDBU SAMA5D27C-LD2G-CU
[1.65V .. 3.6V]
VDD_MAIN MCP16502AC
VDDISC
[3.0V .. 5.5V] 3.3V VDDISC
1
VDDANA
1.2V VDDANA
2 VDDFUSE
VDDFUSE
MIC DC/DCs
1.25V VDDSDHC
842 3 VDDSDMMC
1.8V
4
VDD_DDR
Up to 900mA
1.8 to 3.3V (Off by default) VLDO2

2 Up to 300mA
LDOs 3.3V WILC
1 3000
RF
ATSAMA5D27-WLSOM1

4.2.2 Various Power Configurations

Two different configurations are described below, depending on customer use.
• Single Supply—ATSAMA5D27-WLSOM1 can be supplied by only one input supply (for example, a 5V AC/DC
wall adapter) and other input supplies can be connected to the internal 3.3V regulator VDD_3V3. All the PIO
lines are supplied at 3.3V.
• Multiple Supplies—ATSAMA5D27-WLSOM1 can be supplied by 5V and by a backup battery. Some PIO lines
are supplied by different LDOs for specific applications, such as an ISC camera or a high-speed SD card.
4.2.2.1 Power Configurations: Single Supply

Figure 4-7. ATSAMA5D27-WLSOM1 Single Supply Connection Example
VDDBU
VDD_3V3
VDDISC
VDDANA
Input Supply
(3.0V - 5.5V) VDD_MAIN
VDDSDHC
Application Fuse
VDDFUSE
(2.5V)
Application Board
VDD_DDR (1.8V)
Application Board
VLDO2 (1.8V to 3.3V)
ATSAMA5D27-WLSOM1

4.2.2.2 Power Configurations: Multiple Supplies

Figure 4-8. ATSAMA5D27-WLSOM1 Multiple Supplies Connection Example
Backup
VDDBU
Battery
VDD_3V3
LDO
VDDISC (2.5V/2.8V/3.0V)
VDDANA
Input Supply
(3.0V - 5.5V) VDD_MAIN
LDO + Switch
VDDSDHC (3.3V/1.8V)
Application Fuse
VDDFUSE
(2.5V)
Application Board
VDD_DDR (1.8V)
Application Board
VLDO2 (1.8V to 3.3V)
ATSAMA5D27-WLSOM1
4.2.3 Power On/Off Sequences
4.2.3.1 LPDDR2 Power-Off Sequence

The LPDDR2 power-off sequence must be controlled by software to preserve the LPDDR2 device.
In this sequence, the CKE signal should be low during the full period the power rails are powering down.
The power failure can be controlled by the embedded Voltage Supervisor (MIC842) and handled at system level (IRQ
on PD31). The LPDDR2 power-off sequence is applied using the bit LPDDR2_LPDDR3_PWOFF in the MPDDRC
Low-Power register (MPDDRC_LPR).
For more information, refer to the following documents:
• SAMA5D2 Series Data sheet available on www.microchip.com/, sections LPDDR2 Power Fail Management and
MPDDRC Low-Power Register
• Jedec Standard Low Power Double Data Rate 2 (LPDDR2), JESD209-2B
Note: An uncontrolled power-off sequence can be applied only up to 400 times in the life of an LPDDR2 device.

4.2.3.2 Power ON/OFF Sequences for Single Supply

Figure 4-9. ATSAMA5D27-WLSOM1 Single Supply Connection: Power-On Sequence
SYSTEM STATUS OFF STARTUP POWER-UP NRST RELEASED SYSTEM BOOT I²C COMMAND VLDO2 POWER UP
VDD_MAIN 5.0V
nSTART_SOM a
t1
VDD_3V3 b
VDDBU
VDDANA
t2
VDDISC
VDDSDHC
VDD_DDR c
t3
NRST d
PMIC_I2C e
t4
VLDO2 f
Figure 4-10. ATSAMA5D27-WLSOM1 Single Supply Connection: Power-Off Sequence

SYSTEM STATUS SYSTEM ON POWER-OFF REQUEST NRST ASSERTS SYSTEM OFF
VDD_MAIN 5.0V
SHDN a
t2
VDD_3V3 b
VDDBU
VDDANA
VDDISC
VDDSDHC
VDD_DDR c
t3
NRST d
PMIC_I2C e
t1
VLDO2 f
Table 4-1. ATSAMA5D27-WLSOM1 Simple Supply Timing Table
Symbol Description Min. Typ. Max. Unit

t1 Power-Up Request Timing 0.5 – 2000 ms
t2 VDD_DDR Power-Up Timing – 8 – ms
t3 NRST Timing for Release – 16 – ms
t4 VLDO2 Power-Up Timing after I²C Request – 0.5 1 ms
t5 VLDO2 Power-Down Timing after I²C Request – – 1 ms
t6 VDD_3V3 Power-Down Timing – 10 – µs
t7 NRST Forced to Low Timing – – 10 µs

4.2.3.3 Power ON/OFF Sequences for Multiple Supplies

Figure 4-11. ATSAMA5D27-WLSOM1 Multiple Supplies Connections: Power-On Sequence
SYSTEM STATUS BACKUP STARTUP POWER-UP NRST RELEASED SYSTEM BOOT I²C COMMAND VLDO2 POWER UP
VDDBU 1.65V TO 3.6V
VDD_MAIN 5.0V
nSTART_SOM a
t1
VDD_3V3 b
VDDANA t2
VDDSDHC c t4 3.3V 1.8V

t3
VDDISC d
VDD_DDR e
t5
NRST f
PMIC_I2C g
t6
VLDO2 h
Figure 4-12. ATSAMA5D27-WLSOM1 Multiple Supplies Connections: Power-Off Sequence

SYSTEM STATUS SYSTEM ON POWER-OFF REQUEST NRST ASSERTS SYSTEM OFF
VDD_MAIN 5.0V
VDDBU 1.65V to 3.6V
SHDN a
t8
VDD_3V3 b
VDDANA
VDDISC
VDDSDHC
VDD_DDR c
t9
NRST d
PMIC_I2C e
t7
VLDO2 f
Table 4-2. ATSAMA5D27-WLSOM1 Multiple Supplies Timing Table
Symbol Description Min. Typ. Max. Unit

t1 Power-Up Request Timing 0.5 – 2000 ms
t2 VDDSDHC Power-Up Timing – 35 100 µs
t3 VDDISC Power-Up Timing – 40 100 µs
t4 VDD_DDR Power-Up Timing – 8 – ms
t5 NRST Timing for Release – 16 – ms
t6 VLDO2 Power-Up Timing after I²C Request – 0.5 1 ms
t7 VLDO2 Power-Down Timing after I²C Request – – 1 ms
t8 VDD_3V3 Power-Down Timing – 10 – µs
t9 NRST Forced to Low Timing – – 10 µs
4.2.4 Baseboard Power Delivery Application Diagram Example

The following figure is an example of power architecture at the baseboard level, input to the SOM and output from the
SOM.

Figure 4-13. Baseboard Power Delivery Application Diagram Example
LDO (3.3V)
(3.3V / 1.8V)
VDDSDHC VDD_3V3
REGULATOR
DC/DC MIC5353YMT SD-CARD
VDDANA
DCIN CONVERTER (5.0V)
VDDIN
(12V)
1V8 Output
MIC24051 SHDN
LDO VDDISC VLDO2

(2.5V) (1.8V-3.3V)
REGULATOR
MIC5259-2.5YD5 CAMERA
WLSOM1
SuperCap LDO
Charger REGULATOR VDDBU
(Discret Comp.) SuperCap MCP1810T-33
5.5V
GND
4.3 LAN Subsystem
4.3.1 Ethernet Phy

The Microchip ATSAMA5D27-WLSOM1 embeds a single-supply 10Base-T/100Base-TX Ethernet physical layer
transceiver for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081RNAIA is a highly-integrated PHY solution. The KSZ8081RNAIA offers the Reduced Media
Independent Interface (RMII) for direct connection to RMII-compliant MACs in Ethernet processors.
The KSZ8081RNAIA is available in 24-pin, lead-free QFN packages. For more information, refer to the product web
page.
Figure 4-14. Ethernet Phy Schematic
VDD_3V3
R20 R21
1k 1k
0201 0201
U3 KSZ8081RNAIA-TR
DIFF100 6 16
ETH_TX_P TXP REF_CLK ETH_GTXCK_PB14
DIFF100 5 21
ETH_TX_N TXM TXD1 ETH_GTX1_PB21
20
TXD0 ETH_GTX0_PB20
DIFF100 4 19
ETH_RX_P RXP TXEN ETH_GTXEN_PB15
DIFF100 3 12
ETH_RX_N RXM RXD1 ETH_GRX1_PB19
13
0402 10V 2.2uF C84 RXD0 ETH_GRX0_PB18
1 17
0201 0.1uF C85 VDD_1V2 RXER ETH_GRXER_PB17
15
6.3V CRS_DV/PHYAD[1_0] ETH_GRXDV_PB16
22 11
GND MDC ETH_GMDC_PB22
25 10
PADDLE MDIO ETH_GMDIO_PB23
18
INTRP ETH_INT_PB24
R22 6.49K 9 VDD_3V3
REXT TP10 FB2 180R
0201 1% 2
VDDA_3V3 R23
C86 C87 BLM18PG181SN1D
10K
10uF 0.1uF
GND 1%
6.3V 6.3V
0201
0402 0201
GND
Y3 25MHz
1 3 XIN_25MHz 8 14
PD24 OE OUT XI VDDIO GND
VDD_3V3 C88 C89
2 4 10uF 0.1uF R24
GND VDD
6.3V 6.3V 10K
C90
DSC6102HI2B-025.0000 0402 0201 1%
0.1uF GND
0201
6.3V
7 23
0201 XO LED0/ANEN_SPEED ETH_LED0
GND
24 R25 0R
RST NRST
GND 0201
4.3.2 Interfacing with the Ethernet Phy
4.3.2.1 Design Schematic Example

The figure below is a schematic example at main board level.

Figure 4-15. Ethernet Phy Schematic Example

J
TX+ TD+ 1
1 TCT 2
U1
2 TX- TD- 3
DIFF100 89
3 ETH_TX_P
DIFF100 88
ETH_TX_N
4 RX+ RD+ 4 DIFF100 87
ETH_RX_P
DIFF100 86
5 ETH_RX_N
RCT 5
6
RX- RD- 6 ATSAMA5D27-WLSOM1
7
C C
8 0.1uF 0.1uF
75R 10V 10V
75R 75R Green 0402 0402
11
FB 120R
Right 12 R 0R
Yellow GND_ETH 0402
75R BLM18PG121SN1D
VDD_3V3
9 R 470R
1nF Lift 10 5% 0402 U1
EARTH_ETH GND GND_ETH
84
ETH_LED0
CON RJ-45 JD2-0010NL
SHD
JD2-0010NL
ATSAMA5D27-WLSOM1
EARTH_ETH EARTH_ETH
4.3.2.2 Design Layout Recommendations

When designing the Ethernet interface, consider the following recommendations:
• ETH_TX_P, ETH_TX_N, ETH_RX_P and ETH_RX_N should be routed on the top layer without any vias. Traces
must be straight.
• ETH_TX_P and ETH_TX_N should be matched in length to within 120 mils.
• ETH_RX_P and ETH_RX_N should be matched in length to within 120 mils.
• ETH_TX_x and ETH_RX_x must be symmetric.
• Place the TX_P and TX_N signals at least 2 times the trace width away from other signals for noise immunity.
• Place signals at least 2 times the trace width away from any copper plan.
• Place the TX and RX signals at least 5 times the trace width away from other signals for noise immunity.
• Check that the ETH_TX_x and ETH_RX_x line impedance is the same for all signal layers. Recommended
differential impedance for net: 100Ω ± 5%.
4.3.2.3 Design Layout Example
4.4 Voltage Threshold Detector

The Microchip ATSAMA5D27-WLSOM1 embeds a MIC842 micro-power, precision-voltage comparator with an on-
chip voltage reference.
The device is intended for voltage monitoring applications. External resistors are used to set the voltage monitor
threshold. When the threshold is crossed, the outputs switch polarity. Refer to the figures below.

The MIC842 incorporates a voltage reference and comparator with fixed internal hysteresis; two external resistors are
used to set the switching threshold voltage.
Supply current is extremely low (1.5 μA, typical), making it ideal for portable applications.
The MIC842 is supplied in 4-pin 1.2 mm × 1.6 mm Thin DFN package. For more information, refer to the product web
page.
Figure 4-16. Voltage Threshold Detector Schematic
VDD_MAIN VDDANA
C94 0.1uF
0201 6.3V R27
100k
GND 0201
U5 MIC842NYMT-T5
4 1
VDD OUT INT_MIC842_PD31
R57 100R 3 2
EP
VTH INP GND
0201 1%
C104
EP
100pF
25V GND
0201
GND GND
Figure 4-17. Voltage Threshold Detector Implementation Example

Application Board WLSOM1 Module
VDD_MAIN VDDANA
V_SUPPLY
C94 0.1uF
0201 6.3V R27
100k
GND 0201
Rext1 U5 MIC842NYMT-T5
4 1
VDD OUT INT_MIC842_PD31
R57 100R 3 2
EP
VTH INP GND

0201 1%
C104
EP
Rext2 100pF
25V GND
0201
GND GND
GND
Table 4-3. Output Resistor Ladder Values and Input System Supply Example
System Supply Voltage Threshold Detection Value Rext1 Value Rext2 Value
5V 4.64V 787 kΩ 287 kΩ
12V 11V 787 kΩ 100 kΩ
24V 21.78V 787 kΩ 47.5 kΩ
48V 39.51V 787 kΩ 25.5 kΩ
4.5 Radio Subsystem

The ATSAMA5D27-WLSOM1 embeds an ATWILC3000-MR110UA module, which uses a single chip IEEE 802.11
b/g/n RF/Baseband/MAC link controller and Bluetooth 5. The ATWILC3000 connects to Microchip MPUs, with
minimal resource requirements with simple SDIO-to-Wi-Fi and UART-to-Bluetooth interfaces.
The ATWILC3000-MR110UA supports single stream 1x1 802.11n mode, providing tested throughput of up to 46
Mbps UDP & 28 Mbps TCP/IP. The ATWILC3000-MR110UA features fully integrated power amplifier, LNA, switch
and power management. Implemented in low-power CMOS technology, the ATWILC3000-MR110UA offers very low
power consumption while simultaneously providing high performance and minimal bill of materials.

The ATWILC3000-MR110UA utilizes highly -optimized 802.11 Bluetooth coexistence protocols. The only external
clock sources needed are a high-speed crystal or oscillator and a 32.768 kHz clock for sleep operation. In the
ATSAMA5D27-WLSOM1, the 32.768 kHz clock is provided by the ATSAMA5D27 through PB13.
Figure 4-18. Wi-Fi/BT Radio Subsystem Schematic
VDD_3V3 VLDO1 FB3 VDD_3V3
FB4 742792731
U4 ATWILC3000-MR110UA
742792731
VBAT 18 35
VBAT GPIO21 R28 R29 R30 R31 R32
0402 100R VDDIO 12 34
VDDIO GPIO0 68K 68K 68K 68K 10K
0402 100R 31
GPIO19 1% 1% 1% 1% 1%
30
C91 C92 C105 C93 GPIO18 0201 0201 0201 0201 0201
29
47uF 0.1uF 4.7uF 0.1uF GPIO17
14
10V 6.3V 10V 6.3V GPIO3 NC_3-WILC
32
0805 0201 0402 0201 GPIO20 NC_20-WILC
VDD_3V3 15
GPIO4
R26
27
10K SD_DAT3/GPIO7 SDIO_DAT3_WILC_PA21
GND 26
1% SD_DAT2/SPI_MOSI SDIO_DAT2_WILC_PA20
25
0201 SD_DAT1/SPI_SSN SDIO_DAT1_WILC_PA19
16 24
TXD_WILC_DBG UART_TXD SD_DAT0/SPI_MISO SDIO_DAT0_WILC_PA18
17 23
RXD_WILC_DBG UART_RXD SD_CMD/SPI_SCK SDIO_CMD_WILC_PA28
22
SD_CLK/GPIO8 SDIO_CK_WILC_PA22
33
INT_WILC_PB25 IRQN
7
NRST_WILC_PA27 RESETN
19 8
CE_WILC_PA29 CHIP_EN BT_TXD TXD_WILC_PA23
20 9
RTC_OUT_PB13 RTC_CLK BT_RXD RXD_WILC_PA24
2 10
SDIO/SPI_CFG BT_RTS RTS_WILC_PA25
11
BT_CTS CTS_WILC_PA26
R34 R35 3
C106 NC
10K 10K 4
PADDLE
10000pF NC
1% 1% 5
10V NC
GND
GND
GND
GND
GND
0201 0201 6
0201 NC
1
13
21
28
36
37
GND GND GND GND
GND
4.6 External Interfaces
4.6.1 Interfacing with an SD Card

The SD (Secure Digital) Card is a nonvolatile memory card format used as mass storage memory in mobile devices.
Secure Digital Multimedia Card (SDMMC) Controller
The ATSAMA5D27-WLSOM1 has one Secure Digital Multimedia Card (SDMMC) interface that supports the
MultiMedia Card (e.MMC) Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0
specification. It is compliant with the SD Host Controller Standard V3.0 specification.
The SDMMC0 interface can be connected to a standard SD card interface.
SDMMC0 Card Connector
The board features a standard MMC/SD card connector, connected to SDMMC0. The SDMMC0 communication is
based on a 4- or 8-pin interface (clock, command, four or eight data and power lines). It may include a card detection
switch.
4.6.1.1 Design Schematic Examples

The figures below illustrate the implementation for the SDMMC0 interface for a 4-bit interface and for an 8-bit
interface with a power switch for the supply of the digital interface for high-speed interface management.

Figure 4-19. 4-bit/8-bit SD Card Power Switch Example Schematic
VDD_1V8 VDD_3V3 VDDSDHC

C 0.1uF
U
2
VDD
4
S1
5
D
6
S2
U1
174 1 3
PA11 IN GND
R
10k ADG849
ATSAMA5D27-WLSOM1
Figure 4-20. 4-bit SD Card Interface Example Schematic

VDDSDHC
VDD_3V3
C C
R R R R R R R 0.1uF 4.7uF
10k 68k 68k 68k 68k 10k 10k
GND
U1 J
163 R 22R 0402 1% 1
PA5 DAT3
162 R 22R 0402 1% 2
PA1 CMD
3
VSS1
4
VDD
165 5
PA0 CLK
6
VSS2
166 R 22R 0402 1% 7
PA2 DAT0
164 R 22R 0402 1% 8
PA3 DAT1
169 R 22R 0402 1% 9
PA4 DAT2
175 10
PA13 CD
170 11
PA12 WP
12
SHIELD
SD
ATSAMA5D27-WLSOM1
GND

Figure 4-21. 8-bit SD Card Interface Example Schematic

VDDSDHC
VDD_3V3
C C
R R R R R R R R R R R 0.1uF 4.7uF
10k 68k 68k 68k 68k 68k 68k 68k 68k 10k 10k
GND
U1 J
163 R 22R 0402 1% 1
PA5 DAT3
162 R 22R 0402 1% 2
PA1 CMD
3
VSS1
4
VDD
165 5
PA0 CLK
166 R 22R 0402 1% 7
PA2 DAT0
164 R 22R 0402 1% 8 13
PA3 DAT1 DAT7
169 R 22R 0402 1% 9 12
PA4 DAT2 DAT6
175 6 11
PA13 CD DAT5
170 14 10
PA12 WP DAT4
15
SHIELD
SD
171 R 22R 0402 1% GND

PA6
173 R 22R 0402 1%
PA7
167 R 22R 0402 1%
PA8
172 R 22R 0402 1%
PA9
ATSAMA5D27-WLSOM1

When designing the SD Card interface, consider the following recommendations:
• Match signal lengths to within 50 mils. Affected PIOs in the example above are PA0 to PA5.
• Place the clock line (PA0) at least 3 times the trace width away from other signals for noise immunity.
• Apply impedance control of 50 Ohms on the clock and data interfaces.
• Place data signals at least 2 times the trace width away from any other data traces.
• Place data signals at least 1 trace width away from any copper plan.
Figure 4-22. SD Card Layout Example
Copper
Plane
W
Data
2W
Traces
W
3W
Clock
Trace W
3W
Data 2W
Traces
4.6.1.3 EMI Improvement Recommendations

To reduce radiation emission, consider the following recommendations:
• Position all the signals of the SD Card interface in inner layers of the PCB.
• Place the resistors as close as possible to the WLSOM1 module.

Figure 4-23. EMI Improvement Layout Example
TOP LAYER INNER LAYER
4.6.2 Interfacing with e-MMC

The Secure Digital Multimedia Card (SDMMC) Controller supports the Embedded MultiMedia Card (e-MMC)
Specification V4.41, the SD Memory Card Specification V3.0, and the SDIO V3.0 specification. It is compliant with the
SD Host Controller Standard V3.0 specification.
Table 4-4. SDMMC Reference Documents
Name Link
SD Host Controller Simplified Specification V3.00 www.sdcard.org
SDIO Simplified Specification V3.00 www.sdcard.org
Physical Layer Simplified Specification V3.01 www.sdcard.org
Embedded MultiMedia Card (e-MMC) Electrical Standard 4.51 www.jedec.org

In the example below, one MTFC4GLDEA 4 GB e-MMC is connected to the processor through the SDMMC0 port.
Figure 4-24. e-MMC Power Switch Example Schematic
VDD_1V8 VDD_3V3 VDDSDHC

C 0.1uF
U
2
VDD
4
S1
5
D
6
S2
U1
174 1 3
PA11 IN GND
R
10k ADG849
ATSAMA5D27-WLSOM1

Figure 4-25. e-MMC Interface Example Schematic

VDDSDHC VDD_3V3 VDDSDHC
C C
R R R R R R R R R R 0.1uF 2.2uF
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k C C
2.2uF 0.1uF
GND GND
M4
J10
N4
K9
C6
C2
E6
P3
P5
F5
U1
166 A3
PA2 DAT0
VCC0
VCC1
VCC2
VCC3
VCCQ1
VCCQ2
VCCQ3
VCCQ4
VCCQ5
VDDI
164 A4
PA3 DAT1
169 A5
PA4 DAT2
163 B2
PA5 DAT3
171 B3
PA6 DAT4
173 B4
PA7 DAT5
167 B5
PA8 DAT6
172 B6
PA9 DAT7
162 M5
PA1 CMD
165 M6
PA0 CLK
VSSQ1
VSSQ2
VSSQ3
VSSQ4
168 K5
nRST
VSS1
VSS2
VSS3
VSS4
VSS5
PA10
ATSAMA5D27-WLSOM1
N2
P6
P4
C4
G5
E7
H10
K8
N5
When designing the e-MMC interface, consider the following recommendations:
• Match signal lengths to within 50 mils. Affected PIOs in the example above are PA0 to PA9.
• Place the clock line (PA0) at least 3 times the trace width away from other signals for noise immunity.
• Place data signals at least 2 times the trace width away from any other data trace.
Figure 4-26. e-MMC Layout Example
Copper
Plane
W
Data
2W
Traces
W
3W
Clock
Trace W
3W
Data 2W
Traces
4.6.3 Interfacing with NAND Flash

This Static Memory Controller (SMC) is capable of handling several types of external memory and peripheral devices,
such as SRAM, PSRAM, PROM, EPROM, EEPROM, LCD module, NOR Flash and NAND Flash.
The SMC generates the signals that control the access to external memory devices or peripheral devices.
The SMC embeds a NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands
and address cycles to the NAND Flash and transferring the contents of the page (for read and write) to the NFC
SRAM. It minimizes the CPU overhead.
The SMC includes programmable hardware error correcting code with one-bit error correction capability and supports
two-bit error detection.

In order to improve the overall system performance, the DATA phase of the transfer can be DMA-assisted.

The example below is given with an 8-bit NAND Flash memory from Micron.
Figure 4-27. NAND Flash Interface Example Schematic
VDD_3V3 VDDSDHC
R R R
10k 10k 10k
U1
U1 U
174 16 29 165
PA11 CLE I/O0 PA0
168 17 30 162
PA10 ALE I/O1 PA1
170 8 31 166
PA12 RE I/O2 PA2
167 18 32 164
PA8 WE I/O3 PA3
172 9 41 169
PA9 CE I/O4 PA4
42 163
I/O5 PA5
169 7 43 171
PA4 R/B I/O6 PA6
44 173
I/O7 PA7
19
WP
26
NC
R
DNP10k
TSOP-48 NC
27
28
NC ATSAMA5D27-WLSOM1
1 33
ATSAMA5D27-WLSOM1 NC NC
2 35
NC NC
3 40
NC NC
4 45
NC NC
5 46
GND NC NC
6
NC
10 38
NC DNU
11 47
NC DNU VDDSDHC
14
NC
15 12
NC Vcc
20 37
NC Vcc
21 34
NC Vcc1
22 39 C C C C
NC Vcc1
23 0.1uF 0.1uF 0.1uF 0.1uF
NC
24 13
NC Vss
36
Vss
25
Vss1
48
Vss1
MT29F4G08ABAEAWP:E TR
GND

When designing the NAND Flash interface, consider the following recommendations:
• Match signal lengths to within 50 mils. Affected PIOs in the example schematic above are PA0 to PA7. For EMI
improvement, all these nets should be placed in inner layers.
Figure 4-28. NAND Flash Layout Example
Copper
Plane
W
Data
2W
Traces
W
4.6.4 Interfacing with an Image Sensor Controller (ISC)

The Image Sensor Controller (ISC) system manages incoming data from a parallel sensor. It supports a single active
interface. The parallel interface protocol can use a free-running clock or a gated clock strategy. It supports the ITU-R
BT 656/1120 422 protocol with a data width of 8 bits or 10 bits and raw Bayer format. The internal image processor
includes adjustable white balance, color filter array interpolation, color correction, gamma correction, 12-bit to 10-bit

compression, programmable color space conversion and horizontal and vertical chrominance subsampling module.
The module also integrates a triple channel Direct Memory Access Controller host interface.

The example schematics shown below are for different Image Sensor supply voltages.
Figure 4-29. Camera Interface Example Schematic with VDDISC Set at 3.3V
VDD_3V3 DOVDD_2V8 DOVDD_2V8
R R R
200k 4k7 4k7
C53 C
0.1uF U 0.1uF
25V 0402 2 7 25V 0402
GND VREF1 VREF2 GND
U1
122 ISC_TWCK 3 6
PD20 SCL1 SCL2 ISI_SCL
120 ISC_TWD 4 5
PD19 SDA1 SDA2 ISI_SDA
1 8
GND EN
ATSAMA5D27-WLSOM1
PCA9306DCUR
VDD_3V3 AVDD_3V GND

U
1 5
VIN VOUT IMAGE SENSOR CONNECTOR
J IMAGE SENSOR
C C 1
3
1uF EN 1uF 2
4 2 U1 U 3
NC GND 1 20 ISI_SDA
66 ISI_MCK R 22R 0402 1%
A1 B1 4
PC24
3 18
XCLK AVDD_3V
MIC5366-3.0YC5 PC7
177 ISI_PWD
A2 B2 5
4 17
PWDN ISI_SCL
61 ISI_RST
A3 B3 6
R 0R PC25
5 16
RESET RESET
65 ISI_VSYNC R 22R 0402 1%
A4 B4 7
PC22
6 15
VSYNC VSYNC
59 ISI_HSYNC R 22R 0402 1%
A5 B5 8
PC23
ISI_PCK 7 14
HREF PWDN
63 R 22R 0402 1%
A6 B6 9
PC21
69 ISI_D0 8 13
PCLK HREF
GND AGND PC9
R 22R 0402 1%
A7 B7 10
60 ISI_D1 9 12
Y2 DVDD_1V5
PC10
R 22R 0402 1% A8 B8 11
Y3 DOVDD_2V8
VDD_3V3 12
DOVDD_2V8 Y9
13
ATSAMA5D27-WLSOM1 2 19 XCLK
VCCA VCCB 14
10 Y8
C OE C 15
0.1uF 0.1uF 16
VDD_3V3 DOVDD_2V8 Y7
17
U 11 PCLK
GND 18
1 5 Y6
VIN VOUT 19
TXB0108 Y2
C C 20
3 Y5
1uF EN 1uF 21
GND GND Y3
22
4 2 Y4
NC GND 23
U 24
MIC5366-2.8YC5 U1
68 ISI_D2 R 22R 0402 1% 1 20
PC11 A1 B1 Y4
67 ISI_D3 R 22R 0402 1% 3 18 Molex_52437-2491
GND GND PC12 A2 B2 Y5
64 ISI_D4 R 22R 0402 1% 4 17
PC13 A3 B3 Y6
62 ISI_D5 R 22R 0402 1% 5 16 AGND GND
PC14 A4 B4 Y7
71 ISI_D6 R 22R 0402 1% 6 15
VDD_3V3 DVDD_1V5 PC15 A5 B5 Y8
57 ISI_D7 R 22R 0402 1% 7 14
U PC16 A6 B6 Y9
8 13
1 5 A7 B7
VIN VOUT 9 A8 B8 12
C C VDD_3V3
3 DOVDD_2V8
1uF EN 1uF
ATSAMA5D27-WLSOM1 2 19
4 2 VCCA VCCB
NC GND 10
C OE C
MIC5366-1.5YC5 0.1uF 0.1uF
11
GND GND GND
TXB0108
GND GND
Figure 4-30. Camera Interface Example Schematic with VDDISC Set at Specific Voltage
VDD_3V3 DOVDD_2V8 DOVDD_2V8
R R R
200k 4k7 4k7
C53 C
0.1uF U 0.1uF
25V 0402 2 7 25V 0402
GND VREF1 VREF2 GND
U1
122 ISC_TWCK 3 6
120 ISC_TWD 4 5
1
GND EN
8 IMAGE SENSOR CONNECTOR
J IMAGE SENSOR
ATSAMA5D27-WLSOM1 1
PCA9306DCUR 2
3
ISI_SDA
4
AVDD_3V
VDD_3V3 AVDD_3V U1 5
GND ISI_SCL
U 61 RESET 6
PC25
1 5 65 VSYNC R 22R 0402 1% 7
PC22
VIN VOUT 177 PWDN 8
PC7
C C 59 HREF R 22R 0402 1% 9
3 PC23
1uF EN 1uF 10
DVDD_1V5
4 2 DOVDD 11
NC GND VDD_ISC
57 Y9 R 22R 0402 1% 12
PC16
MIC5366-3.0YC5 66 XCLK R 22R 0402 1% 13
PC24
71 Y8 R 22R 0402 1% 14
R 0R PC15
15
62 Y7 R 22R 0402 1% 16
PC14
63 PCLK R 22R 0402 1% 17
PC21
GND AGND 64 Y6 R 22R 0402 1% 18
PC13
69 Y2 R 22R 0402 1% 19
PC9
67 Y5 R 22R 0402 1% 20
VDD_3V3 DVDD_1V5 PC12
60 Y3 R 22R 0402 1% 21
PC10
U 68 Y4 R 22R 0402 1% 22
PC11
1 5 23
VIN VOUT
C C 24
3 ATSAMA5D27-WLSOM1
1uF EN 1uF
Molex_52437-2491
4 2
NC GND
MIC5366-1.5YC5 AGND GND
GND GND

When designing the ISC interface, consider the following recommendations:
• Match signal lengths to within 50 mils. Affected PIOs in the example above are PC9 to PC24.
• Place the clock lines (PC21 and PC24) at least 3 times the trace width away from other signals for noise
immunity.
• Place data signals at least 2 times the trace width away from any other data traces.

• Place data signals at least 2 times the trace width away from any copper plan.
Figure 4-31. ISC Layout Example
Copper
Plane
2W
Data
2W
Traces
W
3W
Clock
Trace W
3W
Data 2W
Traces

• Position the ISC bus interface in inner layers of the PCB.
• Add a ferrite bead on PCLK and on XCLK clocks lines.
• Add a ferrite bead on the camera power supply.
• Select a shielded camera connector.
Figure 4-32. EMI Improvement Example
3V3_VIN DOVDD_2V8 DOVDD_2V8
R R R
200k 4k7 4k7
C53 C
0.1uF U 0.1uF
25V 0402 2 7 25V 0402
GND VREF1 VREF2 GND
U1
122 ISC_TWCK 3 6
120 ISC_TWD 4 5
1
GND EN
8 IMAGE SENSOR CONNECTOR
J IMAGE SENSOR
ATSAMA5D27-WLSOM1 1
PCA9306DCUR 2
3
ISI_SDA
4
AVDD_3V
3V3_IN AVDD_3V U1 5
GND ISI_SCL
U 61 RESET 6
PC25
1 5 65 VSYNC R 22R 0402 1% 7
PC22
VIN VOUT 177 PWDN 8
PC7
C C 59 HREF R 22R 0402 1% 9
3 PC23
1uF EN 1uF 10
DVDD_1V5
4 2 DOVDD 11
NC GND VDD_ISC
57 Y9 R 22R 0402 1% 12
PC16
MIC5366-3.0YC5 66 XCLK FB* 220R 13
PC24
71 Y8 R 22R 0402 1% 14
R 0R PC15
15
62 Y7 R 22R 0402 1% 16
PC14
63 PCLK FB* 220R 17
PC21
GND AGND 64 Y6 R 22R 0402 1% 18
PC13
69 Y2 R 22R 0402 1% 19
PC9
67 Y5 R 22R 0402 1% 20
3V3_VIN DVDD_1V5 PC12
60 Y3 R 22R 0402 1% 21
PC10
VDD_3V3 BLM18PG300SN1D U 68 Y4 R 22R 0402 1% 22
FB PC11
30R 1 5 23
VIN VOUT
C C 24
3 ATSAMA5D27-WLSOM1 *BLM18AG221SN1D
C C 1uF EN 1uF
0.1uF 1uF Molex_52437-2491
4 2
10V 10V NC GND
0402 0402 AGND GND
MIC5366-1.5YC5
GND GND GND GND
4.6.5 Connecting to the SPI Interface

Four different FLEXCOM interfaces, with seven possible configurations (configured in SPI mode), and two pure SPI
Interfaces, with four possible configurations, are available on the ATSAMA5D27-WLSOM1 module.
The Flexible Serial Communication Controller (FLEXCOM) offers several serial communication protocols that are
managed by the three submodules USART, SPI, and TWI.
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with
external devices in Host or Client mode. It also enables communication between processors if an external processor
is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPI devices.
During a data transfer, one SPI system acts as the “host”' which controls the data flow, while the other devices act
as “clients'' which have data shifted into and out by the host. Different CPUs can take turn being hosts (multiple host
protocol, contrary to single host protocol where one CPU is always the host while all of the others are always clients).
One host can simultaneously shift data into multiple clients. However, only one client can drive its output to write data
back to the host at any given time.
A client device is selected when the host asserts its NSS signal. If multiple client devices exist, the host generates a
separate client select signal for each client (NPCS).
The SPI system consists of two data lines and two control lines:
• Host Out Client In (MOSI)—This data line supplies the output data from the host shifted into the input(s) of the
client(s).
• Host In Client Out (MISO)—This data line supplies the output data from a client to the input of the host. There
may be no more than one client transmitting data during any particular transfer.
• Serial Clock (SPCK)—This control line is driven by the host and regulates the flow of the data bits. The host can
transmit data at a variety of baud rates; there is one SPCK pulse for each bit that is transmitted.
• Client Select (NSS)—This control line allows clients to be turned on and off by hardware.
Table 4-5. SPI Interface Configurations
Interface Instance IO set Pin # PIO Pin Name Comments

SPI0 1 21 PA14 SPI0_SPCK
SPI0 1 22 PA15 SPI0_MOSI
SPI0 1 23 PA16 SPI0_MISO
SPI0 1 24 PA17 SPI0_NPCS0
SPI0 2 76 PA30 SPI0_NPCS0
SPI0 2 75 PA31 SPI0_MISO
SPI0 2 81 PB00 SPI0_MOSI
SPI0 2 80 PB01 SPI0_SPCK
SPI0 1 18 PC01 SPI1_SPCK
SPI1 1 17 PC02 SPI1_MOSI
SPI1 1 16 PC03 SPI1_MISO
SPI1 1 19 PC04 SPI1_NPCS0
SPI1 3 132 PD25 SPI1_SPCK
SPI1 3 127 PD26 SPI1_MOSI
SPI1 3 123 PD27 SPI1_MISO
SPI1 3 124 PD28 SPI1_NPCS0

Table 4-6. FLEXCOM Interfaces Configurations in SPI Mode
Interface Instance IO set Pin # PIO Pin Name Comments

FLEXCOM0 1 28 PB28 FLEXCOM0_IO0 MOSI Signal
FLEXCOM0 1 27 PB29 FLEXCOM0_IO1 MISO Signal
FLEXCOM0 1 30 PB30 FLEXCOM0_IO2 SPCK Signal
FLEXCOM0 1 26 PB31 FLEXCOM0_IO3 NPCS0 Signal
FLEXCOM0 1 15 PC00 FLEXCOM0_IO4 NPCS1 Signal
FLEXCOM2 1 171 PA06 FLEXCOM2_IO0 MOSI Signal
FLEXCOM2 1 173 PA07 FLEXCOM2_IO1 MISO Signal
FLEXCOM2 1 167 PA08 FLEXCOM2_IO2 SPCK Signal
FLEXCOM2 1 172 PA09 FLEXCOM2_IO3 NPCS0 Signal
FLEXCOM2 1 168 PA10 FLEXCOM2_IO4 NPCS1 Signal
FLEXCOM2 2 127 PD26 FLEXCOM2_IO0 MOSI Signal
FLEXCOM2 2 123 PD27 FLEXCOM2_IO1 MISO Signal
FLEXCOM2 2 124 PD28 FLEXCOM2_IO2 SPCK Signal
FLEXCOM2 2 131 PD29 FLEXCOM2_IO3 NPCS0 Signal
FLEXCOM3 2 56 PC18 FLEXCOM3_IO2 SPCK Signal
FLEXCOM3 2 70 PC19 FLEXCOM3_IO1 MISO Signal
FLEXCOM3 2 58 PC20 FLEXCOM3_IO0 MOSI Signal
FLEXCOM4 1 39 PC28 FLEXCOM4_IO0 MOSI Signal
FLEXCOM4 1 38 PC29 FLEXCOM4_IO1 MISO Signal
FLEXCOM4 1 34 PC30 FLEXCOM4_IO2 SPCK Signal
FLEXCOM4 2 119 PD12 FLEXCOM4_IO0 MOSI Signal
FLEXCOM4 2 116 PD13 FLEXCOM4_IO1 MISO Signal
FLEXCOM4 2 117 PD14 FLEXCOM4_IO2 SPCK Signal
4.6.6 Connecting to the I²C Interface

Four different FLEXCOM interfaces, with seven possible configurations (configured in TWI mode), and one pure TWI
Interface are available on the ATSAMA5D27-WLSOM1 module.
The Flexible Serial Communication Controller (FLEXCOM) offers several serial communication protocols that are
managed by the three submodules USART, SPI, and TWI.

The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and
one data line with speeds of up to 400 kbit/s in Fast mode and up to 3.4 Mbit/s in High-Speed Client mode only,
based on a byte-oriented transfer format.
It can be used with any Two-wire Interface bus Serial EEPROM and I²C-compatible devices, such as a Real-Time
Clock (RTC), Dot Matrix/Graphic LCD Controller and temperature sensor. The TWI is programmable as a host or a
client with sequential or single-byte access. Multiple host capability is supported.
Table 4-7. I²C Interface Configurations
Interface
IO Set Pin # PIO Pin Name Comment
Instance
TWI1 3 120 PD19 TWD1 No need of external pull-up. Already integrated in ATSAMA5D27-
TWI1 3 122 PD20 TWCK1 WLSOM1 module
FLEXCOM0 1 28 PB28 FLEXCOM0_IO0

FLEXCOM0 1 27 PB29 FLEXCOM0_IO1
FLEXCOM2 1 171 PA6 FLEXCOM2_IO0
FLEXCOM2 1 173 PA7 FLEXCOM2_IO1
FLEXCOM2 2 127 PD26 FLEXCOM2_IO0
FLEXCOM3 1 22 PA15 FLEXCOM3_IO0 Need external pull-up in case the FLEXCOM interface is used as an
FLEXCOM3 1 175 PA13 FLEXCOM3_IO1 I²C/TWI interface.
FLEXCOM3 2 58 PC20 FLEXCOM3_IO0
4.6.7 Interfacing with CLASS-D Audio Output

The Audio Class D Amplifier (CLASSD) is a digital input, pulse width modulated (PWM) output mono Class D
amplifier. It features a high-quality interpolation filter embedding a digitally controlled gain, an equalizer and a
de-emphasis filter.
On its input side, the CLASSD is compatible with most common audio data rates. On the output side, its PWM output
can drive either:
• high-impedance single-ended or differential output loads (Audio DAC application) or,
• external MOSFETs through an integrated nonoverlapping circuit (Class D power amplifier application).

Figure 4-33. CLASS-D Interface Example Schematic

MAIN_VOLT
(Up to 12V)
C C C C
10uF 10uF 10uF 10uF
R D 25V 25V 25V 25V
10k
1N4148W
R C
1 2
Q
22R 10000pF SSM3J56ACT GND
25V 3
3
Q
R
1 SSM3K56ACT
U1 2
22R
80 CLASSD_R0
PB1
PB2
79 CLASSD_R1 R
PB3
78 CLASSD_R2 10k FB
77 CLASSD_R3 0402 J
PB4
4
BLM18PG181SN1D 3
2
GND GND 1
FB
ATSAMA5D27-WLSOM1
TERMINAL 1x4
BLM18PG181SN1D
R D
10k
1N4148W
R C
1 2
Q
22R 10000pF SSM3J56ACT
25V 3
GND
3
Q
R
1 SSM3K56ACT
22R 2
R
10k
GND GND
4.6.8 QTouch® Peripheral Touch Controller (PTC)

For details on implementing the PTC, refer to the documents listed below:
Title Document Type Literature Number

QTAN0079 – Buttons, Sliders and Wheels Sensor Design Guide Design Guide 10752
AN_2585: Implementing a QTouch PTC Subsystem on SAMA5D2 MPU Application Note DS000002585
AN_2472: QTouch on SAMA5D2 MPU Application Note DS000002472
4.6.9 Interfacing with an LCD

The ATSAMA5D27-WLSOM1 features an 18-bit RGB LCD interface.
The figure below is a schematic example at main board level illustrating the interface with the AC32005 Microchip
display module (WVGA LCD display module with maXTouch® technology).
In this example, several interfaces are used:
• LCD _xxx signals for display
• one SPI interface for display configuration
• one TWI interface for maXTouch and QTouch device control
• two IRQ I/Os for capacitive touch and buttons interruption

Figure 4-34. LCD Schematic Example
U1D J21
69 LCD_ID_PC09 1
PC9
2
3
4
60 R 22R 0402 1% LCD_D2_PC10 5
PC10
68 R 22R 0402 1% LCD_D3_PC11 6
PC11
7
67 R 22R 0402 1% LCD_D4_PC12 8
PC12
64 R 22R 0402 1% LCD_D5_PC13 9
PC13
62 R 22R 0402 1% LCD_D6_PC14 10
PC14
71 R 22R 0402 1% LCD_D7_PC15 11
PC15
12
13
14
57 R 22R 0402 1% LCD_D10_PC16 15
PC16
72 R 22R 0402 1% LCD_D11_PC17 16
PC17
17
56 R 22R 0402 1% LCD_D12_PC18 18
PC18
70 R 22R 0402 1% LCD_D13_PC19 19
PC19
58 R 22R 0402 1% LCD_D14_PC20 20
PC20
63 R 22R 0402 1% LCD_D15_PC21 21
PC21
22
23
24
65 R 22R 0402 1% LCD_D18_PC22 25
PC22
59 R 22R 0402 1% LCD_D19_PC23 26
PC23
27
66 R 22R 0402 1% LCD_D20_PC24 28
PC24
61 R 22R 0402 1% LCD_D21_PC25 29
PC25
37 R 22R 0402 1% LCD_D22_PC26 30
PC26
35 R 22R 0402 1% LCD_D23_PC27 31
PC27
32
33 R 39R 0402 1% LCD_PCLK_PD00 33
PD00
34 R 22R 0402 1% LCD_VSYNC_PC30 34
PC30
36 R 22R 0402 1% LCD_HSYNC_PC31 35
PC31
32 R 22R 0402 1% LCD_DATA_EN_PD01 36
PD1
18 SPI1_SPCK_LCD_PC01 37
PC1
17 SPI1_MOSI_LCD_PC02 38
PC2
16 SPI1_MISO_LCD_PC03 39
PC3
176 SPI1_NPCS2_LCD_PC06 40
PC6
38 R 22R 0402 1% LCD_EN_PC29 41
PC29
120 TWD1_LCD_PD19 42
PD19
122 TWCK1_LCD_PD20 43
PD20
77 LCD_IRQ1_PB04 44
PB4
24 LCD_IRQ2_PA17 45
PA17
39 R 22R 0402 1% LCD_PWM_PC28 46
PC28
7 NRST 47
nRST
48
ATSAMA5D27-WLSOM1 49
VDD_MAIN
50
C FFC
MNT
1uF
10V
FFC/FPC 50P Female
0402
GND GND

When designing the LCD interface, consider the following recommendations:
• Match the LCD signal lengths to within 50 mils. Affected PIOs in the example above are PC10 to PC27, PC30,
PC31, PD0 and PD1.
• Place the clock line (PD0) at least 3 times the trace width away from other signals for noise immunity.
• Design data signals at least 2 times the trace width away from any copper plan.

Figure 4-35. LCD Layout Example
Copper
Plane
2W
Data
2W
Traces
W
3W
Clock
Trace W
3W
Data 2W
Traces

• Position the LCD bus interface in inner layers of the PCB.
• Add a ferrite bead on the CLK line.
• Add a ferrite bead on the LCD power supply.
• Select a shielded LCD connector.

Figure 4-36. EMI Improvement Layout Example
U1D J21
69 LCD_ID_PC09 1
PC09
2
3
4
60 R 22R 0402 1% LCD_D2_PC10 5
PC10
68 R 22R 0402 1% LCD_D3_PC11 6
PC11
7
67 R 22R 0402 1% LCD_D4_PC12 8
PC12
64 R 22R 0402 1% LCD_D5_PC13 9
PC13
62 R 22R 0402 1% LCD_D6_PC14 10
PC14
71 R 22R 0402 1% LCD_D7_PC15 11
PC15
12
13
14
57 R 22R 0402 1% LCD_D10_PC16 15
PC16
72 R 22R 0402 1% LCD_D11_PC17 16
PC17
17
56 R 22R 0402 1% LCD_D12_PC18 18
PC18
70 R 22R 0402 1% LCD_D13_PC19 19
PC19
58 R 22R 0402 1% LCD_D14_PC20 20
PC20
63 R 22R 0402 1% LCD_D15_PC21 21
PC21
22
23
24
65 R 22R 0402 1% LCD_D18_PC22 25
PC22
59 R 22R 0402 1% LCD_D19_PC23 26
PC23
27
66 R 22R 0402 1% LCD_D20_PC24 28
PC24
61 R 22R 0402 1% LCD_D21_PC25 29
PC25
37 R 22R 0402 1% LCD_D22_PC26 30
PC26
35 R 22R 0402 1% LCD_D23_PC27 31
PC27
BLM18AG221SN1D 32
33 FB 220R LCD_PCLK_PD00 33
PD00
34 R 22R 0402 1% LCD_VSYNC_PC30 34
PC30
36 R 22R 0402 1% LCD_HSYNC_PC31 35
PC31
32 R 22R 0402 1% LCD_DATA_EN_PD01 36
PD01
18 SPI1_SPCK_LCD_PC01 37
PC01
17 SPI1_MOSI_LCD_PC02 38
PC02
16 SPI1_MISO_LCD_PC03 39
PC03
176 SPI1_NPCS2_LCD_PC06 40
PC06
38 R 22R 0402 1% LCD_EN_PC29 41
PC29
120 TWD1_LCD_PD19 42
PD19
122 TWCK1_LCD_PD20 43
PD20
77 LCD_IRQ1_PB04 44
PB04
24 LCD_IRQ2_PA17 45
PA17
39 R 22R 0402 1% LCD_PWM_PC28 46
PC28
7 NRST 47
nRST
BLM18PG300SN1D 48
ATSAMA5D27-WLSOM1 FB 30R 49
VDD_MAIN
50
C C FFC
MNT
0.1uF 1uF
10V 10V
FFC/FPC 50P Female
0402 0402
GND GND GND

Electrical Characteristics
5. Electrical Characteristics
5.1 Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 5-1. Absolute Maximum Ratings
Characteristic Symbol Min. Max. Unit

I/O Supply Voltage VDDANA, VDDISC, VDDSDHC -0.3 4.0 V
Fuse Supply Voltage VDDFUSE -0.3 3.0 V
Main Supply Voltage VDD_MAIN -0.3 6.0 V
Backup Supply Voltage VDDBU -0.3 4.0 V
Storage Temperature TSTORAGE -55 150 °C
RF Input Power Maximum – – 23 dBm
Maximum Input Current VDD_MAIN – 2 A
5.2 Recommended Operating Conditions

The following table provides the operating ratings for the ATSAMA5D27-WLSOM1 module.
Table 5-2. Recommended Operating Ratings
Characteristic Symbol Min. Max. Unit

I/O Supply Voltage VDDANA, VDDISC, VDDSDHC 1.6 3.6 V
Fuse Supply Voltage VDDFUSE 2.25 2.75 V
Main Supply Voltage VDD_MAIN 3.0 5.5 V
Backup Supply Voltage VDDBU 1.65 3.6 V
Operating Temperature TA -40 85 °C
5.3 DC Characteristics
The following characteristics are applicable to the operating temperature range TA = -40°C to +85°C, unless
otherwise specified.
Table 5-3. DC Electrical Characteristics for GPIO Inputs
Pad Parameters Conditions Min. Typ. Max. Unit

VIL Low-level Input Voltage All GPIO @ 3.3V -0.3 – 0.4 V
VIH High-level Input Voltage All GPIO @ 3.3V 2.3 – 3.6 V
VOL Low-level Output Voltage I0 Max. – – 0.41 V
VOH High-level Output Voltage I0 Max. 2.9 – – V

Pad Parameters Conditions Min. Typ. Max. Unit
IIL Low-level Input Current All GPIO @ 3.3V -1 – 1 µA
IIH High-level Input Current All GPIO @ 3.3V -1 – 1 µA
All GPIO @ 3.3V / Low -2 – – mA
IOL Low-level Output Current
All GPIO @ 3.3V / High -32 – – mA
All GPIO @ 3.3V / Low – – 2 mA
IOH High-level Output Current
All GPIO @ 3.3V / High – – 32 mA
5.4 Power Consumption
5.4.1 Hardware Setup

The following figure illustrates the hardware architecture and the position of ammeters for the measurements
performed on ATSAMA5D27-WLSOM1-EK1 board.
ATSAMA5D27-WLSOM1 IVDD_3V3
VDD_3V3 A
IVDDBU
SDMMC
LDO 3.3 V A VDDBU SDMMC
VDDANA
IVDD_MAIN VDDISC
VDDSDHC
MIKROE-1649
A VDD_MAIN SPI
mikroBUS
TWI
(5.0V)
RGB
MIKROE-2000
mikroBUS
ZiF LCD
ZiF LCD
LCD + TOUCH TM5000B
5.4.2 Software Setup and Command
5.4.2.1 Software Setup

The Linux image used for the tests is available on Linux4SAM.org.
The board web page is here: www.linux4sam.org/bin/view/Linux4SAM/Sama5d27WLSom1EKMainPage.
The image used is the Buildroot Based Demo with PDA5" configuration, available in the Demo archives section of the
page.
5.4.2.2 Software Commands

To activate various interfaces, the following commands are used:
For Wi-Fi activity

modprobe wilc-sdio
wpa_supplicant -Dnl80211 -iwlan0 -c/etc/wpa_supplicant.conf &
wpa_cli -iwlan0 -p/var/run/wpa_supplicant add_network
wpa_cli -iwlan0 -p/var/run/wpa_supplicant set_network 2 ssid '"IPERF_TEST"'

wpa_cli -iwlan0 -p/var/run/wpa_supplicant set_network 2 key_mgmt WPA-PSK

wpa_cli -iwlan0 -p/var/run/wpa_supplicant set_network 2 psk '"12345678"'
wpa_cli -iwlan0 -p/var/run/wpa_supplicant select_network 2
udhcpc -iwlan0 &
iperf -s -i 1 -w 512k & (At WLSOM terminal)
iperf -c 192.168.1.3 -i 1 -t 300 -w 512k (At PC terminal)
For Ethernet activity

ping 192.168.1.2 &
For SD Card Read/Write activity

sh sdcardtest.sh &
For USB Host Copy activity

sh copy.sh &
For OLED activity

sh oledtest.sh &
For Heart Beat activity

python hr_click_board.py &
For LCD activity

sh lcdtest.sh &
5.4.2.3 Current Consumption Measurements in Linux Environment
Scenario N°1 Scenario N°2 Scenario N°3 Scenario N°4 Scenario N°5 Scenario N°6
Before Boot. Wi-Fi + Ethernet + USB

Scenario Setup Wi-Fi Activity Wi-Fi + Ethernet Wi-Fi + SD Card+ Host + SD Card + Heart
Module Off After Linux Boot
Channel 6 Activities LCD Activities Beat + OLED + LCD
Not Started
Activities
IVDD_MAIN @5V 60.5 µA 162 mA 207 mA 208 mA 244 mA 250 mA
Current Consumption IVDDBU @ 3.3V 13.8 µA 10.1 µA 10.1 µA 10.2v 10.1 µA 10.1 µA
IVDD_3V3 @ 3.3V 0 mA 1.21 mA 1.31 mA 1.48 mA 7.94mA 7.95mA
PVDD_MAIN @5V 302.5 µW 810 mW 1035 mW 1040 mW 1220 mW 1250 mW
Power Consumption PVDDBU @ 3.3V 45.54 µW 33.33 µW 33.33 µW 33.66 µW 33.33 µW 33.33 µW
PVDD_3V3 @ 3.3V 0 mW 3.993 mW 4.323 mW 4.884 mW 26.202 mW 26.325 mW
5.4.2.4 Current Consumption in Backup Modes
Scenario N°7 Scenario N°8 Scenario N°9 Scenario N°10 Scenario N°11
Scenario Setup Backup Mode Backup Mode w/ Self refresh ULP0 Mode ULP1 Mode Idle Mode
IVDD_MAIN @5V 58.9µA 82.6 mA 59.8 mA 58.4 mA 58.7 mA
Current Consumption IVDDBU @ 3.3V 13.6 µA 9.6 µA 13.7 µA 6.2 µA 6.3 µA
IVDD_3V3 @ 3.3V 578.9 µA 5.34 mA 870 µA 780 µA 800µA

Scenario N°7 Scenario N°8 Scenario N°9 Scenario N°10 Scenario N°11
Scenario Setup Backup Mode Backup Mode w/ Self refresh ULP0 Mode ULP1 Mode Idle Mode
PVDD_MAIN @5V 294.5 µW 413 mW 299 mW 292 mW 293.5 mW
Power Consumption PVDDBU @ 3.3V 44.88 µW 31.68 µW 45.21 µW 20.46 µW 20.79 µW
PVDD_3V3 @ 3.3V 1910 µW 17.62 µW 2871 µW 2574 µW 2640 µW
5.5 Radio Performance

For more details about radio performance, refer to the ATWILC3000-MR110xA data sheet.

Mechanical Characteristics
6. Mechanical Characteristics
6.1 Module Outline Drawings

Figure 6-1. ATSAMA5D27-WLSOM1 Module Drawing
PIN 1 CORNER S
188
186
180
187
183
177
182
181
184
179
178
174
171
158
143
142
185
164
161
152
176
175
173
172
170
167
149
146
145
144
166
165
163
162
160
159
155
154
153
148
147
169
168
157
156
151
150
1 141
2 140
3 139
4 138
5 137
6 136
7 RevB.0 - 0000027 135
8 134
9 1941000 133
10 132
11
ATSAMA5D27-WLSOM1 131
12 MICROCHIP 130
13 129
14 128
aaa
15 127
TOP VIEW
16 126
17 125
18 124
P1t
19 123
20 122
21 121
22 120
23 119
24 118
25 117
26 116
27 115
28 114
29 113
30 112
31 111
32 110
dA2
33 109
34 108
35 107
36 106
37 105
38 104
39 103
40 102
P2 nx
41 101
42 100
43 99
fff
44 98
45 97
46 96
47 95
A
72
69
91
48
51
54
52
53
60
70
71
49
50
57
66
67
68
78
84
92
58
59
63
75
64
65
76
77
81
90
93
55
56
82
83
86
89
61
62
73
74
87
88
79
80
85
94
dA1
E P2Eb
TP10
TP11
BOTTOM VIEW
e
aaa
TP9
P1b
D
TP3
TP6
TP2 TP1
TP4
GND
TP8 P2 fff x n
TP7
fff
SAMA5D27-WLSOM1 DIMENSIONS Drawn by : R C R

P2Ea jjj x m Pads : 188 SAMA5D27-WLSOM1_POD
jjj Tests Points Body : 40.8 x 40.8 x 3.287 B01
Origin in mm
11/15/2019
X
Y Pads Pitch : 0.8
Table 6-1. ATSAMA5D27-WLSOM1 Module Dimensions (in mm)
Common Dimensions
Symbol Comments
Min. Typ. Max.
X E 40.700 40.800 40.900
Body Size
Y D 40.700 40.800 40.900
Pad Pitch e – 0.800 –
PCB Thickness S 1.150 1.200 1.250
Total Thickness A – 3.287 3.387
Top Side P1t – 0.800 –
Pad Length (1)
Bottom Side P1b – 1.500 –
Pad Width (1) P2 – 0.600 – Solder Mask Defined 0.550
Pad Space (1) aaa – 0.200 –

Common Dimensions
Symbol Comments
Min. Typ. Max.
Opening Drill Diameter fff – 0.400 –
Pad Count n – 188 –
Test Point Diameter jjj – 1.000 –
Test Point Count m – 10 –
X P2Ea – 2.000 –
Pad Axis to Edge (1)
Y P2Eb – 2.000 –
X dA1 – 5.011 –
U.FL Antenna Axis to Edge
Y dA2 – 6.161 –
Notes:
1. Tolerances are defined upon:
– IPC A600 – Class2
– IPC 2615
2. Test points placed under module are for production purposes only. No connection on these points is allowed.
They are listed to avoid any contact with the main board vias or copper areas.
Table 6-2. Test Point Position Compared to Center Origin
Test Point Number X Y Voltage Point

TP1 -13.875 3.000 VDDUTMII
TP2 -15.900 3.825 VDD_3V3
TP3 -13.700 1.225 VDDOSC_PLL
TP4 -17.975 8.000 GND
TP6 -9.025 2.775 VDDIODDR
TP7 -9.500 16.825 VDDCORE
TP8 -4.850 15.550 VDDPLLA
TP9 -8.875 -1.025 VLDO1
TP10 10.825 -15.800 VDDA_3V3
TP11 4.350 -14.250 VBAT

6.2 Module Land Pattern (Host Board PCB Footprint)

Figure 6-2. ATSAMA5D27-WLSOM1 Land Pattern Drawing
LAND PATTERN RECOMMENDATIONS
PIN 1 CORNER
S1
1.6
1.6
10.75 9.75
W
k
10.9
S2
4.75
3.25 8.5
3.75
8.5
1 10
0.2
2.5
4
1
1.25
0.2
5 L
Inside <S1-S2> square, keepout area SAMA5D27-WLSOM1 DIMENSIONS Drawn by : R C R

No signals and power vias, no tracks are allowed. Pads : 188 SAMA5D27-WLSOM1_POD
Body : 40.8 x 40.8 x 3.287 B01
11/15/2019
Pads Pitch : 0.8
Table 6-3. ATSAMA5D27-WLSOM1 Land Pattern Dimensions (in mm)
Common Dimensions
Parameter Symbol Min. Typ. Max. Comments
Land Pattern Pad Width W – 0.600 – Solder Mask Defined 0.550
Land Pattern Pad Length L – 2.000 – –
Land Pattern Pad X Space S1 – 37.800 – –
Land Pattern Pad Y Space S2 – 37.800 – –
Land Pattern Pad Space k – 0.200 – –

Figure 6-3. GND Pads Overview and Layout Recommendation
WRONG GOOD
Note: It is recommended to use the layout as shown on the right above. This solution increases RF performance of
the Wi-Fi and Bluetooth communications and optimizes heat sink capability of the system; on the host board, do not
apply thermal brakes on the TOP layout around GND pads.
Note: A full GND plane with evenly distributed GND vias should be placed underneath the module, on the top layer
of the host board.
6.3 Other Characteristics

Table 6-4. ATSAMA5D27-WLSOM1 Other Characteristics
Measurement
Parameter Comments
Value Unit
Weight 7.91 g

Assembly and Storage Information
7. Assembly and Storage Information
7.1 Storage Condition
7.1.1 Moisture Barrier Bag Before Opening

A moisture barrier bag must be stored at a temperature of less than 30°C with humidity under 85% RH.
The calculated shelf life for the dry-packed product is 12 months from the date the bag is sealed.
7.1.2 Moisture Barrier Bag Open

Humidity indicator cards must be blue, RH < 30%.
7.2 Motherboard Solder Paste

The SnAgCu eutectic solder with melting temperature of 217°C is most commonly used for lead-free solder reflow
application. This alloy is widely accepted in the semiconductor industry due to its low cost, relatively low melting
temperature, and good thermal fatigue resistance. Some recommended pastes include NC-SMQ® 230 flux and
Indalloy® 241 solder paste made up of 95.5 Sn/3.8 Ag/0.7 Cu or SENJU N705-GRN3360-K2-V Type 3, or SENJU
M705-GRN360-K-V, no clean paste.
7.3 Motherboard Stencil Design

The recommended stencil is a laser-cut, stainless-steel type with thickness of 100 μm to 130 μm and an approximate
ratio of 1:1 for stencil opening to pad dimension. To improve paste release, a positive taper with bottom opening 25
μm larger than the top is utilized. Local manufacturers may find other combinations of stencil thickness and aperture
size to get good results.
7.4 Bake Information

The ATSAMA5D27-WLSOM1 module is rated MSL 3, indicating that storage and assembly processes must be
compliant with IPC/JEDEC J-STD-033C.
The ATSAMA5D27-WLSOM1 module has a total thickness of 3.287 mm (PCB and SMD mounted) and is comparable
to a die package. Thus baking instructions must comply with Table 4-1 of J-STD-033-C as a package body comprised
between 2.0 mm and 4.5 mm.
Refer to the highlighted information in the table below.

Figure 7-1. IPC/JEDEC Table
7.5 Reflow Profile

The ATSAMA5D27-WLSOM1 is assembled using standard lead-free reflow profile IPC/JEDEC J-STD-020E.
In addition to the initial assembly solder, we recommend a maximum of two additional soldering processes:
• the assembly on main board
• a spare heating pass in case the module must be removed from the main board for analysis
The ATSAMA5D27-WLSOM1 can be soldered to the host PCB by using the standard and lead-free solder reflow
profile. To avoid damage to the module, follow the JEDEC recommendations as well as those listed below:
• Do not exceed the peak temperature (Tp) of 245ºC.
• Refer to the solder paste data sheet for specific reflow profile recommendations.
• Use no-clean flux solder paste.
• Use only one flow. If the PCB requires multiple flows, mount the module at the time of the final flow.

Figure 7-2. Reflow Profile Example used for Soldering ATSAMA5D27-WLSOM1 Module on ATSAMA5D27-
WLSOM1-EK1 Board
-
Supplier Tp > Tc
User Tp < Tc-
Tc
Tc -5°C
Supplier tp User tp
Tp Tc -5°C
Max. Ramp Up Rate = 3°C/s
tp
Max. Ramp Down Rate = 6°C/s
Te m p e r a t u r e
TL
tL
Tsmax Preheat Area
Tsmin
ts
25
Time 25°C to Peak
Time
IPC-020e-5-1
Table 7-1. Reflow Profile Table Parameters
Profile Feature J-STD-020E Profile

Pre-heat Temperature Min Tsmin 150°C
Pre-heat Temperature Max Tsmax 200°C
Temperature Rise ts (from Tsmin to Tsmax) 60 to 120 seconds
Ramp-up Rate TL to Tp 3°C/sec. max.
Liquidous Temperature Time maintained above 217°C tL 60 to 150 seconds
Peak Temperature TP 245°C
Time (tP) within 5°C of the specified classification temperature (TC) tP 30 seconds
Ramp-down rate TP to TL 6°C/sec. max.
Time 25°C to peak temperature – 8 minutes max.

Regulatory Approval
8. Regulatory Approval
The ATSAMA5D27-WLSOM1 is the implementation of the ATWILC3000-MR110UA module in a particular host, in this
case the PCB of the ATSAMA5D27-WLSOM1.
The ATWILC3000-MR110UA module has received regulatory approval for the following countries:
• United States/FCC ID: 2ADHKWILC3000U
• Canada/ISED:
– IC: 20266-WILC3000UA
– HVIN: ATWILC3000-MR110UA
– PMN: ATWILC3000-MR110UA
• Europe/CE
8.1 United States

ATWILC3000-MR110UA module has received Federal Communications Commission (FCC) CFR47
Telecommunications, Part 15 Subpart C “Intentional Radiators” single-modular approval in accordance with Part
15.212 Modular Transmitter approval. Single-modular transmitter approval is defined as a complete RF transmission
sub-assembly, designed to be incorporated into another device, that must demonstrate compliance with FCC rules
and policies independent of any host. A transmitter with a modular grant can be installed in different end-use
products (referred to as a host, host product, or host device) by the grantee or other equipment manufacturer, then
the host product may not require additional testing or equipment authorization for the transmitter function provided by
that specific module or limited module device.
The user must comply with all of the instructions provided by the Grantee, which indicate installation and/or operating
conditions necessary for compliance.
A host product itself is required to comply with all other applicable FCC equipment authorization regulations,
requirements, and equipment functions that are not associated with the transmitter module portion. For example,
compliance must be demonstrated: to regulations for other transmitter components within a host product; to
requirements for unintentional radiators (Part 15 Subpart B), such as digital devices, computer peripherals, radio
receivers, etc.; and to additional authorization requirements for the non-transmitter functions on the transmitter
module (i.e., Suppliers Declaration of Conformity (SDoC) or certification) as appropriate (e.g., Bluetooth and Wi-Fi
transmitter modules may also contain digital logic functions).
8.1.1 Labeling and User Information Requirements

The ATWILC3000-MR110UA module has been labeled with its own FCC ID number, and if the FCC ID is not visible
when the module is installed inside another device, then the outside of the finished product into which the module is
installed must display a label referring to the enclosed module. This exterior label should use the following wording:
Contains Transmitter Module FCC ID: 2ADHKWILC3000U

or
Contains FCC ID: 2ADHKWILC3000U
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference, and (2) this device must accept any interference
received, including interference that may cause undesired operation.

Regulatory Approval
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part
15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a
residential installation. This equipment generates, uses and can radiate radio frequency energy, and if not installed
and used in accordance with the instructions, may cause harmful interference to radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment off and on, the user
is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna
• Increase the separation between the equipment and receiver
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
• Consult the dealer or an experienced radio/TV technician for help
Additional information on labeling and user information requirements for Part 15 devices can be found in KDB
Publication 784748, which is available at the FCC Office of Engineering and Technology (OET) Laboratory Division
Knowledge Database (KDB) https://apps.fcc.gov/oetcf/kdb/index.cfm
8.1.2 RF Exposure
All transmitters regulated by FCC must comply with RF exposure requirements. KDB 447498 General RF Exposure
Guidance provides guidance in determining whether proposed or existing transmitting facilities, operations or devices
comply with limits for human exposure to Radio Frequency (RF) fields adopted by the Federal Communications
Commission (FCC).
From the FCC Grant: Output power listed is conducted. This transmitter is restricted for use with the specific
antenna(s) tested in this application for Certification.
The antenna(s) used with this transmitter must be installed to provide a separation distance of at least 8.0 cm from
all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Users and
installers must be provided with antenna installation instructions and transmitter operating conditions for satisfying RF
exposure compliance.
8.1.3 Approved External Antennas

To maintain modular approval in the United States, only the antenna types that have been tested shall be used. It
is permissible to use different antenna, provided they are of the same antenna type, antenna gain (equal to or less
than), similar in band and out-of band characteristics (consult specification sheet for cutoff frequencies).
Testing of the ATWILC3000-MR110UA module was performed with the antenna types listed in the table List of
External Antennas.
8.1.4 Module Integration in the Host Product

Host products are to ensure continued compliance as per KDB 996369 Module Integration Guide.
8.2 Canada
The ATSAMA5D27-WLSOM1 module contains the ATWILC3000-MR110UA which has been certified for use in
Canada under Innovation, Science, and Economic Development (ISED, formerly Industry Canada) Radio Standards
Procedure (RSP) RSP-100, Radio Standards Specification (RSS) RSS-Gen and RSS-247. Modular approval permits
the installation of a module in a host device without the need to recertify the device.

Labeling Requirements (from RSP-100 - Issue 11, Section 3): The host product shall be properly labeled to identify
the module within the host device.
The Innovation, Science and Economic Development Canada certification label of a module shall be clearly visible
at all times when installed in the host device; otherwise, the host product must be labeled to display the Innovation,
Science and Economic Development Canada certification number of the module, preceded by the word “Contains” or
similar wording expressing the same meaning, as follows:
Contains IC: 20266-WILC3000UA

Regulatory Approval
User Manual Notice for License-Exempt Radio Apparatus (from Section 8.4 RSS-Gen, Issue 5, April 2018): User
manuals for license-exempt radio apparatus shall contain the following or equivalent notice in a conspicuous location
in the user manual or alternatively on the device or both:
This device contains license-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic
Development Canada’s license-exempt RSS(s). Operation is subject to the following two conditions:
1. This device may not cause interference;
2. This device must accept any interference, including interference that may cause undesired operation of the
device.
L’émetteur/récepteur exempt de licence contenu dans le présent appareil est conforme aux CNR d’Innovation,
Sciences et Développement économique Canada applicables aux appareils radio exempts de licence. L’exploitation
est autorisée aux deux conditions suivantes:
1. L’appareil ne doit pas produire de brouillage;
2. L’appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d’en
compromettre le fonctionnement.
Transmitter Antenna (From Section 6.8 RSS-GEN, Issue 5, April 2018): User manuals, for transmitters shall display
the following notice in a conspicuous location:
This radio transmitter [IC: 20266-WILC3000UA] has been approved by Innovation, Science and Economic
Development Canada to operate with the antenna types listed below, with the maximum permissible gain
indicated. Antenna types not included in this list that have a gain greater than the maximum gain indicated
for any type listed are strictly prohibited for use with this device.
Le présent émetteur radio [IC: 20266-WILC3000UA] a été approuvé par Innovation, Sciences et
Développement économique Canada pour fonctionner avec les types d'antenne énumérés cidessous et
ayant un gain admissible maximal. Les types d'antenne non inclus dans cette liste, et dont le gain est
supérieur au gain maximal indiqué pour tout type figurant sur la liste, sont strictement interdits pour
l'exploitation de l'émetteur.
Immediately following the above notice, the manufacturer shall provide a list of all antenna types which can be used
with the transmitter, indicating the maximum permissible antenna gain (in dBi) and the required impedance for each
antenna type.
Testing of the ATWILC3000-MR110UA module was performed with the antenna types listed in the table List of
External Antennas.
8.2.2 RF Exposure
All transmitters regulated by Innovation, Science and Economic Development Canada (ISED) must comply with RF
exposure requirements listed in RSS-102 - Radio Frequency (RF) Exposure Compliance of Radio communication
Apparatus (All Frequency Bands).
This transmitter is restricted for use with a specific antenna tested in this application for certification, and must not
be co-located or operating in conjunction with any other antenna or transmitters within a host device, except in
accordance with Canada multi-transmitter product procedures.
The installation of the transmitter must ensure compliance is demonstrated according to the ISED SAR procedures.
8.2.3 Helpful Web Sites

Innovation, Science and Economic Development Canada (ISED): http://www.ic.gc.ca/.
8.3 Europe
The ATSAMA5D27-WLSOM1 module is a Radio Equipment Directive (RED) assessed radio module that is CE
marked and has been manufactured and tested with the intention of being integrated into a final product.

Regulatory Approval
The ATSAMA5D27-WLSOM1 module has been tested to RED 2014/53/EU Essential Requirements for Health
and Safety (Article (3.1(a)), Electromagnetic Compatibility (EMC) (Article 3.1(b)), and Radio (Article 3.2) and are
summarized in European Compliance Testing.
The ETSI provides guidance on modular devices in “Guide to the application of harmonized standards
covering articles 3.1b and 3.2 of the Directive 2014/53/EU (RED) to multi-radio and combined radio and non-
radio equipment” document available for download from the following location: http://www.etsi.org/deliver/etsi_eg/
203300_203399/203367/01.01.01_60/eg_203367v010101p.pdf
To maintain conformance to the testing listed in European Compliance Testing, the module shall be installed in
accordance with the installation instructions in this datasheet and shall not be modified.
When integrating a radio module into a completed product the integrator becomes the manufacturer of the final
product and is therefore responsible for demonstrating compliance of the final product with the essential requirements
against the RED.

The label on the final product which contains the ATSAMA5D27-WLSOM1 module must follow CE marking
requirements.
8.3.2 Conformity Assessment

From ETSI Guidance Note EG 203367, section 6.1 Non-radio products are combined with a radio product:
If the manufacturer of the combined equipment installs the radio product in a host non-radio product in equivalent
assessment conditions (i.e. host equivalent to the one used for the assessment of the radio product) and according to
the installation instructions for the radio product, then no additional assessment of the combined equipment against
article 3.2 of the RED is required.
The European Compliance Testing listed in the table below was performed using the antennas listed in the table List
of External Antennas.
Table 8-1. European Compliance Testing
Certification Standards Article Laboratory Report Number Date
Safety EN 62368-1:2014, EN 62368-1:2014/A11:2017 50307896 001 22 Oct 2019
EN 300 328 V2.1.1/ 50141821 001(1) 06 Jun 2018
EN 62311:2008 3.1(a) 50141821 002 22 Oct 2019
Health
EN 300 328 V2.1.1/ 50141820 001(1)
06 Jun 2018
EN 62479:2010 50141801 001(1)
EN 301 489-1 V2.1.1
EN 301 489-1 V2.2.0
50126738 001(1) 06 Jun 2018
EN 301 489-17 V3.1.1 TÜV Rheinland,
EMC EN 301 489-17 V3.2.0 3.1(b) Taiwan
EN 55032:2012+AC:2013/
EN 55032:2015+AC:2016/ 50304514 001 22 Oct 2019
EN 55024:2010+A1:2015
50141821 001(1)
50141820 001(1) 06 Jun 2018
Radio EN 300 328 V2.1.1 3.2
50141801 001(1)
50141821 002 22 Oct 2019
Note:
1. Reports correspond to ATWILC3000-MR110UA.

Regulatory Approval
8.3.3 Simplified EU Declaration of Conformity

Hereby, Microchip Technology Inc. declares that the radio equipment type [ATSAMA5D27-WLSOM1] is in compliance
with Directive 2014/53/EU.
The full text of the EU declaration of conformity is available at the following internet address : https://
www.microchip.com/wwwproducts/en/ATSAMA5D27-WLSOM1
8.3.4 Helpful Web Sites

A document that can be used as a starting point in understanding the use of Short Range Devices (SRD) in Europe is
the European Radio Communications Committee (ERC) Recommendation 70-03 E, which can be downloaded from
the European Communications Committee (ECC) at: http://www.ecodocdb.dk/
Additional helpful web sites are:
• Radio Equipment Directive (2014/53/EU):
– https://ec.europa.eu/growth/single-market/european-standards/harmonised-standards/rtte_de
• European Conference of Postal and Telecommunications Administrations (CEPT):
– http://www.cept.org
• European Telecommunications Standards Institute (ETSI):
– http://www.etsi.org
• European Communications Committee (ECC):
– http://www.ecodocdb.dk
• The Radio Equipment Directive Compliance Association (REDCA):
– http://www.redca.eu/
8.4 Approved Antenna Types

ATWILC3000-MR110UA was tested and approved for use with the antennas listed in the table below.
Different antenna may be used, provided they are of the identical antenna type and antenna gain (equal to or less
than) and have similar in-band and out-of-band characteristics (consult specification sheet for cutoff frequencies).
If other antenna types are used, the OEM installer must authorize the antenna with respective regulatory agencies
and ensure its compliance.
Table 8-2. List of External Antennas(1)
ATWILC3000-
Antenna Gain @ 2.4 MR110UA
P/N Vendor Antenna Type Cable Length/ Remarks
GHz Band
FCC(2) (3) ISED CE
Pulse Electronics
W3525B039 2 dBi PCB X X 100 mm
Corporation
RFDPA870920IMLB301 WALSIN 1.84 dBi Dipole X X 200 mm
RFA-02-P33 Aristotle 2 dBi PCB X X 150 mm
SMA to u.FL cable length of
RN-SMA-S Microchip 0.56 dBi Dipole X X
100 mm (2) (3)
RFA-02-D3 Aristotle 2 dBi Dipole X X 150 mm
RFA-02-G03 Aristotle 2 dBi Metal Stamp X X 150 mm
RFA-02-L2H1 Aristotle 2 dBi Dipole X X 150 mm
RFA-02-P05 Aristotle 2 dBi PCB X X 150 mm
SMA to u.FL cable length of
RFA-02-C2M2 Aristotle 2 dBi Dipole X X
100 mm (2) (3)
86254 Delock 2 dBi PCB – X 50 mm

Regulatory Approval
Notes:
1. X = Covered under the certification.
2. If the end product using the module is designed to have an antenna port that is accessible to the end user,
then a unique (nonstandard) antenna connector (refer to FCC KDB 353028) must be used; for example,
Reverse Polarity - SMA.
3. If an RF coaxial cable is used between the module RF output and the enclosure, then a unique (nonstandard)
antenna connector must be used in the enclosure wall for interface with antenna.
8.4.1 Antenna Placement Recommendations

Particular attention must be given to the placement of the antenna and its cable. The following recommendations
must be applied:
• Ensure that the antenna cable is not expected to be routed over circuits generating electrical noise on the Host
board.
• Antenna should not be placed in direct contact or in close proximity of the plastic casing/objects.
• Do not enclose the antenna within a metal shield.
• Keep any components which may radiate noise, signals or harmonics within the 2.4 GHz to 2.5 GHz frequency
band away from the antenna and, if possible, shield those components. Any noise radiated from the host board
in this frequency band degrades the sensitivity of the module.
• It is highly recommended not to run the antenna cable alongside or underneath the module. It is preferred that
the cable is routed straight out of the module.
• The antenna should preferably be placed at a distance greater than 5 cm away from the module. The figure
below indicates the area where the antenna should not be placed.
This recommendation is based on an open air measurement and does not take into account by any metal shielding of
the customer end product. When a metal enclosure is used, the antenna can be located closer to the ATSAMA5D27-
WLSOM1 module.
The drawing below indicates how the antenna cable should be routed depending on the location of the antenna
with respect to the ATSAMA5D27-WLSOM1 PCB. Two possible options for the optimum routing of the cable are
described.
These guidelines are generic only; customers need to check and fine tune the antenna positioning in the final host
product.

Regulatory Approval
Figure 8-1. SAMA5D27-WLSOM1 Antenna Placement
5 cm
Preferred Antenna
Cable Routing
Directions
5 5
cm cm
MICROCHIP
ATSAMA5D27-WLSOM1
1941000
RevB.0 - 0000027
5 cm
Antenna Keep out Area

Ordering Information
9. Ordering Information
Table 9-1. Ordering Details
Ordering Code Package Description Regulatory Information

Certified Microchip MPU
Wireless module with
ATSAMA5D27-WLSOM1 40.8 x 40.8 x 3.287 mm FCC, ISED, CE
SAMA5D27, WILC3000 and
U.FL connector

Revision History
10. Revision History
10.1 Rev. C - 03/2021

Note: Microchip is in the process of implementing inclusive language in our documentation. During this update, you
may see the old terms and the new terms in our documentation text. We apologize for any confusion.
Throughout: Updated all secure element references to ATECC608B (was ATECC608A).

Updated 3.2 Pin List and PIOA, PIOB, PIOC and PIOD pin description tables.
Updated 4.1.4 Secure Element.
Updated figure in 4.2.1 Power Architecture.
Updated figure in 4.2.2.2 Power Configurations: Multiple Supplies.
Updated figure in 4.2.4 Baseboard Power Delivery Application Diagram Example.
PIO muxing tables moved from 4.6 External Interfaces to 3.2 Pin List.
Updated schematic and EMI example in 4.6.9 Interfacing with an LCD.
Added 5.4 Power Consumption.
Updated link to ATWILC3000 data sheet in 5.5 Radio Performance.
10.2 Rev. B - 12/2019

Updated Figure 3-1.
Updated pins 151, 152 in Pin Description: System.
Updated figure in 4.1.4 Secure Element.
Updated figure in 4.2.1 Power Architecture.
Updated 4.3.1 Ethernet Phy.
Modified component reference in 4.5 Radio Subsystem.
Updated 4.6.1 Interfacing with an SD Card.
Updated 4.6.2 Interfacing with e-MMC.
Updated 4.6.3 Interfacing with NAND Flash.
Updated 4.6.4 Interfacing with an Image Sensor Controller (ISC).
Updated 4.6.7 Interfacing with CLASS-D Audio Output.
Added 4.6.8 QTouch® Peripheral Touch Controller (PTC).
Added 4.6.9 Interfacing with an LCD.
Section 4.7 content moved to 8. Regulatory Approval.
Updated 5.5 Radio Performance.
Updated Figure 6-1.
Updated Figure 6-2.
Added new section 8. Regulatory Approval.
Updated Regulatory Information in 9. Ordering Information.

Revision History
10.3 Rev. A - 10/2019

First issue.

The Microchip Website

Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service

Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Embedded Solutions Engineer (ESE)
• Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support

Product Identification System

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
ATSAMA5 D27 - WLSOM1
Architecture
Product Group
Architecture: ATSAMA5 = Arm Cortex-A5 CPU

Product Group: D27-WLSOM1 Certified MPU Wireless module with
SAMA5D27, WILC3000 and U.FL
connector
Examples:
• ATSAMA5D27-WLSOM1 = System-On-Module (SOM) based on the SAMA5D27, with 2 Gb LPDDR2-SDRAM
running up to 500 MHz, and a Wi-Fi/BT Wireless module
Microchip Devices Code Protection Feature

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specifications contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is secure when used in the intended manner and under normal
conditions.
• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features
of the Microchip devices. We believe that these methods require using the Microchip products in a manner
outside the operating specifications contained in Microchip’s Data Sheets. Attempts to breach these code
protection features, most likely, cannot be accomplished without violating Microchip’s intellectual property rights.
• Microchip is willing to work with any customer who is concerned about the integrity of its code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code
protection does not mean that we are guaranteeing the product is “unbreakable.” Code protection is constantly
evolving. We at Microchip are committed to continuously improving the code protection features of our products.
Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act.
If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue
for relief under that Act.
Legal Notice
Information contained in this publication is provided for the sole purpose of designing with and using Microchip
products. Information regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR
CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW,
MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE

WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR
THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk,
and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or
expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,
MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip
Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer,
Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed
Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC,
ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra,
TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching,
BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge,
In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto,
maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad,
SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense,
VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
© 2021, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-7750-1
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,
DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,
TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Quality Management System

For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
2355 West Chandler Blvd. Tel: 61-2-9868-6733 Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
Chandler, AZ 85224-6199 China - Beijing India - New Delhi Fax: 43-7242-2244-393
Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen
Fax: 480-792-7277 China - Chengdu India - Pune Tel: 45-4485-5910
Technical Support: Tel: 86-28-8665-5511 Tel: 91-20-4121-0141 Fax: 45-4485-2829
www.microchip.com/support China - Chongqing Japan - Osaka Finland - Espoo
Web Address: Tel: 86-23-8980-9588 Tel: 81-6-6152-7160 Tel: 358-9-4520-820
www.microchip.com China - Dongguan Japan - Tokyo France - Paris
Atlanta Tel: 86-769-8702-9880 Tel: 81-3-6880- 3770 Tel: 33-1-69-53-63-20
Duluth, GA China - Guangzhou Korea - Daegu Fax: 33-1-69-30-90-79
Tel: 678-957-9614 Tel: 86-20-8755-8029 Tel: 82-53-744-4301 Germany - Garching
Fax: 678-957-1455 China - Hangzhou Korea - Seoul Tel: 49-8931-9700
Austin, TX Tel: 86-571-8792-8115 Tel: 82-2-554-7200 Germany - Haan
Tel: 512-257-3370 China - Hong Kong SAR Malaysia - Kuala Lumpur Tel: 49-2129-3766400
Boston Tel: 852-2943-5100 Tel: 60-3-7651-7906 Germany - Heilbronn
Westborough, MA China - Nanjing Malaysia - Penang Tel: 49-7131-72400
Tel: 774-760-0087 Tel: 86-25-8473-2460 Tel: 60-4-227-8870 Germany - Karlsruhe
Fax: 774-760-0088 China - Qingdao Philippines - Manila Tel: 49-721-625370
Chicago Tel: 86-532-8502-7355 Tel: 63-2-634-9065 Germany - Munich
Itasca, IL China - Shanghai Singapore Tel: 49-89-627-144-0
Tel: 630-285-0071 Tel: 86-21-3326-8000 Tel: 65-6334-8870 Fax: 49-89-627-144-44
Fax: 630-285-0075 China - Shenyang Taiwan - Hsin Chu Germany - Rosenheim
Dallas Tel: 86-24-2334-2829 Tel: 886-3-577-8366 Tel: 49-8031-354-560
Addison, TX China - Shenzhen Taiwan - Kaohsiung Israel - Ra’anana
Tel: 972-818-7423 Tel: 86-755-8864-2200 Tel: 886-7-213-7830 Tel: 972-9-744-7705
Fax: 972-818-2924 China - Suzhou Taiwan - Taipei Italy - Milan
Detroit Tel: 86-186-6233-1526 Tel: 886-2-2508-8600 Tel: 39-0331-742611
Novi, MI China - Wuhan Thailand - Bangkok Fax: 39-0331-466781
Tel: 248-848-4000 Tel: 86-27-5980-5300 Tel: 66-2-694-1351 Italy - Padova
Houston, TX China - Xian Vietnam - Ho Chi Minh Tel: 39-049-7625286
Tel: 281-894-5983 Tel: 86-29-8833-7252 Tel: 84-28-5448-2100 Netherlands - Drunen
Indianapolis China - Xiamen Tel: 31-416-690399
Noblesville, IN Tel: 86-592-2388138 Fax: 31-416-690340
Tel: 317-773-8323 China - Zhuhai Norway - Trondheim
Fax: 317-773-5453 Tel: 86-756-3210040 Tel: 47-72884388
Tel: 317-536-2380 Poland - Warsaw
Los Angeles Tel: 48-22-3325737
Mission Viejo, CA Romania - Bucharest
Tel: 949-462-9523 Tel: 40-21-407-87-50
Fax: 949-462-9608 Spain - Madrid
Tel: 951-273-7800 Tel: 34-91-708-08-90
Raleigh, NC Fax: 34-91-708-08-91
Tel: 919-844-7510 Sweden - Gothenberg
New York, NY Tel: 46-31-704-60-40
Tel: 631-435-6000 Sweden - Stockholm
San Jose, CA Tel: 46-8-5090-4654
Tel: 408-735-9110 UK - Wokingham
Tel: 408-436-4270 Tel: 44-118-921-5800
Canada - Toronto Fax: 44-118-921-5820
Tel: 905-695-1980
Fax: 905-695-2078

Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
ATSAMA5D27-WLSOM1

ATSAMA5D27 WLSOM1 Data Sheet ds60001590c-2256516

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ATSAMA5D27 WLSOM1 Data Sheet ds60001590c-2256516

Uploaded by

Copyright:

Available Formats

SAMA5D27 Wireless SOM1

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 1

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 2

7. Assembly and Storage Information....................................................................................................... 56

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 3

10. Revision History.................................................................................................................................... 67

The Microchip Website.................................................................................................................................69

Product Change Notification Service............................................................................................................69

Product Identification System.......................................................................................................................70

Microchip Devices Code Protection Feature................................................................................................ 70

Quality Management System....................................................................................................................... 71

Worldwide Sales and Service.......................................................................................................................72

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 4

Document Title Available

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 5

Mono PDMIC Interface

Power Supply Input

SMC 8-bit Interface

18-bit LCD Interface

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 6

3.1 Pinout Overview

3.2 Pin List

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 7

3.2.1 PIOA Pin Description

Primary Alternate PIO Peripheral Note

W11 VDDSDHC GPIO_EMMC PA0 I/O – – B QSPI0_SCK O 1 PIO, I, PU, ST

R9 VDDSDHC GPIO_EMMC PA1 I/O – – B QSPI0_CS O 1 PIO, I, PU, ST

W12 VDDSDHC GPIO_EMMC PA2 I/O – – B QSPI0_IO0 I/O 1 PIO, I, PU, ST

V11 VDDSDHC GPIO_EMMC PA3 I/O – – B QSPI0_IO1 I/O 1 PIO, I, PU, ST

W14 VDDSDHC GPIO_EMMC PA4 I/O – – B QSPI0_IO2 I/O 1 PIO, I, PU, ST

V10 VDDSDHC GPIO_EMMC PA5 I/O – – B QSPI0_IO3 I/O 1 PIO, I, PU, ST

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 8

T16 VDD_3V3 GPIO PA12 I/O – – B IRQ I 1 PIO, I, PU, ST

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 9

3.2.2 PIOB Pin Description

Reset State (Signal, Dir, PU, PD, HiZ,

Signal Dir Signal Dir Func Signal Dir IO Set

A9 VDD_3V3 GPIO PB1 I/O – – D PWML1 O 1 PIO, I, PU, ST Note (3)

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 10

Signal Dir Signal Dir Func Signal Dir IO Set

H5 VDD_3V3 GPIO PB27 I/O – – D PDMIC_CLK0 O 1 PIO, I, PU, ST Note (3)

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 11

Signal Dir Signal Dir Func Signal Dir IO Set

A2 VDD_3V3 GPIO PB30 I/O – – D TCLK5 I 2 PIO, I, PU, ST Note (3)

3.2.3 PIOC Pin Description

Primary Alternate PIO Peripheral Note

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 12

B2 VDDISC GPIO PC9 I/O – – C ISI_D0 I 1 PIO, I, PU, ST Note (2)

C2 VDDISC GPIO PC11 I/O – – D TCLK4 I 2 PIO, I, PU, ST Note (2)

D2 VDDISC GPIO PC12 I/O – – D URXD3 I 1 PIO, I, PU, ST Note (2)

K2 VDDISC GPIO PC13 I/O – – D UTXD3 O 1 PIO, I, PU, ST Note (2)

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 13

L7 VDDISC GPIO PC23 I/O – – C ISI_HSYNC I 1 PIO, I, PU, ST Note (2)

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 14

E1 VDDISC GPIO_CLK PC24 I/O – – C ISI_MCK O 1 PIO, I, PU, ST Note (2)

L4 VDDISC GPIO PC25 I/O – – C ISI_FIELD I 1 PIO, I, PU, ST Note (2)

D6 VDD_3V3 GPIO PC26 I/O – – D CANTX1 O 1 PIO, I, PU, ST Note (2)

C6 VDD_3V3 GPIO PC29 I/O – – B FLEXCOM4_IO1 I/O 1 PIO, I, PU, ST

D7 VDD_3V3 GPIO PC30 I/O – – B FLEXCOM4_IO2 I/O 1 PIO, I, PU, ST

© 2021 Microchip Technology Inc. Complete Datasheet DS60001590C-page 15

3.2.4 PIOD Pin Description

J7 VDD_3V3 GPIO_CLK PD0 I/O – – C UTXD3 O 2 PIO, I, PU, ST

D8 VDD_3V3 GPIO PD1 I/O – – D GRXCK I 2 PIO, I, PU, ST