Design of a Novel, High-Density, High-Speed 10 kV
SiC MOSFET Module
Christina DiMarino1, Mark Johnson2, Bassem Mouawad2, Jianfeng Li2, Dushan Boroyevich1, Rolando Burgos1,
Guo-Quan Lu1, Meiyu Wang1,
1Center for Power Electronics Systems
Virginia Tech
Blacksburg, VA, USA
dimaricm@vt.edu
Abstract— High-density packaging of fast-switching power
semiconductors typically requires low thermal resistance and
parasitic inductance. High-density packaging of high-voltage
semiconductors, such as 10 kV SiC MOSFETs, has the added
challenge of maintaining low electric field concentration in order
to prevent premature dielectric breakdown. This work proposes
a wire-bond-less, sandwich structure with embedded decoupling
capacitors and stacked ceramic substrates in order to realize a
high-density module capable of high-speed switching with low
electric field concentration and EMI. This is the first time that
these advanced packaging techniques have been applied to a 10
kV SiC MOSFET module.
Keywords—silicon carbide, packaging, high voltage, high
density, SiC MOSFET, power module
I. INTRODUCTION
For several decades, silicon (Si) has been the primary
semiconductor choice for power electronics applications [1].
However, Si is quickly approaching its limits in power
conversion [2],[3]. Silicon carbide (SiC) semiconductors have
demonstrated improved efficiency, reduced size and weight,
and lower system cost [4],[5],[2],[3],[6]. With these benefits,
SiC devices have begun appearing in commercial products [5],
and in public transportation systems [6]. However, even greater
strides can be made in medium- and high-voltage systems
through the utilization of •10 kV SiC devices. Currently, these
systems use Si insulated gate bipolar junction transistors
(IGBT), integrated gate-commutated thyristors (IGCT), or gate
turn-off thyristors (GTO). However, due to limited voltage
ratings (typically 6.5 kV or less), these devices must be
connected in series or multilevel converter topologies need to
be used [7]. The series connection of devices raises the issue of
voltage imbalance, and multilevel converters require additional
components and complex control [7]. Moreover, these Si
devices have low switching frequency capability, which places
constraints on their applications. The •10 kV SiC devices, on
the other hand, are able to switch at faster rates [8],[9], thereby
allowing for the improvement of existing medium-voltage
systems, as well as the realization of new technologies, such as
medium-voltage solid-state transformers.
Due to the vast possibilities for •10 kV SiC devices, a great
deal of resources have been devoted to their development. To
This work is funded in part by the UK Engineering and Physical Sciences
Research Council (EPSRC) through research grant [EP/K035304/1] and the
CPES High Density Integration Consortium.
978-1-5090-2998-3/17/$31.00 ©2017 IEEE
2Power Electronic, Machine and Control Group
University of Nottingham
Nottingham, UK
date, the majority of the reports on these devices have been
focused on the characterization [8],[9],[10] and gate drive
design [11],[12],[13]; however, the device package has a
significant impact on the performance. For instance, in [14],
the parasitic impedances for a package intended for 10 kV SiC
MOSFETs were extracted and put into a circuit simulator using
a 2 kV SiC MOSFET die model. The results showed notable
ringing in the switching waveforms due to the module parasitic
impedances [14]. Even more troublesome was the current
imbalance among the paralleled die during the switching
transients [14]. Due to the asymmetrical busbar design, each of
the paralleled die had a different parasitic loop inductance,
resulting in a maximum difference in the current overshoot of
150 % among the paralleled die [14]. This severe imbalance
will cause the die with the greater overshoot to have larger
switching losses, and thus a higher junction temperature,
ultimately reducing the lifetime of the module.
Consequently, the packaging of these unique devices
should be a top research priority. This is especially critical for
the adoption of these •10 kV SiC devices because, with an
optimal package, the advantages of replacing ”6.5 kV Si
devices are even greater, which helps to justify the higher cost.
Accordingly, Wolfspeed, a Cree company, has developed a
new half-bridge module for their 10 kV, 350 mȍ SiC
MOSFETs [15]. This package does not include antiparallel
diodes, and instead uses synchronous rectification with
eighteen 10 kV SiC MOSFET die in parallel per switch
position to achieve a total module current rating of 240 A [15].
Thus far, characterization has been shown for the module
populated with a single 10 kV, 350 mȍ SiC MOSFET die [15].
The module has a power-loop inductance of 16 nH, and a
power density of 4.2 W/mm3 [15]; though, to date, few details
have been published on the module design.
This work will present the detailed design of a novel, high-
power-density high-speed, synchronous, half-bridge power
module package for Wolfspeed’s 10 kV, 350 mȍ SiC
MOSFET [8]. Of course, there are several challenges
associated with creating a high-density package for high-speed,
10 kV devices. First, it is well known that high-power-density
packages have greater power dissipation densities and hence
require a more thoughtful thermal design. Additionally, when
operating in synchronous mode, the MOSFETs have higher
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average power dissipation, thus further emphasizing the need
for a package with low thermal resistance and a good thermal
management system. The challenges associated with high-
speed switching include sensitivity to parasitic inductances,
which can result in significant voltage overshoot, ringing, and
current imbalance among paralleled die [14]. Furthermore, the
high voltage rate of change (dv/dt) can result in common-mode
(CM) current flowing through the parasitic capacitance that
exists between the devices and the cooling system. If the
cooling system is grounded, then this current can flow through
the system ground, potentially coupling into the control and
logic circuitry, which could result in false signals.
There has been extensive research on high-power-density
packages. The metal post interconnect parallel plate (MPIPP)
module proposed in [16], achieves both low parasitic
inductance and high power density. Instead of using typical
wire bonds for the module interconnections, the MPIPP
module uses Cu posts that are directly attached to the
semiconductor die. The other side of the Cu posts connects to a
direct-bonded-copper (DBC) substrate. Gate drive components
can be mounted on the top DBC in order to achieve a higher
level of integration [16]. Although the MPIPP module was
demonstrated using a 1.2 kV Si IGBT and diode [16], the
structure is scalable to higher voltages. This is due to the Cu
posts, which provide electrical isolation between the top and
bottom substrates, as well as relax the electric field at the edge
of the semiconductor die [17]. Therefore, by increasing the
post height, higher voltage ratings can be achieved.
More recently, a hybrid half-bridge module was proposed
in [18]. In this module, copper/molybdenum/copper (CMC)
laminate is used for the posts instead of pure Cu. This was
done to increase the thermal cycling capability of the module
[19]. The improved reliability is attributed to the reduced
coefficient of thermal expansion (CTE) mismatch between the
posts and the die since molybdenum (Mo) has a CTE of 4.9,
which is closer to that of Si (2.6) and SiC (3.7) than Cu (17).
However, since solder and sintering metals do not adhere well
to Mo, a laminate that sandwiches the Mo between two Cu
sheets was used to achieve good adhesion. In [19], it was found
that a thinner Cu layer increases the module reliability. This is
due to the lower equivalent CTE of the CMC post.
While the modules presented in [16] and [18] have several
advantages over conventional packages, there are still several
areas for further research. In particular, these modules did not
demonstrate paralleling of multiple die. Paralleling SiC devices
is non-trivial because, as was mentioned earlier, their high-
speed switching makes them sensitive to stray inductances in
the package and surrounding circuitry. Hence, if the stray
inductances are asymmetrical among the paralleled die, then
current imbalance can occur during the transients [14]. This
work proposes a symmetric, scalable layout with embedded
decoupling capacitors. Further, in order to minimize the CM
current flowing through the system ground, this work proposes
to embed a CM screen within the power module that will divert
the current back to the dc bus.
Additionally, in order to develop a high-power-density
module for 10 kV devices, the electric field concentrations
within the module, and at the system interface, must be
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carefully analyzed. In particular, the highest electric field is
typically found at the interface between a conductor, a solid
dielectric, and a gas/liquid dielectric (or vacuum) [20]. This
interface is known as the triple point [20]. If the electric field at
the triple point exceeds the breakdown field strength of the
insulation, then partial discharge (PD) can occur. Repetitive
PD events can degrade the insulation, eventually resulting in
failure [21]. This work proposes to use stacked ceramic
substrates to help ease the electric field at the metal-ceramic-
encapsulation triple point. This report presents the first detailed
account of the design of a high-power-density, low-inductance,
low-EMI, low-PD, 10 kV, 54 A SiC MOSFET half-bridge
module with system integration solutions. This is the first time
that these advanced packaging techniques have been applied to
a 10 kV SiC MOSFET power module.
II. MODULE DESIGN
Fig. 1 shows the designed half-bridge power module, which
has three 10 kV, 350 mŸ, 8.1 mm × 8.1 mm die in parallel per
switch position for a total module current of 54 A. This value is
based on the preliminary datasheet for the 10 kV SiC MOSFET
die, which rates the continuous drain current at 18 A for a case
temperature of 90 °C, junction temperature of 175 °C, and
gate-source voltage of 20 V. The module has a planar structure,
using Mo posts and direct-bonded-aluminum (DBA) substrate
as the die interconnection instead of wire bonds. This type of
structure allows for increased power density, and reduces the
parasitic inductances and capacitances in the module, thereby
improving the transient performance. Furthermore, by
eliminating the wire bonds, the energy absorption capability
(e.g. during faults) of the module may be increased [22]. This
structure also allows decoupling capacitors to be embedded
within the module to further improve the dynamic performance
without increasing the module footprint. The total module
footprint is 35.2 mm × 74.3 mm × 11.4 mm without the
housing, but including the decoupling capacitors. This gives a
power density of 18.1 W/mm3. For reference, the power
density of Wolfspeed’s 10 kV, 240 A SiC MOSFET module is
4.2 W/mm3 [15], including the housing. The various aspects of
the module design will be discussed in more detail in the
following subsections.
(a) (b) (c)
(d) for the half-bridge module, (b) (e)
Fig. 1: (a) Schematic bottom stacked DBAs
with six 10 kV SiC MOSFET die and Mo posts, (c) module with the top DBA
stack and embedded decoupling capacitors attached, (d), side view of the
module with the vias shown, and (e) module with spring terminals.
A. Substrate Design
In this work, DBA substrates with 1-mm-thick aluminum
nitride (AlN) and 0.3-mm-thick aluminum (Al) are used. DBA
was selected because it has higher thermal-cycling capability
compared to direct-bonded copper (DBC) [23]. AlN was
chosen due to its high thermal conductivity, and because it is
available in 1-mm thickness, which provides high-voltage
isolation. The DBAs have vias (Fig. 1d), which form the low-
inductance electrical connections within the power module.
The AlN-DBA substrates used in this work were supplied by
DOWA.
In order to address the enhanced electric field and thermal
effects associated with a high-voltage, high-density design, the
DBA substrate must be carefully designed and evaluated. The
ceramic of the DBA typically has a dielectric strength around
20 kV/mm. At 10 kV, one would think that 1-mm-thick AlN
would provide sufficient margin such that the module could
operate reliably at this high voltage. However, the peak electric
field will in fact be much greater than the expected 10 kV/mm.
This is because the electric field will be highly concentrated at
the triple point, which is where the Al, AlN, and encapsulation
meet (Fig. 2) [24]. If this electric field exceeds the breakdown
field strength of the insulation materials (i.e. the AlN or
encapsulation), then PD can occur. Repetitive PD events can
ultimately result in insulation failure, thus destroying the
module [21].
By stacking two DBA substrates (one on top of the other),
the electric fields both within the bulk AlN and at the critical
triple points are notably reduced. This concept was
demonstrated in [25], which analyzed the electric field
distribution for a simple substrate structure with nearly
symmetrical top and bottom metal layers. However, in a
practical power module, the top and bottom metal layers are
not symmetrical; the top metal is patterned to create the circuit
(e.g. a half bridge). Further, the various traces in the top metal
pattern are at different potentials during the module operation.
Accordingly, due to the asymmetry and different potentials of
the top metal traces, if the middle metal layer of the DBA stack
is left floating, then it may not necessarily be at a potential that
will yield a meaningful reduction in the electric field.
This phenomenon is demonstrated by ANSYS Maxwell 2D
electrostatic simulations (Fig. 2). Fig. 2a and Fig. 2b show the
electric field distribution for the case when the top and bottom
metal layers are symmetrical. For this case, the peak electric
fields both within the bulk AlN and at the triple points are
reduced by 40 % when two DBA substrates are stacked
together (Fig. 2b) compared to when there is only a single
DBA substrate (Fig. 2a). This reduction is due to the potential
of the middle metal layer, which, due to the vertical symmetry
of the stacked substrate structure, floats to half of the voltage
applied across the top and bottom metal layers. For example,
when 10 kV is applied across the top and bottom metal layers,
then, due to the vertical symmetry, the middle metal layer will
float to 5 kV.
Fig. 2c and Fig. 2d show the electric field distribution for
the case when the top metal substrate is patterned and has
different potentials. It can be seen that, when the middle metal
layer is left floating, the peak electric field is not as notably
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Fig. 2: Electric field plots from 2D electrostatic ANSYS Maxwell simulations
for (a) a single DBA with vertical symmetry and a single potential on the top
and bottom Al layers, (b) two stacked DBAs with vertical symmetry and a
single potential on the top and bottom Al layers, (c) two stacked DBAs with
vertical asymmetry and two different potentials on the top Al layer with the
middle metal layer left floating, and (d) two stacked DBAs with vertical
asymmetry and two different potentials on the top Al layer with the middle
metal layer connected to half of the applied voltage (5 kV).
(a)
(b)
Fig. 3: Simulated temperatures (in degrees Celsius) for modules with (a) a
single DBA and (b) two stacked DBAs with a heat transfer coefficient of 7000
W/m2K, a power loss of 200 W per MOSFET.
reduced (Fig. 2c) compared to the case with the vertical
symmetry (Fig. 2b). This is because the asymmetry and
different potentials cause the middle metal layer to float to a
potential that is less than half of the applied voltage (2.4 kV for
this example). Accordingly, the reduction in the peak electric
field is not as prominent (27 %, compared to 40 %). However,
if the middle metal layer is electrically connected to half of the
applied voltage (Fig. 2d), then the electric field is again
reduced by 40 % compared to the single-substrate case (Fig.
2a).
Furthermore, the stacked DBA structure improves the heat
spreading in the module. This was verified with ANSYS
Workbench steady-state thermal simulations, where it was
found that stacking the DBAs reduces the peak junction
temperature by 9 °C for a heat transfer coefficient of 7000
W/m2K (applied to the bottom-most surface only), a power loss
of 200 W per MOSFET, and a conservative thermal
conductivity of 100 W/mK for the sintered silver (Ag) joints,
which are 100 μm thick between the stacked DBAs, and 50 μm
thick for the die and Mo attach layers (Fig. 3). Moreover, other
embodiments of the design presented in Fig. 1 can be
developed to incorporate top-side cooling. However, this may
complicate the termination and system interfacing design.
As mentioned earlier, the parasitic capacitance between the
SiC die and the cooling system is a path for CM current under
high-dv/dt switching. Specifically, the parasitic capacitance
between the output trace in the top Al layer (“Out”) and the
bottom Al layer (connected to the cooling system) are of
interest since the output node (i.e. the source of the top switch
and drain of the bottom switch) experiences high dv/dt as the
top and bottom switches in the half-bridge alternately conduct.
By stacking two DBAs, this capacitance is reduced by 22 %
since there are now effectively two parasitic capacitors in
series (Fig. 1a and Fig. 1d). For a single DBA, the parasitic
capacitance between the Out trace and the bottom Al layer is
45 pF (CP1). When two DBAs are stacked together, the
effective capacitance becomes 35 pF due to the series
connection of a 160-pF parasitic capacitor across the second
DBA substrate (CP2). These values, which were simulated
using ANSYS Q3D Extractor, are in good agreement with the
calculated capacitances. With this proposed design, the
parasitic capacitance to the cooling system is more than fifteen
times lower than that for the module evaluated in [14].
Additionally, it can be seen from Fig. 1d that when the
middle metal layer in the DBA stack is connected to the dc bus
midpoint (to reduce the peak electric field), then part of the
CM current that flows through CP1 will be diverted back to the
dc bus (i.e. the midpoint of the two series decoupling
capacitors) rather than going through CP2 to the cooling
system. This will hence reduce the amount of CM current that
flows through the system ground. The amount of CM current
that is diverted will depend on the high-frequency impedance
of the connection path between the middle metal layer and the
dc bus. Due to the embedded decoupling capacitors and usage
of Mo posts and vias in the DBA substrate, the parasitic
inductance of this loop is less than 2 nH allowing for a high
proportion of the CM current to be diverted back to the dc bus.
A similar screen was proposed in [26]; however, wire bonds
and connection lugs were used to make the connection to the
external dc bus, resulting in higher parasitic inductance and
hence a less-effective screen. Additionally, in [26], the middle
metal layer was connected to either the positive or negative dc
bus (rather than the midpoint), resulting in negligible electric
field reductions. So, the second insulating substrate was not
being fully utilized.
B. Embedded Decoupling Capacitors
Each MOSFET switch pair has its own set of decoupling
capacitors placed directly above it (Fig. 1c), providing a low-
impedance, high-frequency loop, which compensates for the
different distances to the terminals. This type of vertical
capacitor loop was reported in [27], which allowed for a
parasitic loop inductance of less than 1 nH. However, [27] did
not report on the utilization of these capacitors for improving
the current balance among paralleled die. This is a key
advantage of this structure, especially for high-current modules
with multiple die in parallel.
In [28], each phase-leg switch pair has its own embedded
decoupling capacitor. However, since the module in [28] uses
wire bonds for the interconnections, the capacitors must be
placed beside the die, thereby increasing the footprint of the
module. The vertical capacitor loop, on the other hand, does
not increase the module footprint/area. In fact, the planar
structure reduces the footprint of the module since no
additional area is needed for the wire bond landing pads.
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Since there are few high-voltage capacitors that are suitable
for embedding inside a power module, especially of such a
small size, a capacitor with 5 kV rating was selected, and thus
two must be connected in series. This means that, unlike in
[27] and [28], the dc bus midpoint potential is accessible within
the module. This allows for a low-impedance connection of the
middle metal layer in the bottom DBA stack to the dc bus
midpoint, which reduces the peak electric field at the Al-AlN-
encapsulation triple points and the CM current flowing through
the system ground.
The chosen capacitor is a surface-mount, 680-pF, C0G, 5
kV capacitor from AVX Corporation. This is the highest
capacitance value that could be found for the C0G material
with 5 kV voltage rating in a small, surface-mount package.
C0G was selected because its capacitance is stable with
temperature and voltage [29],[30]. While X7R capacitors
appear to have higher capacitance, under high-temperature and
high-voltage conditions, the capacitance can decrease by 50 %
or more [29],[30] to the point where it becomes comparable to
the capacitance of the C0G capacitors.
C. Die Arrangement
It has been shown in the literature that asymmetrical
parasitic elements among paralleled die can result in significant
current imbalance [11],[31]. In particular, during transients,
more current will flow to the die with the lower-impedance
paths due to unmatched power- and gate-loop inductances.
Those die will thus have higher losses, leading to greater
junction temperatures than the others [31]. As a result, these
die are likely to fail before their predicted lifetime, which
reduces the overall module reliability. To address this issue,
care was taken to ensure that the gate- and power-loop
inductances are symmetrical for each of the paralleled die.
For the gate loop, this is achieved by having individual gate
and source connections for each die. This requires that the gate
drive connects to each MOSFET. The gate drive component
placement and PCB traces can be adjusted to achieve
symmetrical impedances for optimal balancing. It should be
noted that this module design employs a Kelvin connection,
which separates the power source from the gate source. This
decoupling prevents the negative feedback between the two
loops, thereby increasing the switching speed [32]. According
to ANSYS Q3D Extractor, the gate-loop inductance for each
MOSFET die is 1.6 nH without the terminals.
For the power loop, embedded decoupling capacitors are
used to help balance the parasitic elements within the proposed
module, as well as to minimize the impact of the busbar stray
inductances on the device switching (i.e. the voltage overshoot
and ringing). Each MOSFET pair has its own set of decoupling
capacitors placed directly above it (Fig. 1c). This gives
symmetrical, low-impedance paths for each of the paralleled
MOSFET pairs. Further, the vertical power loop (awarded by
the planar structure) is perpendicular to the gate loop,
minimizing the coupling between them. With the decoupling
capacitors, the parasitic power-loop inductance decreases from
10.3 nH (including the terminals) to 4.4 nH. This is more than
eight times lower than the module reported in [14] and more
than three times lower than that in [15].
D. Molybdenum Posts
The Mo posts are needed as spacers to reduce the peak
electric field between the edge termination of the 10 kV
MOSFET die and the source potential on the upper DBA [17].
The optimal post height is a tradeoff between the
electromagnetic and electrostatic performances; a shorter post
height will reduce the parasitic inductances and resistances, but
will have a higher peak electric field. To determine the optimal
height of the Mo posts, 2D electrostatic simulations were
performed using ANSYS Maxwell. Fig. 4 shows the electric
field distributions in the module cross-section with Mo post
heights of 1 mm and 2 mm. In this simulation, the voltage field
was graded along the top surface of the 10 kV SiC MOSFET in
order to mimic the guard rings of the die. It can be seen from
Fig. 4 that the electric field between the top surface of the die
and the bottom surface of the top DBA reduces when the post
height is increased. If the electric field between the die and the
top DBA exceeds the breakdown field strength of the
encapsulation material, then PD and even arching could occur,
resulting in a short circuit between the drain and source
terminals of the SiC MOSFET. Accordingly, a post height of 2
mm was selected for this 10 kV SiC MOSFET module because
of the lower peak electric field.
As mentioned earlier, [18] uses CMC laminates for the
posts instead of pure Cu. It was found in [19] that CMC
laminate posts with thinner Cu layers had higher thermal
cycling capability. This is because the equivalent CTE of the
CMC post will be lower with thinner Cu layers. The thinnest
Cu layer used in [19] was approximately 60 μm. Accordingly,
this work proposes to eliminate the Cu layers entirely, and to
instead sputter 0.2 μm each of titanium (Ti) and Ag onto the
pure Mo posts in order to make them compatible with Ag
sintering. Thus the equivalent CTE of the Ti/Ag-coated Mo
posts will be even lower than that of the CMC laminate posts
evaluated in [19], potentially further improving the reliability.
Fig. 4: Simulated electric field distributions for 1-mm Mo post height (top) and
2-mm Mo post height (bottom). The node labels correspond to those with the
same name and color in Fig. 1a.
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TABLE I. MODULE PARAMETERS SIMULATED IN Q3D EXTRACTOR
Value Condition
Gate-loop 1.6 nH Without spring terminals.
inductance 3.8 nH With spring terminals.
Power-loop 10.3 nH With terminals, without decoupling capacitors.
inductance 4.4 nH With terminals, with decoupling capacitors.
CP1 45 pF Single DBA.
CP1//CP2 35 pF Two stacked DBAs.
Power density 18.1 W/mm3 With decoupling capacitors, without housing.
E. Terminal Design
Another challenge associated with the high-density design
of a 10 kV power module is the termination and system
interface. Commercial high-voltage connectors are
significantly larger than the module itself, and are thus not
viable options for this work. Consequently, alternative
solutions have been explored. Several terminal types were
considered: 1) busbar, 2) pins, and 3) springs. These designs
were evaluated based on the tradeoffs between peak electric
field, current-carrying capability, parasitic inductance, ease of
assembly, and reliability. Busbars are common in high-power
modules due to their high current-carrying capability and
lamination option, which offers lower inductance. However,
the sharp edges result in high electric field concentration. Pin
and spring connectors, on the other hand, have a rounded
geometry, resulting in lower electric field concentration. In
terms of mechanical reliability and ease of connecting and
disconnecting the module, spring connectors are preferred
compared to rigid pins. Multiple springs can also be placed in
parallel to reduce the parasitic inductance. Further, the springs
can be distributed throughout the module to maintain
impedance symmetry for the paralleled die. The scattered
terminals also create a more even pressure distribution
throughout the module, providing uniform contact to the
cooling system. For these reasons, springs were chosen for the
module terminals.
The springs selected for this module each have a current
rating of 10 A. The arrangement of the spring terminals is
shown in Fig. 1e. According to ANSYS Q3D Extractor, the
gate-loop inductance for each MOSFET die is 3.8 nH with the
spring terminals. This is more than five times lower than the
gate-loop inductance reported in [14]. For the power loop, the
total parasitic inductance is still 4.4 nH with the spring
terminals due to the embedded decoupling capacitors. Table I
summarizes the module parameters simulated using ANSYS
Q3D Extractor.
III. MODULE FABRICATION
Table II lists the materials used for the designed module.
The AlN-DBA substrates were plated with Ag by the
manufacturer (DOWA) to make them compatible with Ag
sintering. Ag sintering was chosen for the DBA-DBA, die, and
Mo post attach because it has been shown to have lower
voiding content, higher thermal conductivity, and improved
reliability compared to solder [33]. Furthermore, since the
melting temperature after sintering (960 °C) is lower than the
sintering temperature (” 260 °C), multiple sintering processes
can be done without affecting the previously-sintered joints.
TABLE II. PACKAGING MATERIALS AND PROCESSES SELECTED FOR THE
10 KV SIC MOSFET MODULE

Selected
Advantages Disadvantages
Material/Process
Two stacked High thermal conductivity,
Expensive and
Substrate 1-mm-thick voltage isolation, and
requires plating
AlN-DBAs reliability
Expensive and
Substrate Pressure-assisted Low voiding and high
complex
attach Ag sintering thermal conductivity
process (a) (b)
Low voiding, and high
Pressure-less temperature, thermal
Expensive
Ag sintering conductivity, reliability,
Die attach and shear strength
Low voiding, and high Expensive and
Pressure-assisted
temperature, thermal complex
Ag sintering
conductivity, and reliability process
Expensive and
Ti/Ag-coated
Interconnect Low inductance, low CTE complex
Mo posts
process (c) (d)
Rounded geometry, easy Fig. 5: 2D X-ray images of the Ag-sintered (a) DBA1-DBA2 and (b) DBA3-
connection, good DBA4 substrates, and (c) bottom and (d) top, angled view of the XCT scans of
Terminals Au-plated springs Expensive the DBA1-DBA2 sample. The dashed red boxes indicate the approximate
mechanical reliability, and
distributes pressure location of the 10 kV SiC MOSFET die.

scans, no large voids could be observed in the regions where

This is essential for this type of planar structure that requires
the DBAs, die, and Mo posts to be attached in stages. Although
the materials and processes used in this power module are
more expensive than traditional packaging technologies, they
allow for improved electrical and thermal performance and
reliability. Hence, costs could be saved at the system level. The
details of the fabrication of the various subcomponents of the
proposed module will be discussed in more detail in the
following subsections.
A. Substrate Attach
A pressure-assisted Ag-sintering process was developed for
bonding the 50.3 mm × 49.2 mm DBA1 and DBA2 substrates
and the 35.2 mm × 74.3 mm DBA3 and DBA4 substrates.
Approximately 100 μm of Ag paste was screen-printed onto
DBA2 for the DBA1-DBA2 bonding, and onto DBA3 for the
DBA3-DBA4 bonding. The printed paste was then dried in an
oven at 130 °C for 30 minutes. DBA1 was then placed on top
of the dried paste on DBA2, and DBA4 was placed on top of
the dried paste on DBA3. Each sample was sintered using a
hydraulic press at 250 °C for 10 minutes with 10 kN
(approximately 4.0 MPa and 3.8 MPa for DBA1-2 and DBA3-
4, respectively). PTFE was used to improve the pressure
uniformity over these large samples during sintering.
2D X-ray images of the bonded DBA1-DBA2 and DBA3-
DBA4 samples are shown in Fig. 5a and Fig. 5b, respectively.
From the X-ray images, some voids could be seen at the edges
of the DBA1-DBA2 bonded area. However, no large voids or
cracks could be observed in the inner region where the die will
be located (indicated by the dashed red boxes in Fig. 5a). It is
essential to have low voiding in this area so that the heat can be
effectively removed from the MOSFETs. Due to the need for a
low thermal resistance in the DBA1-DBA2 bonding layer
under the die, X-ray computer tomography (XCT) scans were
also performed on the sample (Fig. 5c and Fig. 5d). From these
the die will be placed (indicated by the dashed red boxes).
To obtain a better understanding of the bonding
characteristics of the bonded DBA1-DBA2 sample, thermal
impedance tests were performed at six locations along the
surface of the sample where the SiC die would be located.
Cumulative structure-function analysis was then used to find
the thermal resistance of the bond-line at each location. The
measured specific thermal resistances ranged from 6.93–7.56
mm2K/W, which are close to the low-end of the 4–100
mm2K/W range found in most thermal interface materials [34].
The 9 % variation of the measured thermal resistances
indicates good uniformity of the bond, and suggests that no big
voids or cracks exist in these locations. This conclusion is in
good agreement with the X-ray and XCT scan images (Fig. 5).
B. Bare Die Topside Metallization
Since the 10 kV SiC die come with Al topside metallization
(intended for wire bonding), Ti/Ag was sputtered on top of the
original Al pads such that the Mo posts could be sintered to the
devices. Moreover, the Mo posts for the gate connections are
1.0 mm × 1.0 mm, which is larger than the original MOSFET
gate pad. Consequently, two photolithography steps were used
to re-pattern the top surface of the MOSFET such that the gate
pad could be enlarged without being shorted to the source.
Prior to the metallization procedure, the die are characterized
using a Keysight B1505A curve tracer. Since the tests are done
in air, the voltage is limited to 2.5 kV. Beyond this value, the
high electric fields could breakdown the air, resulting in PD
and potentially arching. Next, the die surfaces are cleaned with
an oxygen plasma. Benzocyclobutene (BCB) is then spin-
coated onto the die. A first photoplot is then used to create the
openings in BCB such that the existing Al pads can be
contacted. After the BCB is exposed and developed, it goes
through a curing process. After curing, the film is descummed
with an O2-CF4 plasma in order to remove a thin polymer film
leftover from the develop process. A photoresist layer is then

4008

Fig. 6: 10 kV SiC MOSFET die after metallization process with enlarged gate
pad (right).
(a)
(b)
Fig. 7: (a) Reverse drain leakage currents at VGS= 0 V and 25 °C, and (b) on-
resistances at VGS= 18 V (dashed curve) and VGS= 20 V (solid curve) and 25 °C
before (red curves) and after (green curves) the die re-metallization. The die
used for testing the metallization procedure was a semi-functional 10 kV SiC
MOSFET die.
spin-coated onto the die. A second photoplot is then used to
create the new gate and source pad patterns. After the
photoresist is exposed and developed, it is again descummed
with another O2-CF4 plasma. The die is then sputtered with
approximately 0.1 μm of Ti and 0.2 μm Ag. Finally, the
photoresist is lifted off using acetone. Fig. 6 shows the newly-
metallized die. The static characteristics were repeated after the
die metallization process, and no changes in the reverse drain
leakage current (Fig. 7a) or on-state resistance (Fig. 7b) were
observed. While developing this re-metallization procedure,
only semi-functional 10 kV SiC MOSFET die were used.
Hence, the characteristics shown in Fig. 7a and Fig. 7b are for
semi-functional die. The fully-functional 10 kV die have lower
leakage current (Fig. 7a).
C. Molybdenum Post Attach
Mo was selected as the post material because it has a lower
CTE compared to Cu; however, solder and Ag (for sintering)
do not adhere well to Mo. Consequently, the Mo posts were
sputtered with approximately 0.1 μm of Ti followed by 0.2 μm
Ag to improve the bonding strength. Pressure-less sintering
with nano-Ag paste was used to attach the Ti/Ag-coated Mo
posts to the Ag-plated DBAs. Ag paste was stenciled onto the
4009
Ag-plated DBA with a thickness of 50 μm. The Ti/Ag-coated
Mo posts were then placed on top of the stenciled paste. The
sintering was performed at a ramp rate of 5 ÛC/min to 280 ÛC
and held for 30 minutes. Die shear tests were performed on
several samples, and bonding strengths between 31.3 MPa and
67.0 MPa (depending on the area of the Mo post) were
achieved. The Ti/Ag-coated Mo posts were also sintered to the
MOSFET die with the Ti/Ag topside metallization using the
same sintering process. Shear tests revealed bonding strengths
from 20.2 MPa for the large Mo posts (5.2 mm × 3 mm) to
48.3 MPa for the smaller Mo posts (1.0 mm × 1.0 mm).
D. Die Attach
As mentioned above, Ag sintering was chosen for the die
attach because it has been shown to have lower thermal
impedance and thermal cycling capability compared to solder
[33]. Both pressure-less and pressure-assisted Ag sintering
processes using nano-Ag paste were evaluated in this work.
An 8.1 mm × 8.1 mm 10 kV die was sintered without
pressure onto a Ag-plated DBA using Kyocera’s CT2700R7S
Ag paste at 230 °C for 90 minutes. The resulting die shear
strength was 18.4 MPa. It should be noted that these 10 kV SiC
MOSFET die have gold (Au) metallization on the bottom
surface. Since Ag diffuses faster than Au, a sintering profile
that limits the Ag diffusion is essential. If too much Ag
diffuses into the Au, then Kirkendall voids will form at the Ag-
Au interface, resulting in a bond with low shear strength [35].
Applying pressure during sintering can improve the shear
strength by creating a denser Ag layer [35]. However, pressure-
assisted sintering is more complex, especially when sintering
multiple die simultaneously since the pressure must be
uniformly applied to all of the die.
Nonetheless, pressure-assisted sintering was also evaluated
for the die attach. Ag paste was screen printed onto Ag-plated
DBA with a thickness 100 μm, and then dried in an oven at
130°C for 10 minutes. Once the paste was dried, a 10 kV die
was placed on top, and the sample was sintered at 250°C for 5
minutes with 10 MPa using a hydraulic press. The die shear
strength of the pressure-assisted Ag-sintered sample was 25.0
MPa.
IV. SUMMARY AND CONCLUSION
The design and optimization of a wire-bond-less, planar 10
kV SiC MOSFET module was presented. The proposed
module achieves a power density of 18.1 W/mm3 by taking
advantage of the superior reverse conduction characteristics of
the SiC MOSFET (i.e. not using external antiparallel diodes),
and by employing a planar structure using Mo posts and DBA
substrate for the interconnections instead of wire bonds. This
structure, along with the embedded decoupling capacitors,
yields gate- and power-loop parasitic inductances of just 1.6
nH and 4.4 nH, respectively. However, the high power density
increases the peak electric fields within the module. To remedy
this issue, two DBA substrates are stacked together and the
middle metal layer is connected to half of the dc bus voltage in
order to reduce the peak electric fields at the triple points. This
connection also decreases the CM current that flows through
the system ground.
 ACKNOWLEDGMENT
The authors acknowledge experimental assistance from
Zhenwen Yang, Shan Gao, Yue Xu, and Robert Skuriat. The
donation of substrates from DOWA and 10 kV SiC MOSFET
die from Wolfspeed, a Cree Company, and the financial
support from Rolls-Royce are greatly appreciated.
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