IEEE – VLSI LIST

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PROJECT ID TITLE
AB_VLSI_M2401 A GENERALIZED ALGORITHM AND RECONFIGURABLE
ARCHITECTURE FOR EFFICIENT AND SCALABLE
ORTHOGONAL APPROXIMATION OF DCT
AB_VLSI_M2402 DESIGN & ANALYSIS OF 16 BIT RISC PROCESSOR USING
LOW POWER PIPELINING
AB_VLSI_M2403 CONCEPT, DESIGN, AND IMPLEMENTATION OF
RECONFIGURABLE CORDIC
AB_VLSI_M2404 RECURSIVE APPROACH TO THE DESIGN OF A PARALLEL
SELF-TIMED ADDER
qAB_VLSI_M2405 DLAU A SCALABLE DEEP LEARNING ACCELERATOR UNIT
ON FPGA
AB_VLSI_M2406 A NOVEL HETEROGENEOUS APPROXIMATE MULTIPLIER
FOR LOW POWER AND HIGH PERFORMANCE
AB_VLSI_M2407 A NOVEL FIVE-INPUT MULTIPLE-FUNCTION QCA
THRESHOLD GATE
AB_VLSI_M2408 AN EFFICIENT VLSI ARCHITECTURE FOR REMOVAL OF
IMPULSE NOISE IN IMAGE USING EDGE PRESERVING
FILTER
AB_VLSI_M2409 HIGH-SPEED AND ENERGY-EFFICIENT CARRY SKIP ADDER
OPERATING UNDER A WIDE RANGE OF SUPPLY VOLTAGE
LEVELS
AB_VLSI_M2410 FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR
CORRECTION CODES
AB_VLSI_M2411 DELAY ANALYSIS FOR CURRENT MODE THRESHOLD
LOGIC GATE DESIGNS
AB_VLSI_M2412 INPUT-BASED DYNAMIC RECONFIGURATION OF
APPROXIMATE ARITHMETIC UNITS FOR VIDEO ENCODING
AB_VLSI_M2413 LOW-POWER PULSE-TRIGGERED FLIP-FLOP DESIGN
BASED ON A SIGNAL FEED-THROUGH SCHEME
AB_VLSI_M2414 MAES: MODIFIED ADVANCED ENCRYPTION STANDARD
FOR RESOURCE CONSTRAINT ENVIRONMENTS
AB_VLSI_M2415 A NOVEL VEDIC MATHEMATICS BASED ALU USING
SPECIFIC REVERSIBLE GATES
AB_VLSI_M2416 CHIP DESIGN FOR TURBO ENCODER MODULE FOR IN-
VEHICLE SYSTEM
AB_VLSI_M2417 A SYNERGETIC USE OF BLOOM FILTER FOR THE
EFFECTIVNESS OF ERROR CORRECTION
AB_VLSI_M2418 FAULT TOLERANT PARALLEL FFTS USING ERROR
CORRECTION CODES AND PARSEVAL CHECKS
AB_VLSI_M2419 DATA ENCODING TECHNIQUES FOR REDUCING ENERGY
CONSUMPTION IN NETWORK-ON-CHIP
AB_VLSI_M2420 DESIGN OF LOW POWER BARREL SHIFTER AND VEDIC
MULTIPLIER WITH KOGGE-STONE ADDER USING
REVERSIBLE LOGIC GATES
 IEEE – VLSI LIST
CONTACT @9640623444/8886866641
LANGUAGE: VERILOG/VHDL
VISIT: WWW.MYDIYPROJEKT.COM
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AB_VLSI_M2421 DUAL-QUALITY 42 COMPRESSORS FOR UTILIZING IN

DYNAMIC ACCURACY CONFIGURABLE MULTIPLIERS
AB_VLSI_M2422 FAST ENERGY EFFICIENT RADIX-16 SEQUENTIAL
MULTIPLIER
AB_VLSI_M2423 SCALABLE APPROACH FOR POWER DROOP REDUCTION
DURING SCAN-BASED LOGIC BIST
AB_VLSI_M2424 RELIABLE LOW-POWER MULTIPLIER DESIGN USING
FIXED-WIDTH REPLICA REDUNDANCY BLOCK
AB_VLSI_M2425 AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH
ADAPTIVE HOLD LOGIC
AB_VLSI_M2426 OVERLOADED CDMA CROSSBAR FOR NETWORK-ON-CHIP
AB_VLSI_M2427 DESIGN OF POWER AND AREA EFFICIENT APPROXIMATE
MULTIPLIERS
AB_VLSI_M2428 TEST COMPRESSION CAPABILITIES FOR PROGRAMMABLE
PRPG WITH LESS POWER AND AREA
AB_VLSI_M2429 ROBA MULTIPLIERA ROUNDING-BASED APPROXIMATE
MULTIPLIER FOR HIGH-SPEED YET ENERGY-EFFICIENT
DIGITAL SIGNAL PROCESSING
AB_VLSI_M2430 CLOCK-GATING OF STREAMING APPLICATIONS FOR
ENERGY EFFICIENT IMPLEMENTATIONS ON FPGAS
AB_VLSI_M2431 DESIGN OF EFFICIENT BCD ADDERS IN QUANTUM-DOT
CELLULAR AUTOMATA
AB_VLSI_M2432 DESIGN OF LOW-POWER HIGH-PERFORMANCE 2–4 AND 4–
16 MIXED-LOGIC LINE DECODERS
AB_VLSI_M2433 LOW POWER SEQUENTIAL SYSTEM USING MULTI BIT
FLIPFLOP WITH DATA DRIVEN CLOCK GATING