Unit 4 (Tutorials) - Combinational Logic Circuits (De-Multiplexer)

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DBV30023

DEMULTIPLEXER Q4. The 74HC154 decoder in Figure 2.4.4 used as Demultiplexer. Fill up the table
if data in (Din) and selector inputs applied to the demultiplexer.
Q1. The timing diagram below is applied to 1-to-4 demultiplexer. Sketch the
outputs line (D0, D1, D2, D3) waveform.

Figure 2.4.1

Q2. Below are waveform applied to 1-to-8 demultiplexer. Determine the output
level waveform for D0 – D7.

Figure 2.4.4

Selector Output
DIN
S3 S2 S1 S0 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
Figure 2.4.2 0 1 0 1 1
0 1 1 0 0
Q3. Sketch the outputs of 1-to-4 demultiplexer using waveform in Fifure 2.4.3. 0 1 1 1 1
[D0, D1, D2, D3] 1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

Figure 2.4.3

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