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    ALAN WALKER PIANO
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    This document defines two Verilog modules: a parallel-in parallel-out (PIPO) module and a parallel-in serial-out (PISO) shift register module. The PIPO module uses a register to store input data and outputs it simultaneously. The PISO module shifts input data into a register on the negative edge of shi and outputs the first bit of the register on the positive edge of clock, shifting the remaining bits. Testbenches are provided to simulate loading different values into the modules over multiple clock cycles.

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    This document defines two Verilog modules: a parallel-in parallel-out (PIPO) module and a parallel-in serial-out (PISO) shift register module. The PIPO module uses a register to store input data and outputs it simultaneously. The PISO module shifts input data into a register on the negative edge of shi and outputs the first bit of the register on the positive edge of clock, shifting the remaining bits. Testbenches are provided to simulate loading different values into the modules over multiple clock cycles.

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    12 views1 page

    Exp 11

    Uploaded by

    ALAN WALKER PIANO
    This document defines two Verilog modules: a parallel-in parallel-out (PIPO) module and a parallel-in serial-out (PISO) shift register module. The PIPO module uses a register to store input data and outputs it simultaneously. The PISO module shifts input data into a register on the negative edge of shi and outputs the first bit of the register on the positive edge of clock, shifting the remaining bits. Testbenches are provided to simulate loading different values into the modules over multiple clock cycles.

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    of 1

    module testpipo; module module PISO_Shi _Register

    reg shi =1'b0,clock=1'b0; pipo(clock,shi ,parallel_in,parallel_out); (shi ,clock,parallel_in,serial_out);


    reg [3:0]parallel_in; input clock,shi ; input shi ,clock;
    wire [3:0]parallel_out; input [3:0]parallel_in; input [3:0]parallel_in;
    pipo output reg [3:0]parallel_out; output reg serial_out;
    dut(clock,shi ,parallel_in,parallel_out); reg [3:0]d; reg [3:0]d;
    always begin always @ (negedge shi ) begin always @(negedge shi ) begin
    #1 shi =1'b1; d<=parallel_in; d<=parallel_in;
    #1 clock=1'b1; end end
    #3 shi =1'b0;clock=1'b0; always @(posedge clock) begin always @(posedge clock) begin
    end parallel_out<=d; serial_out<=d[0];
    ini al begin end d<={d[3],d[3:1]};
    parallel_in=4'b1011; endmodule end
    #5 parallel_in=4'b1101; endmodule
    module test_PISO_Shi _Register;

    #5 parallel_in=4'b1010;
    PISO_Shi _Register uut(shi ,

    #5 parallel_in=4'b0011;
    clock,parallel_in,serial_out);

    #6 parallel_in = 4'b1101;
    #6 parallel_in = 4'b0110;
    #6 parallel_in = 4'b1001;

    #5 parallel_in=4'b1000;
    #4 shi =1'b0;clock=1'b0;

    parallel_in = 4'b1010;

    #5 $finish;
    reg [3:0]parallel_in;

    end
    wire serial_out;
    reg clock=1'b0;

    endmodule
    reg shi =1'b1;

    #1 clock=1'b1;
    #1 shi =1'b1;
    always begin

    ini al begin
    end

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