Introduction to Digital VLSI

Lecture 10
Dr. Shaeen Kalathil
 Sequential Logic

In Combinational Out
Logic
circuit
Combinational logic
output depends on current inputs Memory
Sequential logic
Sequential
output depends on current and
The output is determined by
previous inputs •Current inputs
•Previous inputs

Output = f(In, Previous In)

• Latch: Level sensitive
• Ex: D latch, SR Latch
• Flip-flop: edge triggered
• master-slave flip-flop, D flip-flop, T flip-flop
Latches and flip-flops are the basic elements for storing information. One latch or
flip-flop can store one bit of information. The main difference between latches and
flip-flops is that for latches, their outputs are constantly affected by their inputs if
the enable signal is asserted. In other words, when they are enabled, their content
changes immediately when their inputs change.

Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock
signal. After the rising or falling edge of the clock, the flip-flop content remains
constant even if the input changes.

There are basically four main types of latches and flip-flops: SR, D, JK, and T. The
major differences in these flip-flop types are the number of inputs they have and
how they change state.
Latch vs Flipflop
SR Latch using NOR gates
If the set input (S) is equal to logic "1" and the reset input is equal to logic "0," then
the output node Q will be forced to logic " 1 " while the complementary output node
is forced to logic "0." This means that the SR latch will be set, regardless of its
previous state.

Similarly, if S is equal to "0" and R is equal to " 1" then the output node Q will be
forced to "0" while Q is forced to "1." Thus, with this input combination, the latch is
reset, regardless of its previously held state. Finally, consider the case in which both
inputs S and R are equal to logic " 1“, In this case, both output nodes will be forced
to logic "0," which conflicts with the complementarity of Q and Q. Therefore, this
input combination is not permitted during normal operation and is a not allowed
condition.
The circuit consists of two CMOS NOR2 gates. One of the input terminals
of each NOR gate is used to cross-couple to the output of the other NOR
gate, while the second input enables triggering of the circuit.
The operation of the CMOS SR latch circuit shown in Fig. 8.7 can be examined in
more detail by considering the operating modes of the four nMOS transistors, MI,
M2, M3, and M4. If the set input () is equal to VOH and the reset input (R) is equal to
VOL, both parallel-connected transistors MI and M2 will be on. Consequently, the
voltage on node Q will assume a logic-low level of VOL = 0.

At the same time, both M3 and M4 are turned off, which results in a logic-high
voltage VOH at node Q. If the reset input (R) is equal to VOH and the set input (S) is
equal to VOL, the situation will be reversed (Ml and M2 turned off and M3 and M4
turned on).

When both input voltages are equal to VOL' on the other hand, there are two
possibilities. Depending on the previous state of the SR latch, either M2 or M3 will
be on, while both trigger transistors MI and M4 are off. This will generate a logic-
low level of VOL = 0 at one of the output nodes, while the complementary output
node is at VOH.
SR Latch using NAND gates
Clocked SR Latch
The gate-level schematic of a clocked NOR-based SR latch is shown in Fig.
8.14. It can be seen that if the clock (CK) is equal to logic "0," the input
signals have no influence upon the circuit response. The outputs of the two
AND gates will remain at logic "0,“ which forces the SR latch to hold its
current state regardless of the S and R input signals.

When the clock input goes to logic " 1," the logic levels applied to the S and
R inputs are permitted to reach the SR latch, and possibly change its state.
Note that as in the non clocked SR latch, the input combination S = R = "1"
is not allowed in the clocked SR latch. With both inputs S and R at logic " 1,"
the occurrence of a clock pulse causes both outputs to go momentarily to
zero.
Transmission gate G1 ON
and G2 OFF
Transmission gate G1 OFF
and G2 ON
Review Questions
1. Give the logic diagram, truth table and static CMOS implementation of SR latch using NOR gates.
2. Give the logic diagram, truth table and static CMOS implementation of SR latch using NAND gates.
3. Give the logic diagram and static CMOS implementation of clocked SR latch using NAND gates.
4. Give the logic diagram and static CMOS implementation of clocked SR latch using NOR gates.
5. Explain the working of positive level sensitive D-Latch using transmission gate logic.
6. Give the circuit diagram of negative level sensitive D-Latch