Introduction to Digital VLSI

Lecture 9
Dr. Shaeen Kalathil
Implementation of logic gates using transmission gate logic
TG1 TG1

TG2 TG2
 WHEN INPUT B = ‘0’, TG1 IS BY OBSERVING THE TRUTH SO, WE CAN CONNECT INPUT ‘A’ SIMILARLY, WHEN INPUT B = ‘1’,
TURNED ON. CORRESPONDING TABLE, WE CAN SEE THAT TO INPUT OF TG1. TG2 IS TURNED ON. OUTPUT IS
INPUT IS CONNECTED TO OUTPUT IS EXACTLY EQUAL TO EQUAL TO ABAR. SO, ABAR IS
OUTPUT. INPUT A. CONNECTED TO INPUT OF TG2
Multiplexers
• 2:1 multiplexer chooses between two inputs
S
S D1 D0 Y
0 X 0 D0 0
0 X 1
Y
D1 1
1 0 X
1 1 X
Multiplexers
• 2:1 multiplexer chooses between two inputs
S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1
Transmission Gate Mux
• multiplexer uses two transmission gates
• Only 4 transistors
S

D0
S Y
D1

Slide 12