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Process Optimization for CCGA Surface Mount Assembly Based on Physics of

Failure

Conference Paper · September 2021

DOI: 10.1109/ICEPT52650.2021.9568045

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 Process Optimization for CCGA Surface Mount
Assembly Based on Physics of Failure
Hui Xiao * Weiming Li Yabing Zou
China Electronic Product Reliability China Electronic Product Reliability China Electronic Product Reliability
and Environmental Testing Research and Environmental Testing Research and Environmental Testing Research
Institute Institute Institute
Guangzhou, China Guangzhou, China Guangzhou, China
xiaohui_ceprei@163.com liwm@ceprei.com zouybing@163.com

Xiaotong Guo Jiahao Liu

China Electronic Product Reliability China Electronic Product Reliability
and Environmental Testing Research and Environmental Testing Research
Institute Institute
Guangzhou, China Guangzhou, China
guoxiaotong0713@163.com ljh071408@163.com

Abstract—There is still limited second-level interconnect would often induce the failure of whole system or even
reliability for large-size ceramic column grid array (CCGA) severe problem, because such package is usually used as the
devices. In this paper, the process optimization technology core component, such as CPU, FPGA, DDR, and so on. As
based on physics of failure (PoF) was proposed and applied in surface mount technology is the key process of the
the CCGA surface mount assembly, considering the structure interconnection formation between the CCGA component
characteristics of the package and coupled process and the printed circuit board (PCB), it is necessary and
environment. This methodology is problem-oriented, focusing important to study such process optimization technology, and
on the internal physical and chemical process related to the more attention should be paid to the structure characteristics
failure of components and materials. The failure mechanism
of the package and coupled process environment [4].
study is conducted for typical failure modes, by which the
sensitive process parameters about failure can be obtained.
Then the corresponding process optimization tests are
conducted, ensuring the board-level products meet the
electronic interconnect requirements in service. The results
showed that the process optimization methodology based on
PoF was a useful and efficient tool for solving the interconnect
defects of CCGA surface mount assembly.

Keywords—CCGA surface mount assembly, process

optimization, physics of failure

I. INTRODUCTION
Ceramic column grid array (CCGA) is a kind of
high-density surface mount package, which can be connected
to the printed circuit board (PCB) by solder balls as the I/O
circuit ends. Because the ceramic substrate can offer the
advantages of finer routing density, multiple power and
ground planes, improving signal integrity, moisture resistance
and thermal conductivity, CCGA packaging has been
gradually used in aviation equipment and other high reliability
field in recent years [1].
Fig. 1 shows the two typical structures of CCGA solder
columns. The most commonly used solder column is
Pb90Sn10 solder column, as shown in Fig. 1a. Another one
is Pb80Sn20 solder column with a copper spiral on the
surface, as shown in Fig. 1b, which could ease the column
deformation during thermal cycling [2]. The solder columns
are usually attached to ceramic substrate with 63Sn37Pb
solder. Compared with the ceramic quad flat package (CQFP)
or ceramic ball grid array (CBGA) package, the CCGA
package with higher standoff is believed to have a much
higher reliability under thermal cycling.
However, the CCGA package exhibits poor solder joint
reliability when compared to organic packaging technologies,
there is still limited second-level interconnect reliability for
large-size CCGAs [3]. Solder joints’ interconnect failure
Fig. 1 Typical structure of solder columns [2]
As to the process optimization for electronic assembly,
the traditional method, such as taguchi method, is based on a
large number of process tests and systematically
mathematical statistics analysis [5, 6]. However, for the kind
of high-reliability and core component product, the
traditional reliability technology is not suitable because of
high test cost and long test time [7]. In this paper, the process
optimization technology based on physics of failure (PoF)
was proposed and applied in the surface mount assembly,
considering the structure characteristics of the package and
coupled process environment. This methodology is
problem-oriented, focusing on the internal physical and
chemical process related to the failure of components and
materials. The failure mechanism study is conducted for
typical modes, by which the sensitive process parameters
about failure can be obtained. Then the corresponding
process optimization tests are conducted, ensuring the
board-level products meet the electronic interconnect
requirements in service.

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 II. PROCESS OPTIMIZATION METHODOLOGY BASED ON modes: plenty of voids in the column solder joints, a large
POF number of solder columns deviated from the corresponding
pads’ perimeter, interconnect failure during vibration
The PoF-based process optimization methodology is as
reliability test.
shown in Fig. 1. It was conducted by theoretical research
combining with experimental verification. Firstly, the mainly
problem was identified by product information investigation,
including process site survey and historical failure
investigation. Secondly, Failure analysis was conducted to
identify the failure mechanism of the corresponding typical
failure modes. Then process optimization was conducted
according to the specific modes and mechanism. Finally,
optimization result can be verified by reliability evaluation
tests.
In general, this methodology mainly contains five steps,
Solder joint voids
including product information investigation, failure modes
and failure mechanism research, the root cause determination,
corresponding process optimization, and result verification.

Fig. 3 Voids in the column solder joints

(a) 3D X-ray inspection

Fig. 2. The technical framework of the PoF-based process optimization (b) Optical microscope observation
methodology
Fig. 4 Solder columns deviated from the pads under the views of
III. APPLICATION OF THE POF-BASED PROCESS OPTIMIZATION Optical microscope and 3D X-ray inspection
FOR THE CCGA SURFACE MOUNT ASSEMBLY

A. Samples and Background

The CCGA601 package was used in the present study,
the package size of which was 40mm * 40mm. The solder
column was 90Pb10Sn, and the dimension was ф0.51mm
and 2.2mm high. The pad diameter of the substrate was
0.75mm and the pitch was 1.27mm. The paste used in the Crack
board-level soldering was Loctite CR32Sn63AGS89.5. The
solder columns were attached to the PCB substrate with the
solder paste by reflow soldering. Fig. 5 Cracking in the columns during vibration reliability test
B. Failure Analysis Investigation C. Root cause analysis
Fig. 3 to Fig. 5 shows the failure phenomenon of the Failure mechanism study was conducted to address above
CCGA board-level connection before the process three types of failure modes, as shown in Fig. 3 to Fig. 5.
optimization study. There were mainly three types of defect

2021 22nd International Conference on Electronic Packaging Technology (ICEPT)

 (1) Solder joint voids There were vias and traces buried within the package for the
electrical connection of the neighboring solder joints. Fig. 6b
Solder joint voids were related to flux volatilization depicts the pathway of the current flow across the entire
during reflow soldering of CCGA surface mount assembly assembly.
[8]. The rate of voids could be controlled by reflow
temperature profile optimization, such as pre-heat
temperature, soldering temperature and soldering time.
(2) Solder columns deviation
Compared with CBGA package, self-centering of the
solder column array was poorer than the solder ball array,
during the reflow soldering stage of the surface mount
assembly. In order to ease the solder columns deviation,
there were two types of solution. One solution was the solder
columns coplanarity control for the solder columns of the
CCGA package, which was related to the incoming
inspection. Another one was process optimization for solder
paste printing and the CCGA package patch.
(3) Poor variation resistance
(a) Overview
Variation resistance was mainly related to CCGA
package’s structure, especially related to the structure
frangibility of the ceramic package with the long solder
column array. The solution could be made to promote the
deformation resistance for the structure. Corner reinforcing
with glue for the CCGA package may be an effective (b) Current flow path
solution.
Fig. 6 Schematic Diagram of Daisy-chain Circuit Design of the
D. Corresponding process optimization connection between the CCGA601 package and the substrate
According to the root cause analysis results, process (1) Reflow profile optimization
optimization for the CCGA surface mount assembly was
conducted. Fig. 7 shows reflow profile optimization for the CCGA surface
mount assembly. Compared with CCGA1, the CCGA2 soldering
A daisy-chain circuit is designed for the CCGA601 temperature was higher and soldering time was longer, which could
package assembly, which could be used to conduct process help the flux volatilization bubbles escape from the solder during
optimization test as well as optimization effect verification. the reflow soldering. Reflow profile optimization could be used to
reduce void rate of the CCGA solder joints.
Fig. 6 depicts schematically the daisy-chain circuit design.

(a) Before process optimization (marked as CCGA1) (a) After process optimization (marked as CCGA2)
Fig. 7 Reflow profile optimization for the CCGA surface mount assembly
(2) Process optimization for solder paste printing and the
CCGA package patch
Reinforcing glue
Process optimization for solder paste printing was aimed
to control the solder paste volume in a suitable range, which
would affect the centering of the solder columns during CCGA
soldering stage. It contained two aspects, steel mesh opening
size and solder paste printing parameters. The related
parameter of the CCGA package patch was patch pressure,
which would work with the weight of the CCGA package
and affect the solder columns’ centering.
(3) Corner reinforcing with glue for the CCGA package
Zymet2605 glue was used for corner reinforcing of the Fig. 8 Corner reinforcing with glue for the CCGA package
CCGA package. The dispensing process optimization was E. Optimization effect verification
conducted according to IPC-7095C standard [8].
Process optimization was conducted to solve the
soldering voids, columns’ deviation and board-level
interconnect reliability. A serial of experimental analysis
technologies and reliability qualification tests were used to

2021 22nd International Conference on Electronic Packaging Technology (ICEPT)

verify the optimization effect, such as X-ray inspection,
microsectioning, scanning electron microscope (SEM)
analysis, temperature cycling test and variation test.
The comparison results of solder joints’ morphology
before and after process optimization were as shown in Fig. 4.
Fig. 5 shows the microstructure and elements’ distribution in
the CCGA solder joint. It can be seen that there was not any
obvious abnormality for the soldered interfacial zone
microstructure.
(a) Before process optimization (b) After process optimization
Fig. 9 Comparison results of solder joints’ morphology before and
after process optimization
(a) Microstructure (b) Elements’ distribution
Fig. 10 Microstructure and elements’ distribution in the CCGA
solder joint after process optimization
The solder columns were well aligned and the voids’s
rate of the solder joints was much less than 25%. It was
suggested that the CCGA solder joint quality met the
requirements of IPC-610G and ECSS-Q-ST-70-38C [9, 10].
Moreover, there was not any solder joint failure occurred
during thermal cycling and variation reliability qualification
tests. This suggested that PoF was a useful and efficient tool
for solving the interconnect defects of CCGA surface mount
assembly.
IV. CONCLUSIONS
Process optimization was conducted to solve the
soldering voids, columns’ deviation and board-level
2021 22nd International Conference on Electronic Packaging Technology (ICEPT)
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interconnect reliability. These defects were mainly related to
soldering process, solder paste printing process, and the die
attach process. Based on PoF analysis, the key sensitive
parameters could be determined, which were die attach
pressure, steel mesh opening size, soldering temperature and
soldering time. Corresponding process optimization and
Corner reinforcing with glue for the CCGA package were
conducted, the results showed that the solder joint quality
met the requirements of IPC-610G and ECSS-Q-ST-70-38C.
And there was not any vibration failure occurred in the
solder joints. This suggested that PoF was a useful and
efficient tool for solving the interconnect defects of CCGA
surface mount assembly.
ACKNOWLEDGMENT
This work is financially supported by by the National
Key R&D Program of China under Grant No.
2020YFB1710300, the Science and Technology Program of
Guangzhou, China under Grant No. 202002030357, CEPREI
Innovation and Development Fund No. 20Z32, which were
acknowledged.
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