UNIVERSITY OF ENGINEERING AND

TECHNOLOGY, TAXILA

Lab Report 10
Digital Logic Design Lab
Name: Alina Gulzar

Reg No.: 21-CP-06

Section: Omega

Department: Computer Engineering

Due Date: 15th August 2022

EXPERIMENT #10
INTRODUCTION TO VERILOG HDL
Objective:
To understand and write basic Verilog code for simple design modules.
Apparatus List:

• Icarus Verilog installed on PC

LAB Tasks:
1. Write Verilog Code for Even Parity Generator for 3-bit Message and simulate it on Icarus
Verilog
2. Write Verilog Code for Odd Parity Generator for 3-bit Message and simulate it on Icarus
Verilog
3. Write Verilog Code for Half Adder and simulate it on Icarus Verilog
4. Write Verilog Code for 1-bit Full Adder simulate it on Icarus Verilog

Design Methodology:
• First of all, we have to create a folder so that all the related files are in the same folder.
• Open Notepad, and write the Verilog code, save that notepad file in [module_name.v]
extension. The name of file and name of module must be same. As Verilog HDL is the case
sensitive Language so, a smallest mistake will cause an error.
• Again open notepad and write a test bench for the code file and save this file as syntax:
[module_nametb.v].
• Now, copy both files and open Local Disk: C → iverilog → bin → Paste the files.
• Click on the address bar.

• Write cmd in the bar and press enter key.

• A new interphase is opened…

• Now we have to write the commands, write → iverilog → -o → design name → test
bench file name (tb.v) → verilog code file name (.v) → Press Enter key.
• If there is no error present in the file, then write → vvp → design name → Press enter key.
• Now the vcd file is ready for the output.
• Copy the vcd file, and open Local Disk: C → iverilog → gtkwave → Paste the files.
• Click on the address bar.

• Write cmd in the address bar.

• Write → gtkwave → design name → Press Enter.

• The see the output on the gtkwave analyser.
TRUTH-TABLES:
1. Even Parity Generator
 2. Odd Parity Generator

3. Half Adder

Input Output

A B Sum Carry
0 0 0 0

0 1 1 0
1 0 1 0

1 1 0 1

4. 1-Bit Full Adder

CODES:
1. Even Parity Generator
Verilog Code:
module evenparity (Y, A,B,C);
output Y;
input A, B, C;
wire w1,w2;
xor x1(w1w2,A,B);
xor x2(y,w1w2,C);
endmodule

Test Bench:
module evenparity_tb ();
reg x,y,z;
wire S;
evenparity DUT(S,x,y,z);
initial
begin
x=1'b0; y=1'b0; z=1'b0;
#10 x=1'b0; y=1'b0; z=1'b1;
#10 x=1'b0; y=1'b1; z=1'b0;
#10 x=1'b0; y=1'b1; z=1'b1;
#10 x=1'b1; y=1'b0; z=1'b0;
#10 x=1'b1; y=1'b0; z=1'b1;
#10 x=1'b1; y=1'b1; z=1'b0;
#10 x=1'b1; y=1'b1; z=1'b1;
end

initial
begin
$dumpfile("evenparitytb.vcd");
$dumpvars(0, evenparitytb);
end
endmodule
Simulation:
 2. Odd Parity Generator
Verilog Code:
module oddparity(W, X, Y, Z);

input X, Y,Z ;
output O;
wire w1;

xor x1(w1, X, Y);

xnor x2(O, w1, Z);

endmodule
Test Bench:
module oddparitytb();
reg X, Y, Z;
wire O;
oddparity(O, X, Y, Z);
initial
begin
X=1'b0; Y=1'b0; Z=1'b0;
#10 X=1'b0; Y=1'b0; Z=1'b1;
#10 X=1'b0; Y=1'b1; Z=1'b0;
#10 X=1'b0; Y=1'b1; Z=1'b1;
#10 X=1'b1; Y=1'b0; Z=1'b0;
#10 X=1'b1; Y=1'b0; Z=1'b1;
#10 X=1'b1; Y=1'b1; Z=1'b0;
#10 X=1'b1; Y=1'b1; Z=1'b1;
end
initial
begin
$dumpfile ("oddparitytb.vcd");
$dumpvars (0, oddparitytb);
end
endmodule

Simulation:
 3. Half Adder
Verilog Code:
module halfadder (S, C, A, B);
input A, B;
output S, C;
xor x1(S, A, B);
and a1(C, A, B);
endmodule

Test Bench:
module halfaddertb ( );
reg X, Y;
wire Sum, Carry;
halfadder DUT (Sum , Carry, X, Y);
initial
begin
X=1'b0; Y=1'b0;
#10 X=1'b0; Y=1'b1;
#10 X=1'b1; Y=1'b0;
#10 X=1'b1; Y=1'b1;
end
initial
begin
$dumpfile ("halfadddertb.vcd");
$dumpvars (0, halfaddertb);
end
endmodule

Simulation:
 4. 1-bit Full Adder
Verilog Code:
module fulladder (Sum, Carry, A, B, Cin);
input A, B, Cin;
output Sum, Carry;
wire w1, w2, w3;
halfadder HA1(.A(A), .B(B), .Sum(w1), .Carry(w2));
halfadder HA2(.A(w1), .B(Cin), .Sum(S), .Carry(w3));

or o(Carry, w2, w3 );
endmodule
module halfadder (Sum, Carry, A, B);
input A, B;
output Sum, Carry;
xor x1(Sum, A, B);
and a1(Carry, A, B);
endmodule

Test Bench:
module fulladdertb ( );
wire Sum, Carry;
reg A, B, Cin;
fulladder DUT(.Sum(Sum) , .Carry(Carry), .A(A), .B(B), .Cin(Cin));
initial
begin
A=1'b0; B=1'b0; Cin=1'b0;
#10 A=1'b0; B=1'b0; Cin=1'b1;
#10 A=1'b0; B=1'b1; Cin=1'b0;
#10 A=1'b0; B=1'b1; Cin=1'b1;
#10 A=1'b1; B=1'b0; Cin=1'b0;
#10 A=1'b1; B=1'b0; Cin=1'b1;
#10 A=1'b1; B=1'b1; Cin=1'b0;
#10 A=1'b1; B=1'b1; Cin=1'b1;
end
initial
begin
$dumpfile ("fulladddertb.vcd");
$dumpvars (0, fulladdertb);
end
endmodule

Simulation:
Results:
We have verified the truth table of Odd Parity, Even Parity, Half Adder and Full Adder. Their
outputs are correct.

Conclusion:
Parity comes in even and odd varieties. The output of an even parity generator will be a logic
1 if the data word has an odd number of ones. The parity generator's output will be low if the
data word has an even number of ones.
Half adders serve as a fundamental building component for aspiring digital artists. Two bits
can be added together using just a few basic logic gates, as demonstrated by a half-adder.
Because they can only accept two one-bit inputs, they are rarely used in practise.
Verilog code for simple modules conclusion full adder image result 1 bit
The output is 0 if all of the input bits are 0. When only one input or three inputs are equal to
1, the S output is also equal to 1. The c output has carry of 1 if two or three inputs are equal to
1.