UNIVERSITY OF ENGINEERING AND

TECHNOLOGY, TAXILA

Lab Report 13
Digital Logic Design Lab
Name: Alina Gulzar

Reg No.: 21-CP-06

Section: Omega

Department: Computer Engineering

Due Date: 13th August 2022

EXPERIMENT #13
BEHAVIORAL MODELING
Objective:
To understand and write Verilog code for small modules using Behavioral Modeling.

Apparatus List:

• Icarus Verilog installed on PC

LAB Tasks:
1. Write Verilog Code for 2x1 and 4x1 Mux using behavioral modeling along with Test Bench
and simulate it on Icarus Verilog.
2. Write Verilog Code for Encoder using behavioral modeling along with Test Bench and
simulate it on Icarus Verilog.
3. Write Verilog Code for Comparator along using behavioral modeling with Test Bench
simulate it on Icarus Verilog.

Design Methodology:
• First of all, we have to create a folder so that all the related files are in the same folder.
• Open Notepad, and write the Verilog code, save that notepad file in [module_name.v]
extension. The name of file and name of module must be same. As Verilog HDL is the case
sensitive Language so, a smallest mistake will cause an error.
• Again open notepad and write a test bench for the code file and save this file as syntax:
[module_nametb.v].
• Now, copy both files and open Local Disk: C → iverilog → bin → Paste the files.
• Click on the address bar.

• Write cmd in the bar and press enter key.

• A new interphase is opened…

• Now we have to write the commands, write → iverilog → -o → design name → test
bench file name (tb.v) → verilog code file name (.v) → Press Enter key.
• If there is no error present in the file, then write → vvp → design name → Press enter key.
• Now the vcd file is ready for the output.
• Copy the vcd file, and open Local Disk: C → iverilog → gtkwave → Paste the files.
• Click on the address bar.

• Write cmd in the address bar.

• Write → gtkwave → design name → Press Enter.

• The see the output on the gtkwave analyser.

Truth Table, assumptions, conventions, definitions, Karnaugh Map(s), algebraic simplification

steps, etc.
• Mux (2x1)

Verilog Code:
module m21( D0, D1, S, Y);
input wire D0, D1, S;
output reg Y;

always @(D0 or D1 or S)
begin

if(S)
Y= D1;
else
Y=D0;
end
endmodule

Test Bench:
module m21tb();
wire out;
reg d0, d1, s;
m21 name(.Y(out), .D0(d0), .D1(d1), .S(s));
initial
begin
d0=1'b0;
d1=1'b0;
s=1'b0;
#100 $finish;
end
always #40 d0=~d0;
always #20 d1=~d1;
always #10 s=~s;
always@(d0 or d1 or s)
$monitor("At time = %t, Output = %d", $time, out);
endmodule;

Simulation:
 • Mux (4x1)

Verilog Code:
module m41 ( a, b, c, d, s0, s1, out);
input wire a, b, c, d;
input wire s0, s1;
output reg out;
always @ (a or b or c or d or s0, s1)
begin case (s0 | s1)
2'b00 : out <= a;
2'b01 : out <= b;
2'b10 : out <= c;
2'b11 : out <= d;
endcase
endmodule
Test Bench:
module m41tb();

wire out;
reg a;
reg b;
reg c;
reg d;
reg s0, s1;

m41 name(.out(out), .a(a), .b(b), .c(c), .d(d), .s0(s0), .s1(s1));

initial
begin

a=1'b0; b=1'b0; c=1'b0; d=1'b0;

s0=1'b0; s1=1'b0;
#500 $finish;

end

always #40 a=~a;

always #20 b=~b;
always #10 c=~c;
always #5 d=~d;
always #80 s0=~s0;
always #160 s1=~s1;

always@(a or b or c or d or s0 or s1)
$monitor("At time = %t, Output = %d", $time, out);
endmodule;

Simulation:

• Encoder

Verilog Code:
module encoder (din, dout);

input [7:0] din;

output [2:0] dout;

reg [2:0] dout;

always @(din)

begin

if (din ==8'b00000001) dout=3'b000;

else if (din==8'b00000010) dout=3'b001;

else if (din==8'b00000100) dout=3'b010;

else if (din==8'b00001000) dout=3'b011;

else if (din==8'b00010000) dout=3'b100;

else if (din ==8'b00100000) dout=3'b101;

else if (din==8'b01000000) dout=3'b110;

else if (din==8'b10000000) dout=3'b111;

else dout=3'bX;

end

endmodule

Test Bench:
module encodert_b;
reg [0:7] d;
wire a;
wire b;
wire c;
encodermod uut (.d(d), .a(a), .b(b),.c(c) );
initial begin
#10 d=8’b10000000;
#10 d=8’b01000000;
#10 d=8’b00100000;
#10 d=8’b00010000;
#10 d=8’b00001000;
#10 d=8’b00000100;
#10 d=8’b00000010;
#10 d=8’b00000001;
#10 $stop;
end
initial
begin
$dumpfile ("encodertb.vcd");
$dumpvars (0, encodertb);
end
endmodule

Simulation:

• Comparator

Verilog Code:
module 3_Mag_Comp(
input [2:0]a,b,
output equal, greater, lower
);
reg greater, equal, lower;
initial greater = 0, equal = 0, lower = 0;
always @ (a or b)
begin
if (a < b)
begin
greater = 0; equal = 0; lower = 1;
end
else if (a == b)
begin
greater = 0; equal = 1; lower = 0;
 end
else
begin
greater = 1; equal = 0; lower = 0;
end
end
endmodule

Test Bench:
module 3_Mag_Comptb();

reg [3:0] a, b;
wire lower, equal, greater;

comp DUT (.a(a), .b(b), .lower(lower), .equal(equal), .greater(greater));

initial begin

A = 10;
B = 12;
#100;
A = 15;
B = 11;
#100;
A = 10;
B = 10;
#100;
end
initial
begin
$dumpfile ("3_Mag_Comptb.vcd");
$dumpvars (0, 3_Mag_Comptb);
end
endmodule

Simulation:

Result:
We have verified the truth table of 4-bit Full Adder and 4-bit Full subtractor. Their outputs are
correct.

Conclusion:
The behavioral modeling describes how the circuit should behave. Due to these factors,
structural or data-flow models are regarded as having a lower abstraction level than behavioural
models. The actual implementation of the circuit is determined by the VHDL synthesiser tool.
Results are more accurate by using behavioral modeling. Instead of theories, it concentrates on
how a system behaves.