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Graphene Based FET Report1
Graphene Based FET Report1
Course in charge
Prof. Ramesha C.K
Submitted by
Metal/graphene contacts:
In addition to the
graphene/substrate and graphene/gate-
oxide interfaces, the graphene/metal
interface forms the third important
interface in GFET devices. Being a
semimetal, graphene forms an Ohmic
contact with most of the metals. To realize
a low contact resistance Rc, metals with
Gate oxide formation:
high work function are normally used.
To fabricate a top-gated graphene Metals to be used for GFET electrodes
FET (TG-GFET), we need a qualified include Ti/Au, Cr/Au, Cr/Pt, and Co.
high-k gate insulator that is uniformly thin While analog applications can tolerate
enough with allowably low leakage current Rc~800 Ωμm, digital applications require
and interface trap density. Gate insulators Rc values at or less than 80 Ωμm.
can be formed by evaporation, natural
oxidation of deposited metals,28) and
atomic-layer deposition (ALD). While Configurations of Graphene FET:
ALD provides accurate control of the
thickness and high uniformity of the film, The GFET comes in three different
the method cannot be applied directly onto gate configurations. It can have a top gate,
the hydrophobic graphene surface without a global back gate, or both. The gate of a
chemical functionalization of graphene by GFET regulates the flow of electrons or
NO2 and O3 or insertion of an interfacial holes across its channel, just like in
polymer layer [8] prior to ALD. Other conventional silicon FETs. The single-
atom transistor channel allows all current
methods include deposition of metals (Al,
to flow on its surface, which accounts for
Hf) under oxidizing ambient. Quantum the great sensitivity of graphene FETs.
capacitance Equally important to Most of the current in silicon devices is
formation of gate oxide formation is the carried by electrons or holes. The GFET,
quantum capacitance. Because the density
on the other hand, permits equal carrier density, q is the charge per carrier,
conduction by electrons and holes. GFET and v is the mobility, the conductance of
devices often exhibit ambipolar behaviour, graphene is proportional to both its mobility
where in
and charge carrier density.As gate voltage
hole carrier conduction is observed in the
channel region under a negative bias. A rises, GFET conductivity rises concurrently
positive bias, on the other hand, causes with the electron (or hole) concentration
electron carrier conduction. The Dirac or rise brought on by positive or negative gate
charge neutrality point, which ideally voltages. The Fermi level of graphene
ought to be at zero voltage, is where the controls the variations in the carrier
two conduction curves converge. The concentration of the graphene channel. As
actual Dirac point, however, may change
gate voltage is provided, the Fermi level
in real life based on doping, the number of
impurities on the surface of graphene, the will be constantly driven via the Dirac point
surrounding environment, and other from the conduction band to the valence
factors. For instance, some p-doped band and vice versa. A considerable
graphene FET devices typically have number of holes are introduced into the
values between 10 and 40 volts. The four- valence band when the Fermi level is below
terminal GFET uses both the top and back the Dirac point. A good number of electrons
gates and is suited for some applications,
are introduced into the conduction band
while the rear gate GFET is the most
typical. The dual-gate GFET makes it when the Fermi level is above the Dirac
possible to bias the channel using two point. By applying a gate voltage, charge
distinct voltages. carriers (electrons and holes) may be tuned
continuously up to (10^13) cm^2 and have