ABSTRACT

Studies were done to make the temperature vs time graph of a large RC node ladder to match
with that of lower node RC ladder .the goal of bringing down or reducing the number of node is
to reduce the time complexity while simulating the circuit. This node reduction has been done
only empirically and no mathematical approach has been found or exist. So the goal this project
is to introduce a mathematical equation that helps to reduce the higher number of node to that
of lower number of node. This node reduction in helps with reducing the time complexity while
simulating the circuit.

This project proceeds in three stages starting empirically testing which is the minimum number of
the nodes either one or three or four nodes for making a good match of the lower node
temperature vs time graph to that of higher node temperature vs time graph.

Secondly we proceeded with finding the Z transform function for three node RC ladder and one
node Rc ladder and equated the S coefficient, so as to get a mathematical equation for the lower
node capacitor instead of choosing the capacitor value empirically each time the mathematical
equation is found and it also tested with many other node reduction experiments such as 9 to 3
10 to 3 21 to 3 24 to 3 30 to 4 and 50 to 4 node reduction. Here the larger number of RC ladder
will be consider as segments for instance a 30 node RC ladder is made into segments 8 9 10 and 3
and we reduce each segment to one node RC ladder and so we get a reduce four node Rc ladder

Finally we got value of Rc ladder for a semiconductor device with 5 emitter finger each serving as
heat source. Each finger will have a different temperature vs time graph and the formula found in
the before step will be checked with all the finger for three condition no trench shallow trench
and deep trench. This formula if found satisfying in the all condition, then it can be used for any
semiconductor devices tool

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 ACKNOWLEDGEMENTS
We would like to express our deep sense of gratitude to the Lord Almighty for giving us an
opportunity to do this project and showering his blessing in the due course of the project.

(Director)

(Registrar, Dean)

(Project co-ordinator)

HoD

Guide

others

Last but not the least, we thank our families and friends whose support and suggestions
helped us mould this project.

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TABLE OF CONTENTS

CHAPTE TITLE PAG

R NO E NO
ABSTRACT i
ACKNOWLEDGEMENT ii
TABLE OF CONTENTS iii
LIST OF FIGURES v
LIST OF SYMBOLS AND ABBREVIATIONS vi

1 INTRODUCTION
1.1 General Introduction 1
1.2 Objectives of the thesis 1

2 LITERATURE REVIEW 3

3 PROBLEM STATEMENT 4

4 METHODOLOGY 5

5 EMPERICALLY EXPERIMENT 3

6 MATHEMATICAL EXPLAINATION 7

7 VALIDATION OF ELMORE’S FORMULA WITH RESPECT

TO TCAD
7.1 No Trench
7.1.1 1st Finger No Trench 24
7.1.2 2nd Finger No Trench 24
rd
7.1.3 3 Finger No Trench 25
7.2 Shallow Trench
7.2.1 1st Finger shallow Trench 26
7.2.2 2nd Finger shallow Trench 27
7.2.3 3rd Finger shallow Trench 28

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 7.3 Deep Trench
7.3.1 1st Finger deep Trench 29
nd
7.3.2 2 Finger deep Trench 30
rd
7.3.3 3 Finger deep Trench 31

8 CONCULSION 32

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 LIST OF FIGURES

Figure Title Page No

No.
1 Closed loop system 5

2 Stability region for FOC 8

3 Pole Positions 12

4 Step response 13

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 LIST OF SYMBOLS

k- Thermal conductivity.
q- local heat flux density.
∇T-temperature gradient
ΔT - change in temperature

R- Resistant
C-Capacitate
α = scaling factor

V- Voltage
I- current
Pd - Power dissipated
Rth-thermal resistimes

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vii | P a g e
 CHAPTER 1
INTRODUCTION

1.1General Introduction
Our project is “efficient modeling and implementation of transient heating in
semiconductor devices.”A mathematical equation that efficiently describes the terminal
properties of a device as a function of the terminal voltage is called compact modeling.
Here we have thermal modeling comes into the picture as the currents and voltage of the
semiconductor device are available to us as a function of temperature (I=f(V, T)). That’s
why We consider the law of heat conduction, also known as Fourier's law, which states
that the rate of heat transfer through a material is proportional to the negative gradient in
the temperature and to the area, at right angles to that gradient, through which the heat
flows.

(q=−k ∇ T )

Pd
‘q’ is flux- Rate of heat flow per unit area q=
A

Which gives,

ⅆ T Pd (Fourier Law of Heat Conduction)

−k =
ⅆx A

On rearranging we get,

Δ T =P d R th

Here is Δ T =P d R thequation analogousto V=IR. A semiconductor device is divided into

infinite layers and by the Fourier law of heat conduction, each layer has a resistance ( Rth ¿
and by the propertythat heat flows from one layer to the other layer so each layer has
Thermal capacitance. Through this we can visualize the semiconductor devices as an
infinite number of nodes of Resistance and Capacitor thus forming an RCladder. if we use
the infinity RC node in the spice tool computation time increasesso we reduce the number
of nodes to 3-4. Also, we need the propose a mathematical relation to easily equate RC
higher node to lower node

1.2 Objectives of the thesis

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For explaining the heat diffusion problem in a semiconductor model the idea of the RC
ladder is used. For precision in heat diffusion in such a semiconductor model, the model is
divided into infinite layers and each layer represents RC. Now by using the spice tool for
this semiconductor model, the simulation time increases due to infinite nodes. Therefore,
to reduce the time complexity, the number of nodes is reduced from infinity to 3-4 nodes
which is more precise and consumes less simulation time. Also in the node reduction part,
there is no proper mathematical or qualitative relation that equates the R and C of a higher
node R-C ladder to a lesser node R-C ladder although empirically proved in the Spice tool

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 CHAPTER 2

LITERATURE REVIEW

The work in [1] studies the nonlinear physical model describing the static and dynamic
self-healing mechanism. The Key point in the paper states that if an additional node is
added to a transistor then that added node accounts for the increased self-heating effect in
the semiconductor. Interpretation of the relation between R’s and C’s of higher and lesser
nodes of the semiconductor is quite difficult to obtain, this is confirmed in the literature.

The work in [2] studies, new methods for approximating the thermal spreading impedance
of SiGe HBT devices with electrical equivalent circuits are presented. The electrical
equivalent circuits permit an accurate representation of the fractional behaviour of the
thermal impedance. Using these equivalent circuits, the thermal model can be implemented
in electrical SPICE type simulators. From the book [3]we study the RC ladder.

The work in [4]studies how dynamic thermal phenomena take place in SiGe HBTs when
excited by sinusoidal power dissipation. With the help of 3D thermal simulations, it
illustrates the effect on the spatial distribution of the temperature variations within the
transistor structure, according to the frequency of operation. HBT structures are designed
to analyze the impact on a real device. At higher frequencies, just the region close to the
heat source is concerned by dynamic thermal phenomena.

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 CHAPTER 3
PROBLEM STATEMENT

It is observed that on using an infinite number of nodes the problem of time complexity
arises. So to reduce the simulation time the idea of node reduction is used where an infinite
number of nodes is reduced to 3-4 nodes for better simulation time and precise solution.
Here another problem arises where the relation between R’s and C’s of an infinite RC
ladder to a 3-4 node RC ladder is not mathematically proven yet. Hence the problem being
worked on deals with mathematically proving the relation between R’s and C’s of an
infinite node RC to a 3-4 node RC.

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CHAPTER 4
METHODOLOGY

Started with a simpler step the relationship between R’s and C’s of a 2 node RC ladder to 1
node RC ladder is obtained by equating the real and imaginary parts of both the thermal
impedance equation and it’s been observed that the R’s of one node RC is equal to the
summation of R’s of the 2 node RC ladder, based on a condition that frequency tends to 0.
The condition differs for finding the C’s of 1 node RC ladder with a 2 node RC ladder.
Hence the methodology is being extended on finding the relationship between R’s and C’s
to a higher node per say 3 nodes to 2 nodes or 1 node RC ladder which paves the way for
getting familiarised with the relationship of R’s and C’s and the conditions to be
considered.

Then on empirically experimenting 10 node to 1 node RC ladder we get familiarised with

how temperature (K) vs time(s) graph of 1 node RC ladder behaves with that of the 10
node RC ladder in Qucstudio, Similarly we experimented with 10 node to 3 node RC
ladder and observed how the graph of 3 node RC ladder behaves with that of the 10 node.
Then we compared the graphs of 10 node to 1 node RC ladder and 10 node to 3 node RC
ladder. Then we approach in a mathematical way using 3 to 1 node, where we use Laplace
transform and found the transfer functions of 3 node and 1 node RC Ladder and we equate
the coefficients of S. Using this mathematical approximation we can find the value of C
for 1 node RC ladder.

Figure 4.1 -1node RC ladder

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 Figure 4.2 -3 node RC ladder

R
Z1 =
1+S RC

2
( R1 + R 2 + R 3 +S( R 1 R3 C3 + R 1 R2 C 2 + R 3 R 1 C 2 )+ S R1 R 2 R3 C 2 C 3
Z3 = 2
1+S( R1 C 1 + R2 C1 + R 3 C 1 + R3 C3 + R 2 C 2 + R3 C2 )+ S ( R1 R 3 C 1 C 3 + R1 R 2 C 1 C 2 + R1 R 3 C 1 C 2 + R2 R3 C 2 C 3 )+

Therefore on equating the coefficient of 𝑆 in Z1 ¿ Z 3

𝑅𝐶= ( R1 C1+ R2 C1+ R3 C1+ R3 C3 + R2 C2+ R3 C2 ) [For node 3:1]

( R 1 C 1 + R2 C 1 + R3 C 1 + R 3 C 3 + R2 C 2 + R 3 C 2 )
C= Here R = R1 + R 2 + R 3 ,
R

C
α= (Scaling Factor)
C1 +C 2 +C 3

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For different values of R1, R2, R3 and C1, C2, C3 we found different values of C both
empirically and mathematically and formulated a table to compare the results observed and
also found scaling factor for each simulation. We use scaling factor to determine the value
of C for a given value of R1, R2, R3 using the sum of C1, C2 ,C3 and not the coefficient
equation.The behaviour of the temperature (K) vs. time(s) graph of these RC ladders in
Qucstudio was then empirically tested using 10 node to 1 node and 10 node to 3 node RC
ladders. Then, utilising the 3 to 1 node technique, we employed the Laplace transform to
identify the transfer functions of the 3 node and 1 node RC Ladder and to equate the
coefficients of S. The value of C for a single node RC ladder can be determined using this
Elmores formula.

Generalized time delay is given as

n n
R 𝐶¿ ∑ ∑ Ci R j
i=1 j=i

R j is the ∑ of resistances¿ start of the segment i

C i-Capacitor of that segment

R is sum of the resistance of the considered segment

C is the capacitor value obtained from the segment reduction

C
α=
∑ C i (scaling factor)
i

Using the aforementioned equation, we conducted mathematical experiments with a 9

node to 3 node RC ladder to become familiar with its graphs. Then, in order to understand
how temperature (K) vs. time(s) graphs behave in Qucstudio, we experimented with 21
node to 3 node and 50 node to 3 node as these numbers are closer to infinity. We used data
from IIT Madras, Python code for R and C values, and more realistic TCAD data for
higher nodes. The objective is to bring a TCAD graph, a 50-node graph, and a 4-node in a
temperature(K) vs. time graph (s).

Since the above graph was successfully obtained then we used the Tcad data from IIT
Madras and python codes for R and C value for obtaining a temperature vs time graph for

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No trench, Shallow trench(St) and Deep trench(Dt). Elmores formula was used to
determine the R and C value and Microsoft Excel was also used to add the C values. For
No trench, St and Dt we experimented with the reduction of 30 node RC ladder with 4
node RC ladder and the temperature (K) vs. time(s) graphs was obtained for 1 st finger, 2nd
finger, 3rd finger. The Graph was successfully obtained and perfectly matched.

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 CHAPTER 5
EMPERICAL EXPERIMENTATION
During the initial stage for the reduction of higher node RC ladder to a lesser node RC
ladder we found the R and C value by empirical method of trial and error for obtaining a
logrithemic temperature vs time graph for lesser number of nodes that matches the graph
of higher nodes. From this experiment we found that reduction to 3-4 node is best for
obtaining the graph with lesser time complexity.
5.1 10 node to 1 node reduction
Here we reduced 10 node to 1 node RC ladder. The 10 resistance values of 10 node RC
ladder sums up to 4k ohms. The resistance is larger at source(analogous to current) and
keeps on decreasing towards the sink whereas capacitance increases from source to sink.
The value of current which is analogous to power dissipation is given to be 30 mA. For 1
node RC ladder the resistance value is R=4k ohms and C value is changed empirically to
fit the 10 node RC ladder. We simulate this circuit using qucstudio and bring the relation
between Temperature(K) vs Time(s) .On observing the resulting graphs we found that the
graphs of 1 node RC ladder doesn’t match with the graph of 10 node RC ladder. The

reason is that for 1 node RC ladderFigure

there5.1-10
is only
node1totime
1 nodeconstant
RC ladder (Time constant=RC)
which allows us to change the slope of the graph as a whole and not as segments of the
slope and here only the value of C can be changed because R is only 1 and fixed as 4k
ohms. This proves that we can’t reduce an infinite or n node RC ladder to 1 node RC
ladder as it doesn’t satisfy for even 10 node RC ladder.

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 Figure 5.2-graph for 10 node to 1 node RC ladder

5.2 10 node to 3 node

Here the same 10 node RC ladder set up is used in the previsions example and from an
other setup with three node in the RC ladder. now we use the same concept of decreasing
the resistance value and increasing the capacitor value from source to sink. empirically
experimenting on it we could match the temperature(K) vs time(s) graph of the 10 node
RC ladder to that of the 3 node RC ladder this is because we have access to all the 3
resistance and 3 capacitance values on changing these r’s and c’s value we can move the
slope of three node

RC ladder segment wise and precisely match the graph to that of the 10 node RC ladder
graph. Through this we can say that we can use the segment wise separation of slope of

Figure 5.3-10 node to 3 node RC ladder 10 | P a g e

the three node RC ladder and match its graph with any n node or infinite node RC ladders
graph.

Figure 5.4-graph 10 node to 3 node RC ladder

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 CHAPTER 6
MATHEMATICAL APPROACH
Since we successfully obtained a perfectly matched graph using empirical approach we
then used a mathematical formula or Elmore’s formula for obtaining the graph.The
Laplace transform was then used to determine the transfer functions of the higher node RC
ladder and lesser node RC ladders and compared the coefficients of S and found the
relation for C. This Elmore’s formula can be used calculate the value of R and C for a
Lesser node RC ladder.

6.1) 3 Node to 1 Node

Here we simulated three test with different RC values for both three node and one node
RC ladder. We conducted three simulation and each simulation is done as follows:
 we fix the three r values and three C values for a three node RC ladder. The sum of the
R will give 4k ohms. For one node RC ladder the value of R is 4k ohms and we
empirically change the value of c and try to match the temperature(k) vs time(s) graph
of one node RC ladder to that of the three node RC ladder .
 now we use the mathematical approximation to find the value of c in one node RC
ladder and use the value to simulate the graph. For this we use the equation as follows:

( R1 C 1 + R 2 C 1 + R3 C 1 + R 3 C 3 + R2 C 2 + R3 C 2 )
¿ Here R = R1 + R 2 + R 3 ,
R

Here the R,C is the resistance and capacitance value of one node RC ladders and
R1,R2,R3, and C1,C2,C3, are the resistance and capacitance values of three node RC
ladder.

 Now we formulate a scaling factor(α ) given by,

C
α=
C1 +C 2 +C 3
We use this scaling factor to compare the value of C in a 1 Node RC ladder to that of
sum of C1, C2, C3 in a 3 node RC ladder. For a fixed R1, R2, R3 in 3node RC ladder
and different values of C1,C2,C3 we can find the value of C using this scaling factor.
Scaling factor may vary for different values of R1, R2, R3.

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3 Node to 1 Node Reduction
(Emperical-1)

Figure 6.1- 3 node to 1 node RC ladder (emperical1)

Figure 6.2- graph 3 node to 1 node RC ladder (empirical1)

3 Node to 1 node Reduction

(Mathematical-1)

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 Figure 6.3- 3 node to 1 node RC ladder (math1)

3 Node to 1 Node Reduction

(Emperical-2)

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 Figure 6.5- 3 node to 1 node RC ladder (emperical2)

3 Node to 1 node Reduction

(Mathematical-2)

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Figure 6.6- graph 3 node to 1 node RC ladder (emperical2)

 Figure 6.8- 3 graph node
Figure
to 110
node RC ladder (math2)

3 Node to 1 Node Reduction

(Emperical-3)
Figure 6.10- graph 3 node to 1 node RC ladder (emperical3)

Figure 6.9- 3 node to 1 node RC ladder (emperical3)

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3 Node to 1 node Reduction
(Mathematical-3)

Figure 6.11- 3 node to 1 node RC ladder (math3)

Figure 6.12- graph 3 node to 1 node RC ladder (math3)

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From the above table we can observe that the empirical and mathematical value of C gives
the satisfying approximation in 3rd test but not in the first two test.

3 node to 1 node reduction we used the Elmore’s formula to find the capacitor value and
simulate in the ques studio

6.2) 9node to 3 node

In this reduction figure 6.13 we used the Elmore’s formula to find the capacitor value and
simulate in the ques studio we divided into 3 segment and in that we found that the starting
value of capacitor nearer to the current source is more so the curves mismatch to come
down so the capacitor should be less in first node of reduction circuit form this we went for
higher node and considered change in number of segments. The scaling factor for 1 st ,2nd
and 3rd segment is α 1= 0.520, α 2 = 0.573 and α 3= 0.520 respectively.

Figure 6.13- 9 node to 3 node RC ladder and graph

6.3) 21 node to 3 node

In this reduction figure 6.14 we used the Elmore’s formula to find the capacitor value and
simulate in the ques studio. The 21 node RC ladder is divided into 3 segment. The first
segment has 3 node and 2nd, 3rd section has 9 node each. C value of the 3 node RC ladder is
obtained from the Elmore’s formula. The scaling factor for 1 st ,2nd and 3rdsegment isα

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1=0.543 α 2 =0.381 and α 3=0.382respectively.Thus we obtain a perfectly matched
Temperature vs Time log graph. This result was satisfying.

Figure 6.14- 21 node to 3 node RC ladder and graph

6.4) 50 node to 4 node

In this reduction figure 6.15we used the Elmore’s formula to find the capacitor value
and simulate in the ques studio. We got the data from IIT Madars, a python code from
that we got the R value that is same for all nodes and C capacitor value of the node
differs, based on the assumption that the temperature difference between each layer is
less than 1K.
we also got data from TCAD simulation that has more realistic Temperature vs Time
graph values. We divided the 50 node ‘RC ladder to 4 segments, The first segment has
11 node and 2nd, 3rd ,4th section has 13 node each, C value of the 4 node RC ladder is
obtained from the Elmore’s formula. The scaling factor for 1 st ,2nd ,3rd and 4th segment
is α 1=0.348, α 2 =0.340, α 3=0.348 and α 4 =0.094respectively. Clearly the number of
segments considered didn’t give satisfying results. So we have to change the number of
segments and try new approach to get satisfying results.

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Figure 6.15- 50 node to 4 node RC ladder and graph

CHAPTER 7

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 VALIDATION OF ELMORE’S FORMULA WITH RESPECT TO TCAD
Since we successfully obtained the graph of 50 node RC ladder with respect to the Tcad
data from IIT Madras we have used these values of R and C for obtaining the temperature
vs time graphs for No trench, Shallow trench, Deep trench for a multifinger semiconductor
device.

7.1) No Trench
Given below in the figure 7.1 is a Multifinger semiconductor device the Tj1 to Tj5 are the
emiiter finger also serves as the heat source for a semiconductor devices. these finger or
contact points doesn’t have any trenches of oxides layer between them .so the name no
trench comes in. The 5th finger mimics the1st finger heat properties. The 4th finger mimics

the 2th fingers heat properties. The temperature is highest

Figure 7.1- NoFigure
trench in 3rd fingers due to the influence
1semiconductor

of both 2nd finger and 4th finger. ‘z’ describes the height of the device and ‘x’ is the length
of the device.

7.1.1 1st Finger No Trench

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The circuit at the top figure 7.2 of the finger is a 50 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below figure 7.3 is the four node reduction of the 50 node RC ladder and the graph in
the right side figure 7.3 is a temperature vs time in logarithmic scale with the results of TCAD
graph, the 50 node value and four node value

The property of first finger as that as fifth finger

Figure 7.2- 50 node to 4 node RC ladder and graph (finger 1 -No trench)

7.1.2 2nd Finger No Trench

The circuit at the top figure 7.3of the finger is a 50 node RC ladder that is executed using a Verilog
code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below figure 7.3 is the four node reduction of the 50 node RC ladder and the graph in
the right side figure 7.3 is a temperature vs time in logarithmic scale with the results of TCAD
graph, the 50 node value and four node value comparing the temperature vs time graph of the
first finger wwe can say that second finger overall temperature has increased due to the influence
of first and third finger

The property of second finger as that as fourth finger

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 Figure 7.3- 50 node to 4 node RC ladder and graph (finger 2- No trench)

7.1.3 3rd Finger No Trench

The circuit at the top of figure 7.4 the finger is a 50 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below figure 7.4 is the four node reduction of the 50 node RC ladder and the graph in
the right side figure 7.4 is a temperature vs time in logarithmic scale with the results of TCAD
graph, the 50 node value and four node value comparing the temperature vs time graph of the
second finger we can say that third finger overall temperature has increased due to the influence
of second and fourth finger

Figure 7.4- 50 node to 4 node RCFigure

ladder2 and graph (finger 3- No trench)
7.2 Shallow Trench

The figure 7.5 given below is an example of shallow trench isolation ,where the fingers are
isolated from each other by digging a pit on each side and filled with some oxide layer that

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doesn’t conducted heat properly. This make sure that there is no contact point any fingers. These
also increases overall temperature of the devices

Figure 7.5- Shallow trench

7.2.1 1st Finger shallow Trench

The circuit at the top of figure 7.6 the finger is a 30 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below figure 7.6 is the four node reduction of the 30 node RC ladder and the graph in
the right side figure 7.6 is a temperature vs time in logarithmic scale with the results of TCAD
graph, the 30 node value and four node value

The property of first finger as that as fifth finger

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Figure 7.6- 30 node to 4 node RC ladder and graph (finger 1- Shallow trench)
7.2.2 2nd Finger shaloow Trench

The circuit at the top of figure 7.7the finger is a 30 node RC ladder that is executed using a Verilog
code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below figure 7.12 is the four node reduction of the 30 node RC ladder and the graph in
the right side figure 7.12 is a temperature vs time in logarithmic scale with the results of TCAD
graph, the 30 node value and four node value comparing the temperature vs time graph of the
first finger we can say that second finger overall temperature has increased due to the influence
of first and third finger

The property of second finger as that as fourth finger

Figure 7.7- 30 node to 4 node RC ladder and graph (finger 2- Shallow trench)

7.2.3 3rd Finger shallow Trench

The circuit at the top of figure 7.8 the finger is a 30 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below figure 7.12 is the four node reduction of the 30 node RC ladder and the graph
in the right side figure 7.12 is a temperature vs time in logarithmic scale with the results of TCAD
graph, the 30 node value and four node value comparing the temperature vs time graph of the
second finger we can say that third finger overall temperature has increased due to the influence
of second and fourth finger

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7.3 DEEP TRENCH

This figure 7.9 contains both Shallow trench and deep trench. The deep trench is present at the
sides. When we extend the image, we get 2 devices. So, the main function of the deep trench is to
fill the trench between devices with oxides which has lower thermal conductivity so this
separates the two devices. The temperature in Dt is higher that St because of the presence of
more oxide layer.

Figure 7.9- Deep trench

7.3.1 1st Finger deep Trench

The circuit at the top of figure 7.10 the finger is a 30 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below the figure 7.10 is the four node reduction of the 30 node RC ladder and the
graph in the right side of the figure 7.10 is a temperature vs time in logarithmic scale with the
results of TCAD graph, the 30 node value and four node value

The property of first finger as that as fifth finger

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 Figure 7.10- 30 node to 4 node RC ladder and graph (finger 1- Deep trench)

7.3.2 2nd Finger deep Trench

The circuit at the top of figure 7.11 the finger is a 30 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below of figure 7.11 is the four node reduction of the 30 node RC ladder and the graph
in the right side of figure 7.11 is a temperature vs time in logarithmic scale with the results of
TCAD graph, the 30 node value and four node value comparing the temperature vs time graph of
the first finger we can say that second finger overall temperature has increased due to the
influence of first and third finger

Figure 7.11- 30 node to 4 node RC ladder and graph (finger 2- Deep trench)
The property of second finger as that as fourth finger

7.3.3 3rd Finger deep Trench

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The circuit at the top of figure 7.12 the finger is a 30 node RC ladder that is executed using a
Verilog code in qucstudio using r and c values from the python code already given. It also has an
ammeter and a voltmeter and current source

The circuit below of figure 7.12 is the four node reduction of the 30 node RC ladder and the
graph in the right side of figure 7.12 is a temperature vs time in logarithmic scale with the results
of TCAD graph, the 30 node value and four node value comparing the temperature vs time graph
of the second finger we can say that third finger overall temperature has increased due to the
influence of second and fourth finger

Figure 7.12- 30 node to 4 node RC ladder and graph (finger 3- Deep trench)

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 CHAPTER 3
PROBLEM STATEMENT
 We developed an Elmore’s formula to reduce ‘N’ node RC ladder to a lesser node
RC ladder. Now the users can use this mathematical formula to recreate the
temperature vs time graph for a given semiconductors without empirical approach.

 We used the Elmore’s formula to successfully obtain the graphs for No trench,
shallow trench, deep trench conditions for a device with 5 fingers using the TCAD
data from IIT Madras

 We also found that the reduction to 3 or 4 node is the best approach to reduce time
complexity and suits well with the graph of higher nodes in a simulation for a
semiconductor device.

Future works

We will be studying more about the transient heating and heat flow in a semiconductor
devices

 After that we simulate on COMSOL.

 COMSOL-FEA, Fast, link to AutoCAD

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