Indian Institute of Technology Goa

EE 232 Digtial Circuits and Lab

Instructor: Nandakumar Nambath
Assignment I

General instructions:

• Please go through the video Introduction to VHDL, and the files Introduction to VHDL Slides and
Quartus Design Flow before you attempt this assignment.

• This assignment is to get you familiarized with the Quartus Prime Lite and Modelsim software as
well as the Quartus design flow.

• Prepare a zip file with a name <Roll No> Assignment1.zip that has the following files: (i) <Roll
No> OR2.sof (the .sof file from the output files directory), (ii) <Roll No> Wave.png (a screenshot of
your Modelsim simulations), and (iii) <Roll No> Pins.txt (a text file containing the pin mapping).

• I hope I don’t have to remind you that this is not a group activity.

• The maximum upload size is 2 MB and the deadline is 2 pm on 07-09-2021.

• You are free to assume any missing data, but state them clearly in your solution. Feel free to use
the Telegram group to discuss any doubts, but not the solutions.

• Marks: sof and pin mapping files - 5 Marks and Modelsim screenshot - 5 Marks

1. Create a project with the name <Roll No> OR2 using Quartus. (Note: Remember the .sof file will
be generated with the project name).

2. Write a VHDL structural architecture of a two input OR gate, the entity declaration of which is given
below.

entity <Roll No>_OR2 is

port(I0, I1 : in std_logic;
O0 : out std_logic);
end <Roll No>_OR2;

3. Compile the design and verify the functionality through Modelsim simulations.

4. Assign I0 to SW[0], I1 to SW[1], and O0 to LEDR[0] using the pin planner. Compile the design and
verify the functionality through Modelsim simulations. Select the files to upload to the submission
page.