The ATmega324 Microcontroller

Chapter 2
Hardware Summary

Nguyễn Trung Hiếu

Ref: Giáo trình Vi Xử Lý, BMĐT
Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu
 Features of ATmega324

Memory:
• 32KB Flash code memory
• 1KB EEPROM
• 2KB SRAM

Peripherals:
• 32 programmable I/O Lines
• SPI and JTAG interface
• Timer/Counters/PWM
• 10-bit ADC
• 2 programmable USART
• SPI/I2C

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 Comparison of AVR Family

IC Flash ROM RAM EEPROM I/O ADC Timers Package

code mem data mem data mem Ports

ATmega8 8K 1K 0.5K 23 8 3 TQFP32,

PDIP28
ATmega16 16K 1K 0.5K 32 8 3 TQFP44,
PDIP40
ATmega32 32K 2K 1K 32 8 3 TQFP44,
PDIP40
ATmega64 64K 4K 2K 54 8 4 TQFP64,
MLF64
Atmega1280 128K 8K 4K 86 16 6 TQFP100,
CBGA

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 PDIP Package

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 TQFN/QFN Package

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 ATmega324 block diagram
AVR CPU Memory

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 AVR CPU Core

1. Fetch: PC → (MEM) → IR
2. Decode: IR→ID:
Choose register and operator
3. Execute: ALU execute,
then write back to RF

When reset: PC  0000H

SRAM

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 Instruction Execution Timing

Pipeline technique speed up execution

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 Register File

• 32 x 8-bit registers (R0-R31)

• Special: 6 registers from R26 – R31
can be used as three 16-bit registers
named 16-bit X, Y, Z

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 ALU

• Support arithmetic, logical, and bit-functions

• Support both signed/unsigned multiplication
• Has STATUS REGISTER: updated after all ALU operations
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 SRAM Memory
Include: - Register File (32 x 8-bit registers)
- I/O memory (64 x 8-bit registers)
- Extended I/O memory (160 x 8-bit registers)
- internal data SRAM (2K x 8-bit registers)

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 Data Memory Map with SRAM

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 SRAM – GPRs
LDI Rd,K
(d:1631; K:0  255)
Rd  K

MOV Rd,Rr
(d,r:031)
Rd  Rr

MOVW Rd+1:Rd,Rr+1:Rr
MOVW Rd,Rr
(d,r:0,2,4,..,30)
Rd+1:Rd  Rr+1:Rr

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 SRAM
I/O memory

IN Rd,P
(d:031)
Rd  P

OUT P,Rr
(r:031)
P  Rr

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 SRAM
extended I/O
memory

LDS Rd,P
(d:031)
Rd  P

STS P,Rr
(r:031)
P  Rr

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 SRAM – Internal SRAM
• Address: $100 - $8FF
• Access using LDS and STS, similar to extended I/O memory
• Used to store data and as a STACK

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 SRAM – Internal SRAM as STACK

• LIFO: Last In First Out

• Register SP: 2 register 8-bit (SPH and SPL)
& always point to top of the stack
• PUSH: SP storing data on the stack and then decreases
• POP: data is read from the stack and then SP increases
• The reset value of SP is 8FFH → Stack is from 08FFH

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 Stack Operation Example 1
Ex: LDI R20,$15
LDI R21,$0F R20 15H R21 0FH R22 E9H
LDI R22,$E9
8FCH 8FCH
PUSH R20 8FDH 8FDH
PUSH R21 8FEH SP=8FEH
PUSH R22 SP=8FFH 8FFH 15H

…
8FCH SP=8FCH
LDI R20,$67
SP=8FDH 8FDH E9H
LDI R21,$D8 8FEH 0FH 8FEH 0FH
LDI R22,$63 8FFH 15H 8FFH 15H
…
POP R22 R20 67H R21 D8H R21 63H

POP R21
R20 15H R21 0FH R22 E9H
POP R20
 Stack Operation Example 2
Ex: LDI R20,$15 R20 15H R21 2FH
LDI R21,$2F
8FCH 8FCH
PUSH R20
8FDH 8FDH
PUSH R21 8FEH SP=8FEH
POP R20 SP=8FFH 8FFH 15H
POP R21
8FCH
SP=8FDH
8FEH 2FH
8FFH 15H

R20 2FH R21 15H

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 SRAM – Internal SRAM as STACK

Example: Init SP value point to address $750

.ORG 0
LDI R16, HIGH($750)
OUT SPH, R16
LDI R16, LOW($750)
OUT SPL, R16

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 SREG REGISTER – Status Register

• Bit 7 – I: Global Interrupt Enable

• Bit 6 – T: Copy Storage
• Bit 5 – H: Half Carry Flag (used in BCD arithmetic)
• Bit 4 – S: Sign Flag, S = N ⊕V
• Bit 3 – V: Two’s Complement Overflow Flag
• Bit 2 – N: Negative Flag
• Bit 1 – Z: Zero Flag
• Bit 0 – C: Carry Flag

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 SREG REGISTER – Status Register
Example: LDI R20,$54
LDI R25,$C4
ADD R20,R25

Note:
• V = C  CMSB
• S = N  V (S is real sign of the result)
• Z = 1 if the result is zero, 0 otherwise
 SREG REGISTER – Example 1

Verify using AVR Studio

23
 SREG REGISTER – Example 2

Verify using AVR Studio

24
 SREG REGISTER – Example 3

Verify using AVR Studio

25
 FLASH – CODE (PROGRAM) MEMORY

• Capacity: 32KB
• All instructions in AVR are 16 or 32
bits wide
→ Flash is organized 16K x 16 bits =
16KW

• Address bits: 15 bit

→ PC is 15 bits wide
• Two parts: Boots section & Application
section
• Data is stored in Little Endian format

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 (Remind) Little Endian and Big Endian

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 Data in Flash Memory

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 Access Flash Memory
WRITE:
• Download code using the SPI pins or JTAG interface
• Use preprocessor directive
Example: .DW $ABCD (Create data 0xABCD in Flash)
• Use instruction: SPM (Store Program Memory)
Description: (Z)  R1:R0

READ:
• Use instruction: LPM (Load Program Memory)
Format: LPM Rd,Z
Description: Rd  (Z)
• Only read data at High Address or Low Address once
Low address: (Address)<<1
High address: ((Address)<<1)|1
Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu
Example: Create a 2-byte numeric data $BC13 (0xBC13) in Flash.
Write a program that read the low byte and store it in R1 and read
the high byte and store it in R2.

.ORG 0
LDI ZL,LOW(MYDATA<<1)
LDI ZH,HIGH(MYDATA<<1)
LPM R1,Z
LDI ZL,LOW((MYDATA<<1)|1)
LDI ZH,HIGH((MYDATA<<1)|1)
LPM R2,Z
MYDATA: .DW $BC13

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 EEPROM Memory

• Capacity: 1KB
• Address: 10-bit (from 0x0000 – 0x03FF)
• Endurance of at least 100,000 write/erase cycles
• Data is NOT erased when power off (Non-volatile)
• Access through special registers: EECR, EEAR and EEDR
(More detail in chapter textbook)

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 Around The Pins

Each I/O pin can be

assigned to another
peripheral functions

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 I/O Port Structure

Input Output
DDRx: 7 6 5 4 3 2 1 0

PORTx: 7 6 5 4 3 2 1 0

DDRx
0 1
PINx: 7 6 5 4 3 2 1 0 PORTx

0 high impedance Out 0

Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 1 pull-up Out 1
Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu
 I/O Port Structure
IO SRAM
Port Usage
Address Address
PINA $00 $20 Input
DDRA $01 $21 Direction
PORTA $02 $22 Output
PINB $03 $23 Input
DDRB $04 $24 Direction
PORTB $05 $25 Output
PINC $06 $26 Input
DDRC $07 $27 Direction
PORTC $08 $28 Output
PIND $09 $29 Input
DDRD $0A $2A Direction
PORTD $0B $2B Output

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 I/O Port Registers - Direction

• Address: DDRA – 0x21 (SRAM address)

DDRB – 0x24
DDRC – 0x27
DDRD – 0x2A
• Pin x is output  Bit x = 1
Pin x is input  Bit x = 0

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 I/O Port Registers - Data

• Address: PORTA – 0x22 (SRAM address)

PORTB – 0x25
PORTC – 0x28
PORTD – 0x2B
• When direction is output:
Pin x = 1 Bit x = 1
• When direction is input:
Pin x has pull up resistor  Bit x = 1

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu

 I/O Port Registers – Port Input

• Address: PINA – 0x20 (SRAM address)

PINB – 0x23
PINC – 0x26
PIND – 0x29
• Data read from pin x  Data in bit x

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• 𝑅𝐸𝑆𝐸𝑇:

Power-on Reset External Reset

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• XTAL1 , XTAL2: 2 main methods

Crystal Oscillator Inputs External Clock

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 System Clock

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 References

• Giáo trình Vi xử lý, BMĐT

• Các tài liệu trên Internet không trích dẫn hoặc không ghi tác
giả

Ref: Giáo trình Vi xử lý Nguyễn Trung Hiếu