How to implement an EtherCAT

Slave Device

Martin Rostan
 Agenda

EtherCAT Slave 1. EtherCAT Slave Structure Overview

Structure
Device Definition
2. First Steps: Device Definition
- Integrated or 3. Hardware Design
Interface Device
- Hardware 4. Software Development
Selection
- Device Profile
5. Conformance Testing
- Process Data 6. Common Issues – and how to avoid them
- Synchronization
HW Design
SW Development
Conformance
Testing
Common Issues –
and how to avoid
them

February 2011 © EtherCAT Technology Group 2

 EtherCAT Slave Structure Overview

EtherCAT Slave EtherCAT Master / Device Description File

Structure
Configuration Tool
Device Definition
- Integrated or
Interface Device
XML
- Hardware
Selection
- Device Profile
- Process Data EtherCAT Slave Device
- Synchronization
Application /
µC
HW Design Host Controller
SW Development
I2C
EtherCAT ESC
Conformance Slave
EEPROM
Testing Controller

Common Issues –
TRAFO

TRAFO
and how to avoid
RJ45

RJ45
PHY PHY
them
Network Interface Hardware / Physical Layer

February 2011 © EtherCAT Technology Group 3

 First: Device Definition

EtherCAT Slave Define / Select:

Structure
Device Definition 1. Fully integrated Design or Interfacing Device
- Integrated or
Interface Device
2. Interface Hardware
- Hardware 3. Device Profile
Selection
- Device Profile 4. Parameter + Process Data
- Process Data
5. Synchronization and Time Stamping Requirements
- Synchronization
HW Design
SW Development
Conformance
Testing
Common Issues –
and how to avoid
them

February 2011 © EtherCAT Technology Group 4

 Fully integrated or Interfacing Device?

EtherCAT Slave Fully integrated Interfacing device

Structure
Device Definition
- Integrated or
Interface Device
- Hardware PRO: PRO:
Selection
- Device Profile
• Lower hardware costs • Lower development costs
- Process Data • Most flexible solution • Time to market
- Synchronization
• Full control of all features • Less network know-how
HW Design
required
SW Development
Conformance CON: CON:
Testing
Common Issues –
• Higher development costs • Higher hardware costs
and how to avoid
them • Form factor restrictions

February 2011 © EtherCAT Technology Group 5

 Interface Hardware?

EtherCAT Slave Fully integrated Design*:

Structure
Device Definition • Host / Application µC
- Integrated or Controller
Interface Device
- Hardware
Selection
- Device Profile • EtherCAT Slave ESC
- Process Data Controller
- Synchronization
HW Design

Connector
TRAFO
Connector

TRAFO

PHY
PHY
SW Development • Physical Layer,
Conformance Network Interface
Testing
Common Issues –
and how to avoid
them

* Interfacing Device Hardware Selection: no generic rules

February 2011 © EtherCAT Technology Group
due to the diverse architectures of the various solutions 6
 EtherCAT Host Controller?

EtherCAT Slave • Simple (I/O) Devices do not require a µC at all

Structure
Device Definition • Tasks of Host µC in more complex devices:
- Integrated or – Process data – Exchange with the Application
Interface Device
– Object Dictionary Handling
- Hardware
Selection – Handling of Application Parameter
- Device Profile (Communication Parameter are handled by ESC)
- Process Data – TCP/IP Stack Handling – if required
- Synchronization
HW Design
• Host Controller Performance is determined by
SW Development
Conformance
Device Application, not by EtherCAT
Testing  In many cases an 8bit µC is sufficient
Common Issues –
and how to avoid
them

February 2011 © EtherCAT Technology Group 7

 EtherCAT Host Controller Interface?

Host CPU

The host controller may determine

HTTP,

EtherCAT Slave Service

FTP,… RAM for TCP/IP
and complex
TCP/IP Applications
Structure the interface to internal DPRAM
Process Data Data
(optional)

Device Definition of the EtherCAT Slave Controller

EtherCAT
Application Mapping
Slave
Controller
Process Data Mailbox
- Integrated or Dual Port Memory non volatile Data

Interface Device Sync-Manager, FMMU Registers

- Hardware Example: Beckhoff ASICs: Auto-Forwarder with Loop Back

Selection
• 8/16 Bit µC Interface EtherCAT MAC
MII
EtherCAT MAC
MII
- Device Profile
– Demultiplexed

Trafo

Trafo
RJ45
RJ45
- Process Data PHY PHY

– Intel Signal Types

- Synchronization
– Polarity configurable (BUSY, INT)
HW Design
– Typical µC: ARM, Infineon 80C16x, Hitachi SH1, ST10, TI
SW Development
TMS320 Series, …
Conformance
Testing
Common Issues – • Serial – Interface (SPI)
and how to avoid – Up to 10 MBaud
them
– µC is SPI Master
– Typical µC: Microchip PIC, DSPic, Intel 80C51, Atmel AVR…
February 2011 © EtherCAT Technology Group 8
 EtherCAT Slave Controller?

EtherCAT Slave ASIC FPGA

Structure
Device Definition
- Integrated or
Interface Device
- Hardware PRO: PRO:
Selection
- Device Profile
• Low costs, small • Most flexible: FPGA can
integrate application
- Process Data • netx: Multiple networks
functionality as well
- Synchronization supported
HW Design • Low costs especially if
CON:
SW Development FPGA is used anyhow
Conformance • Less flexible
Testing
• Can support multiple
Common Issues –
Ethernet flavors
and how to avoid
them CON:
• Requires VHDL
programming know-how
February 2011 © EtherCAT Technology Group 9
 Selection Criteria EtherCAT Slave Controller

EtherCAT Slave • No (and type) of Ports

Structure
• Typical: 2-port devices, for line and ring topologies
Device Definition
• 3+4-port devices cater for topology options
- Integrated or
Interface Device
- Hardware 2 3 2 2 2 2
Selection
- Device Profile
- Process Data
4 2 3 2
- Synchronization
HW Design
SW Development
Conformance 1-port only for devices powered 1
Testing by Power over EtherCAT
Common Issues –
and how to avoid
them

February 2011 © EtherCAT Technology Group 10

 Selection Criteria EtherCAT Slave Controller

EtherCAT Slave • Size of DPRAM and no. of Sync Manager entities

Structure
Device Definition
ESC DPRAM
- Integrated or Register 4KByte
Interface Device
- Hardware
Selection Parameter Data Mailbox Out Sync Manager 0
- Device Profile (acyclic)
Mailbox In Sync Manager 1
- Process Data
- Synchronization Output Data Buffer 1
HW Design e.g.
Buffer 2 SM 2
SW Development 1..60

Conformance Process Data Puffer 3 KByte

Testing (cyclic)
Input Data Buffer 1
Common Issues –
and how to avoid Buffer 2 SM 3
them
Buffer 3

February 2011 © EtherCAT Technology Group 11

 Selection Criteria EtherCAT Slave Controller

EtherCAT Slave • No. of Fieldbus Memory Management Units (FMMU)

Structure
• FMMU: copies process data from EtherCAT
Device Definition
datagram to DPRAM – and ensures data consistency
- Integrated or
Interface Device • Mechanism for further optimization of resources
- Hardware (bandwidth, CPU power)
Selection
• Typical requirement: minimum of 3.
- Device Profile
- Process Data
- Synchronization
HW Design
FMMU Number Usage
SW Development 1 Output Data
Conformance 2 Input Data
Testing
3 Status check of Mailbox Response
Common Issues –
and how to avoid
them

February 2011 © EtherCAT Technology Group 12

 Selection Criteria EtherCAT Slave Controller

EtherCAT Slave • Price?

Structure
• Local Support?
Device Definition
• Housing?
- Integrated or
Interface Device • Size?
- Hardware • Integrated PHYs?
Selection
– Hilscher netX
- Device Profile
- Process Data
• Integrated CPU?
- Synchronization – Hilscher netX
HW Design – FPGA solutions (optional: softcore)
SW Development • Need to disclose quantities?
Conformance – FPGA solutions (buy out licenses available)
Testing
• Multi Protocol Support
Common Issues –
and how to avoid – Hilscher netX
them – FPGA solutions

February 2011 © EtherCAT Technology Group 13

 Physical Layer, Network Interface?

EtherCAT Slave EtherCAT Physical Layer is 100BASE-TX or –FX*

Structure
Device Definition
- Integrated or EtherCAT PHYs have to support
Interface Device
- Hardware • Full Duplex Communication
Selection
• Auto-Negotiation, MDI/MDI-X auto-crossover
- Device Profile
- Process Data
• MII with MII management interface
- Synchronization • PHY link loss reaction time (link loss to link
HW Design signal/LED output change) shorter than 15µs (for
SW Development short redundancy switchover)
Conformance
Testing For further details see the ESC Datasheets or the
Common Issues – corresponding PHY Selection Guide
and how to avoid
them

* + LVDS for modular devices, supported by Beckhoff ASICs only

February 2011 © EtherCAT Technology Group 14
 Device Profile?

EtherCAT Slave • Which device profile shall be supported?

Structure
Device Definition • Drive: both CiA402
- Integrated or (the CANopen drive profile,
Interface Device
IEC 61800-7-201) and the
- Hardware
Selection Sercos-Drive-Profile
- Device Profile (IEC 61800-7-204) are
- Process Data mapped on EtherCAT
- Synchronization
HW Design
• If the device can be described as hardware
SW Development
modules or as logical modules:
Conformance – Modular Device Description recommended
Testing
Common Issues –
– Modular Device Profile (ETG.5001)
and how to avoid
them

February 2011 © EtherCAT Technology Group 15

 Parameter + Process Data?

EtherCAT Slave Device Profile determines Parameters and

Structure
Device Definition
Process Data setup
- Integrated or But: decision if the Process Data Layout shall be:
Interface Device
- Hardware → Fixed: cannot be changed by user.
Selection Example: simple I/O device.
- Device Profile
→ Selectable: user can select between several predefined
- Process Data
process data layouts.
- Synchronization Example: drive where process data layout depends on the
HW Design selected drive operation mode
SW Development
→ Determined by module combination (Dynamic):
Conformance
Testing determined at device bootup by actual hardware modules;
Common Issues –
Example: bus coupler with modular I/O.
and how to avoid
them

February 2011 © EtherCAT Technology Group 16

 Synchronization and Time Stamping?

EtherCAT Slave What level of Synchronization is required?

Structure
Device Definition 1. Freerun:
- Integrated or local timer controls application, no
Interface Device synchronization with network
- Hardware
Selection
- Device Profile 2. Synchronized with network cycle:
- Process Data local application triggered by reception of process data
- Synchronization (“SM-event”). Jitter mainly depends on master accuracy.
HW Design
SW Development
Conformance 3. Synchronized by Distributed Clocks:
Testing local application triggered by high precision and fully
Common Issues – synchronized hardware interrupt generated by local clock;
and how to avoid
them
accuracy in the order of nanoseconds

February 2011 © EtherCAT Technology Group 17

 Hardware Design

EtherCAT Slave
Structure
Device Definition Application / Host Controller
- Integrated or According to the Application
Interface Device Requirements
- Hardware
Selection EtherCAT Slave
- Device Profile µC EtherCAT Slave Controller
- Process Data
I2
Acording to the ESC Selection
ESC
Criteria
EEPROM
C
- Synchronization
HW Design
TRAFO

TRAFO
RJ45

PHY PHY RJ45

SW Development
Conformance
Testing
Network Interface / Physical Layer
Standard Ethernet Interface,
Common Issues –
and how to avoid
Requirements according to
them PHY Selection Guide / ESC Data
Sheet

February 2011 © EtherCAT Technology Group 18

 Software Development

EtherCAT Slave Typical Software-Structure:

Structure
• Applications-Program/Firmware
Device Definition
• Communication-Stack with the following elements:
- Integrated or
Interface Device – EtherCAT State Machine
- Hardware – Verification of the configuration settings done by master
Selection – Handling of synchronization + configuration errors
- Device Profile – Mailbox-Protocol Handling
- Process Data – Most common protocol: CoE
- Synchronization – Error Handling (e.g. Parameter cannot be read or written)
HW Design – Access to ESC memory (DPRAM)
SW Development – Synchronization
Conformance
Testing
The listed functionality is supported by most available stacks,
Common Issues –
and how to avoid such as
them – Beckhoff Slave Sample Code
– Hilscher EtherCAT Slave Stack)

February 2011 © EtherCAT Technology Group 19

 Device Description: ESI File

EtherCAT Slave • Each EtherCAT Slave device is described by an

Structure „EtherCAT Slave Information“ (ESI) File in XML Format
Device Definition
• The ESI Format is defined
- Integrated or
Interface Device
in the ETG.2000 spec
- Hardware • Of course there are also a
Selection schemas, example files etc.
- Device Profile on the EtherCAT website
- Process Data • The ESI also
- Synchronization supports the
HW Design description of
SW Development modular devices
Conformance
Testing
Common Issues –
and how to avoid
them

February 2011 © EtherCAT Technology Group 20

 Conformance Testing

EtherCAT Slave • The EtherCAT Conformance Test Tool (CTT) is helpful

Structure throughout the implementation – and afterwards
Device Definition
• Having the CTT and testing with it is a requirement
- Integrated or
Interface Device • Recommended Procedure:
- Hardware – If not yet ETG member: Join ETG (free of charge)
Selection – Obtain EtherCAT Vendor ID (free of charge)
- Device Profile
– Subscribe to Conformance Test Tool
- Process Data
– Conformance Test Record (ETG.7000-2) is Test Guideline
- Synchronization • Test with CTT
HW Design • Test of the LED behavior (ETG.1300)
SW Development • Marking and Trademark Hints (ETG.9001)
Conformance • Further tests
Testing
Common Issues –
and how to avoid • Test in official EtherCAT Test Center (and Certification) is
them optional, but recommended

February 2011 © EtherCAT Technology Group 21

 Common Issues – and how to avoid them!

EtherCAT Slave The 5 „Killer“ for passing the conformance test:

Structure
Device Definition
1. Logo:
Neither on the device nor in the documentation the EtherCAT
- Integrated or
Interface Device logo is shown
- Hardware 2. Trademark:
Selection
Trademark hint is missing in the documentation
- Device Profile
- Process Data
3. Indicator and Port Marking:
Marking is missing or misleading
- Synchronization
HW Design 4. Watchdog Behavior:
SW Development If sending of process data is stopped the device does not show
the required behavior
Conformance
Testing
5. DC-Signal Monitoring:
Common Issues – If the interrupt for the synchronization is disabled the device
and how to avoid
them does not show the required behavior

February 2011 © EtherCAT Technology Group 22