Unit 1-Vlsi

RAJIV GANDHI COLLEGE OF ENGINEERING AND TECHNOLOGY PUDUCHERR
EC E62-VLSI DESIGN
UNIT I
CMOS Technology: Introduction to MOS transistors and VLSI fabrication (NMOS, PMOS,
CMOS and BiCMOS)- Introduction to power reduction techniques-Dynamic Power
Reduction-Static Power Reduction- NMOS and CMOS inverter- Determination of pull up to
pull down ratios – propagation delays – power dissipation - Stick Diagram -MOS layers -
design rules and layout- choice of layers and Scaling.
2 Marks
1. What is the need for demarcation line? (Sep 2020)
In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All
PMOS must lie on one side of the line and all NMOS will have to be on the other
side.
2. List the techniques used for static power reduction. (Sep 2020)
Static power is proportional to circuit leakage current and supply voltage Vdd. Thus
we have following ways to reduce static power:
1. Dynamic Vth scaling by adjusting substrate bias
2. Use multi-Vth devices in design
3. Use high-Vth device whenever possible
4. Dynamic supply voltage scaling
5. Use multi-Vdd in design
6. Shut off the power in standby mode
3. Mention the various types of power dissipation that occurring in the VLSI
circuits (Nov 2019)
1. Static power dissipation (due to leakage current when the circuit is idle)
2. Dynamic power dissipation (when the circuit is switching)
3. Short-circuit power dissipation during switching of transistors.
4. List the different process steps involved in CMOS fabrication process (May 2019)
CMOS Fabrication Steps
1. Substrate.
2. Oxidation.
3. Growing of Photoresist.
4. Masking of Photoresist.
5. Removal of Photoresist.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC E62-VLSI DESIGN Page 1
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6. Etching of SiO2.
7. Removal of Photoresist Layer.
8. Formation of N-well.
5. Compare NMOS and CMOS technology. (Nov 2018)
CMOS NMOS
CMOS stands for Complementary metal- NMOS stands for N-type metal oxide
oxide-semiconductor semiconductor
This technology is used to make ICs which are
used in different applications like batteries,
electronic components, image sensors, digital NMOS technology is used to make logic gates
cameras. as well as digital circuits
CMOS employs symmetrical as well as
complementary pairs of MOSFETs like p-type The operating of NMOS transistor can be done
& n-type MOSFETs for the operation of logic by making an inversion layer within a p-type
functions transistor body
CMOS is used in Digital logic circuits,
Microprocessors, SRAM (Static RAM) & NMOS is used to implement digital circuits as
Microcontrollers well as logic gates.
The NMOS logic level mainly depends on beta
The CMOS logic level is 0/5V ratio as well as poor noise margins
The transmission time of CMOS is tI=tf The transmission time of CMOS is tI>tf
Layout of CMOS is more regular The layout of NMOS is irregular
Load or drive ratio of CMOS is 1:1/2:1 Load or drive ratio of NMOS is 4:1
Packing density is denser, N+1 device for N-
Packing density is less, 2N device for N-inputs inputs
The power supply may change from 1.5 to
15V VIH/VIL, a fixed fraction of VDD The power supply is fixed based on VDD
Transmission gate of CMOS will pass both
logic well Only pass ‘0’, well pass ‘1’ will have VT drop
Pre-charging scheme of CMOS is, for both n
& p are accessible for the pre-charging bus to Simply charges from VDD to VT except utilize
VDD/VSS bootstrapping
In NMOS, when output is ‘0’ then power
Power dissipation is zero in standby dissipates
6. What is meant by power dissipation? (Nov 2018)

The definition of power dissipation is the process by which an electronic or electrical
device produces heat (energy loss or waste) as an undesirable derivative of its primary
action.
7. Compare Bipolar and CMOS technology. (Apr 2018)

CMOS BIPOLAR

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Low static power dissipation High power dissipation

High input impedance Low input impedance
High noise margin Low voltage swing logic
High package density Low package density
High delay sensitivity to load Low delay sensitivity to load
Low input drive current High output drive current
Bidirectional capability Unidirectional capability
8. What are the advantages of EBL pattern generation? (Apr 2018)

Electron beam lithography (EBL) refers to a direct writing lithographic process that
uses a focused beam of electrons to form patterns by material modification, material
deposition (additive), or material removal (subtractive).
9. Write down equation- for describing the channel length modulation effect in
NMOS transistor (Nov 2017)
10. Define power reduction technique. (Nov 2017)

The effective ways of reducing power at the technological level is to reduce the
supply voltage, because the power consumption drops quadratically with the supply
voltage. However, lowering supply voltage results in reduction of performance; therefore,
any such voltage reduction must be balanced against any performance drop. To
compensate and maintain the same throughput, extra hardware can be added. This can
only be successful to the point where the additional circuitry does not diminish the
savings.

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11. Distinguish between nMOS and pMOS transistors based on structure. (Apr
2017)
12. Draw the stick diagram of a 3-input NAND gate. (Apr 2017)

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13. What are pull up to pull down ratios in CMOS inverter? (Dec 2016)
This type of logic is often called a ``ratioed logic'', since the ratio of the pull-
up resistance to the pull-down resistance effectively determines the voltage at which the
output of the device changes state. ... The depletion mode transistor must be made large
( i.e., long and thin) to create the large `òn'' resistance.
14. What are the four basic layers of MOS circuits? (Dec 2016)
Four basic layers-n-diffusion, p-diffusion, polysilicon, and metal, which are isolated
from one another by thick or thin (thinox) silicon one another by thick or thin (thinox)
silicon dioxide insulating layers.
15. Define photoresist layer. (Apr 2016)

A photoresist (also known simply as a resist) is a light-sensitive material used in several
processes, such as photolithography and photoengraving, to form a patterned coating on a
surface. This process is crucial in the electronic industry.
16. Expand CVD. (Apr 2016)

chemical vapour deposition is a process by which gases or vapors are chemically reacted,
leading to the formation of solids on a substrate. CVD can be used to deposit various
materials on a si substrate including poly si, SiO2 and Si3N4.
10 marks
1. Explain the static and dynamic power dissipation in CMOS circuits with
necessary diagrams and expressions. (Sep 2020, Apr 2018, Dec 2016, Apr 2016)
Power dissipation techniques

• Total Power dissipated in a CMOS circuit is sum total of dynamic power, short circuit power
and static or leakage power.
Figure 3.Components of Power in CMOS circuit

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Power and energy

• Power is drawn from a voltage source attached to the VDD pin(s) of a chip.
• Instantaneous Power:
• Energy:
• Average Power:
Dynamic power
Charging and discharging of load capacitances
o CMOS circuits dissipate power by charging the various load capacitances (mostly gate and
wire capacitance, but also drain and some source capacitances) whenever they are
switched.
o In one complete cycle of CMOS logic, current flows from V DD to the load capacitance to
charge it and then flows from the charged load capacitance (C L) to ground during
discharge.
o Therefore in one complete charge/discharge cycle, a total of Q=C LVDD is thus transferred
from VDD to ground. Multiply by the switching frequency on the load capacitances to get
the current used, and multiply by the average voltage again to get the characteristic
switching power dissipated by a CMOS device: P= 0.5CV2.
o Since most gates do not operate/switch at every clock cycle, they are often accompanied by
a factor , called the activity factor. Now, the dynamic power dissipation may be re-
written as P = αCV2f .
o A clock in a system has an activity factor α=1, since it rises and falls every cycle. Most data
has an activity factor of 0.1. [6] If correct load capacitance is estimated on a node together
with its activity factor, the dynamic power dissipation at that node can be calculated
effectively.
• Dynamic power is required to charge and discharge load capacitances when transistors switch.
• One cycle involves a rising and falling output.
• On rising output, charge Q = CVDD is required
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• On falling output, charge is dumped to GND

• This repeats Tfsw times over an interval of T
• Suppose the system clock frequency = f

• Let fsw = af,
where a = activity factor
• If the signal is a clock, a = 1
• If the signal switches once per cycle, a = ½
• Dynamic gates:
Switch either 0 or 2 times per cycle, a = ½
• Static gates:
Depends on design, but typically a = 0.1
• Dynamic power:
Short circuit current
• When transistors switch, both nMOS and pMOS networks may be momentarily ON at once
• Leads to a blip of “short circuit” current.
• < 10% of dynamic power if rise/fall times are comparable for input and output
Static power
Short-circuit power dissipation
• Since there is a finite rise/fall time for both pMOS and nMOS, during transition, for example,
from off to on, both the transistors will be on for a small period of time in which current will
find a path directly from VDD to ground, hence creating a short circuit current. Short circuit
power dissipation increases with rise and fall time of the transistors.
• An additional form of power consumption became significant in the 1990s as wires on chip
became narrower and the long wires became more resistive. CMOS gates at the end of those
resistive wires see slow input transitions. During the middle of these transitions, both the NMOS
and PMOS logic networks are partially conductive, and current flows directly from VDD to VSS.

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• The power thus used is called crowbar power. Careful design which avoids weakly driven long
skinny wires ameliorates this effect, but crowbar power can be a substantial part of dynamic
CMOS power.
• To speed up designs, manufacturers have switched to constructions that have lower voltage
thresholds but because of this a modern NMOS transistor with a V th of 200 mV has a
significant subthreshold leakage current. Designs (e.g. desktop processors) which include vast
numbers of circuits which are not actively switching still consume power because of this leakage
current.
• Leakage power is a significant portion of the total power consumed by such designs. Multi-
threshold CMOS (MTCMOS), now available from foundries, is one approach to managing
leakage power. With MTCMOS, high Vth transistors are used when switching speed is not
critical, while low Vth transistors are used in speed sensitive paths. Further technology advances
that use even thinner gate dielectrics have an additional leakage component because of
current tunnelling through the extremely thin gate dielectric. Using high-k dielectrics instead
of silicon dioxide that is the conventional gate dielectric allows similar device performance, but
with a thicker gate insulator, thus avoiding this current.
• Leakage power reduction using new material and system designs is critical to sustaining
scaling of CMOS
• Static power is consumed even when chip is quiescent.

• Ratioed circuits burn power in fight between ON transistors
• Leakage draws power from nominally OFF devices
2. Write the layout design rules and draw stick diagram and layout for four input
NOR gate? (Sep 2020,May 2019)
Stick diagram
Stick definition
• VLSI design aims to translate circuit concepts onto silicon.
• Stick diagrams are a means of capturing topography and layer information using simple
diagrams.

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• Stick diagrams convey layer information through colour codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and the actual layout
It shows
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics
• It shows relative placement of components.
• Goes one step closer to the layout
• Helps plan the layout and routing
Notations
P diffusion : Yellow/Brown Metal1 : Blue

N diffusion : Green Metal2 : Magenta/Purple
Polysilicon : Red Metal3 : Cyan/L.Blue
Contacts & Taps : Black
Stick rules
Rule 1
• When two or more ‘sticks’ of the same type cross or touch each other that represents electrical
contact.

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Rule 2
• When two or more ‘sticks’ of different type cross or touch each other there is no electrical
contact.
(If electrical contact is needed we have to show the connection explicitly).
Rule 3
• When a poly crosses diffusion it represents a transistor.
Rule 4
• In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must
lie on one side of the line and all nMOS will have to be on the other side.
CMOS NOR gate

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Layout design rules

• The process technology referred to the length of the silicon channel between the source and
drain terminals in field effect transistors.
• The sizes of other features are generally derived as a ratio of the channel length, where some
may be larger than the channel size and some smaller.
• For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the
gate terminal may be only 50 nm.
• Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry
in silicon
• Interface between circuit designer and fabrication engineer
• It Compromises the
designer - tighter, smaller
fabricator - controllable, reproducible
Design rules define ranges for features
Examples:
• min. wire widths to avoid breaks
• min. spacing to avoid shorts
• minimum overlaps to ensure complete overlaps
• Measured in microns
• Required for resolution/tolerances of masks
• Fabrication processes defined by minimum channel width
• Also minimum width of poly traces
• Defines “how fast” a fabrication process is
Two major approaches:
i) “Micron” rules: stated at micron resolution.
Rules: simplified micron rules with limited scaling attributes.
Design rules represents a tolerance which insures very high probability of correct
fabrication
ii) Scalable design rules: lambda parameter
Absolute dimensions (micron rules)
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Micron rules
• All minimum sizes and spacing specified in microns.
• Rules don't have to be multiples of λ.
• Can result in 50% reduction in area over λ based rules
• Standard in industry.
Lambda-based
• Lambda-based (scalable CMOS) design rules define scalable rules based on l (which is half of
the minimum channel length)
• classes of MOSIS SCMOS rules:
SUBMICRON
DEEPSUBMICRON
• Stick diagram is a draft of real layout, it serves as an abstract view between the schematic and
layout.
• Circuit designer in general want tighter, smaller layouts for improved performance and
decreased silicon area.
• On the other hand, the process engineer wants design rules that result in a controllable and
reproducible process.
• Generally we find there has to be a compromise for a competitive circuit to be produced at a
reasonable cost.
• All widths, spacing, and distances are written in the form l = 0.5 X minimum drawn transistor
length
• Design rules based on single parameter, λ
• Simple for the designer
• Wide acceptance
• Provide feature size independent way of setting out mask
• If design rules are obeyed, masks will produce working circuits
• Minimum feature size is defined as 2 λ
• Used to preserve topological features on a chip
• Prevents shorting, opens, contacts from slipping out of area to be contacted
Design rules reality
• Manufacturing processes have inherent limitations in accuracy and repeatability
• Design rules specify geometry of masks that provide reasonable yield
• Design rules are determined by experience
3. Mention the steps involved in basic CMOS fabrication process. Draw the cross-
sections while manufacturing the n-well process of CMOS fabrication. Explain.
(Nov 2019, Apr 2018, Apr 2016)
CMOS Fabrication
N-Well Process
The fabrication sequence consists of a sequence of steps in which the layers of the chip are
defined through a process called “photolithography”.
The process begins with the creation of an n-well on a bare p-type silicon wafer. Step wise
explanation for cmos fabrication is as follows

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Step 1: Si substrate
Start with p-type substrate, which is required to form n-well by adding dopants into the
silicon substrate
Step 2: Oxidation
Exposing to high-purity oxygen and hydrogen at approximately 1000 oC in oxidation furnace,

which causes Si and O2 to react and become SiO2 on the wafer surface
Step 3: Photoresist coating
Photoresist is a light-sensitive organic polymer which softens when exposed to light is spun
on to the wafer
Step 4: Masking
Expose photoresist through n-well mask that allows light to pass through only where the well
should be

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Step 5: Removal of photoresist
Photoresist are removed by treating the wafer with acidic or basic solution
Step 6: Acid etching
SiO2 is selectively removed from areas of the wafer that are not covered by photoresist by
using hydrofluoric acid
Step 7: Removal of photoresist
The remaining photoresist is stripped away using a mixture of acids
Step 8: Formation of n-well
The n-well is formed where the substrate is not covered with oxide using diffusion or ion
plantation method.

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Step 9: Removal of SiO2
The remaining oxide is stripped off with HF to leave the bare wafer with the wells in their
appropriate places.
Step 10 : Polysilicon deposition
Transistor gates are formed by depositing polysilicon over a thin layer of oxide. The thin
layer of gate oxide is formed using (CVD) Chemical Vapour Deposition process.
Step 11: N-diffusion
N-diffusion forms nMOS source, drain and well contact.

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Dopants were diffused or ion implanted
Strip off the remaining oxide
Step 12: P+diffusion
Similar steps of N-diffusion is followed to form P+diffusion for pMOS source,drain and
substrate contacts.
Step 13: Contact cuts

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The devices are to be wired together and then cover the chip with thick field oxide.Etch oxide
where contact cuts are needed.
The field oxide is grown to insulate the wafer from metal and patterned with the contact mask
toleave the contact cuts where metal should attach to diffusion or polysilicon.
Step 14: Metallization
Finally aluminium is sputtered over the entire wafer filling the contact cuts as well, where
sputtering involves blasting aluminium into a vapour that evenly coats the wafer.
The metal is patterned with the metal mask and plasma etched to remove metal everywhere
except where wires should remain.
4. Sketch the transistor-level diagram, stick diagram and layout diagram for n
CMOS gate function of Y =((A +B).(C+D)) (Nov 2019)

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5. Discuss about the different sources of power reduction techniques in CMOS.

(May 2019, Nov 2018, Apr 2018, Apr 2017)
INTRODCTION TO POWER REDUCTION TECHNIQUES:
Dynamic power reduction
Dynamic power dissipation is given by the following equation
(i) Reduction of power supply voltage (VDD)
VDD reduction is the most effective method for dynamic power minimization.
Although it is effective, reducing power supply voltage leads to an increase in delay
propagation i.e., decease of clock speed.
(ii) Reduction of operating frequency (FCLK)
Reducing operating frequency leads to the reduction of power dissipation but

continuous demand of increasing speed of data rate will not give useful results.
(iii) Reduction of activity factor (a)
Reducing activity factor leads to inductive noise in the power supply network
(iv) Reduction of load capacitance (CL)

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Another way is to reduce the load capacitance. Larger load capacitance draws more
charge from power supply during each switching and hence increases dynamic power
dissipation. Also larger capacitance reduces the speed of operation.
Therefore it is needed to reduce the load capacitance to reduce the dynamic power
dissipation.
Static power reduction
(i) Leakage current through reverse biased diodes
Leakage current should be within 0.1 nA to 0.5 nA. If it exceeds the range, then the
device parameters need to be reduced.
(ii) Subthreshold conduction
It takes place when the gate to source voltage is less than threshold voltage (V gs ≤ Vt).
To reduce this conduction, time window of Vgs ≤ Vt should be reduced and Vgs is made
greater than threshold voltage (Vgs ¿ Vt).
(iii) Tunneling current
To reduce tunneling current gate oxide should be made thicker.
6. Draw the stick diagram and layout of NAND and NOR gates. (Nov 2018)
CMOS NOR gate

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CMOS NAND gate

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7. With circuit diagram explain DC and transfer characteristics of a CMOS

Inverter with necessary conditions for different regions of operation (Nov 2017)
CMOS Inverter
CMOS Inverter
The cmos inverter shown in figure 10. is built using one n-mos transistor and one p-
mos transistor. When the input is 0, the n-mos transistor is off and the p-mos transistor is on.
Thus the output is pulled up to 1 because it is connected to Vdd but not to the GND. When
the input to the inverter is 1, then the n-mos transistor is on and the p-mos transistor is off and
the output is pulled down to 0.
DC Characteristics
The DC transfer characteristics of a circuit relate the output voltage to the input
voltage,
assuming the input changes slowly enough that capacitances have plenty of time to charge or
discharge. Specific ranges of input and output voltages are defined as valid 0 and 1 logic
levels.
The DC transfer function (Vout vs. Vin) for the static CMOS inverter is derived using the
Figure 10. Consider the following table 1. which outlines various regions of operation for the
n- and p-transistors.
Table :Relationship between voltages for the three regions of operation of a cmos
inverter

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In the above table, Vtn is the threshold voltage of the n-channel device,and V tp is the threshold
voltage of the p-channel device. Note that Vtp is negative.
As the source of the nMOS transistor is grounded,
Vgsn = Vin and Vdsn = Vout.
As the source of the pMOS transistor is tied to VDD,
Vgsp = Vin – VDD and Vdsp = Vout – VDD.
To find the variation in output voltage (V out) as a function of the input voltage (V in). Given
Vin, we must find Vout subject to the constraint that Idsn = |Idsp|. For simplicity, we assume Vtp =
–Vtn and that the pMOS transistor is 2–3 times as wide as the nMOS transistor so βn = βp.
 The plot in figure 11. (a) shows Idsn and Idsp in terms of Vdsn and Vdsp for various values
of Vgsn and Vgsp.
 The plot in figure 11. (b) shows the same plot of I dsn and |Idsp| now in terms of Vout for
various values of Vin. The possible operating points of the inverter, marked with dots,
are the values of Vout where Idsn = |Idsp| for a given value of Vin.
 The plot in figure 11.(c) shows the operating points plotted on V out vs. Vin axes to
show the inverter DC transfer characteristics.
 The plot in figure 11.(d) gives the supply current I DD = Idsn = |Idsp| is also plotted
against Vin showing that both transistors are momentarily ON as V in passes through
voltages between GND and VDD, resulting in a pulse of current drawn from the power

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supply.
Graphical representation of CMOS inverter DC characteristics
Regions of operation of CMOS inverter
The operations of CMOS inverter can be divided into five regions as shown in figure 11. (c).
Region A
The n MOS transistor is OFF so the p MOS transistor pulls the output to VDD.
Region B
The n MOS transistor starts to turn ON, pulling the output down
Region C
Both transistors are in saturation. Notice that ideal transistors are only in region C for V in =
VDD/2.
Region C
Real transistors have finite output resistances on account of channel length modulation and
have finite slopes over a broader in region C
Region D
The p MOS transistor is partially ON and in region E, it is completely OFF, leaving the n
MOS transistor to pull the output down to GND. Also notice that the inverter’s current

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consumption is ideally zero, neglecting leakage, when the input is within a threshold voltage
of the VDD or GND rails. This feature is important for low-power operation.
Table 2. Summary of cmos inverter operation
The state of each transistor in each region is shown in table 2.andthe figure shows simulation
results of an inverter DC characteristics from a 65 nm process.
Figure 12. Simulated CMOS inverter DC characteristics
 The p MOS transistor is twice as wide as the n MOS transistor to achieve

approximately equal betas.
 Simulation matches the simple models reasonably well, although the transition is not
quite as steep because transistors are not ideal current sources in saturation.
 The crossover point where Vinv = Vin = Vout is called the input threshold.
 Because both mobility and the magnitude of the threshold voltage decrease with
temperature for n MOS and p MOS transistors, the input threshold of the gate is only
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weakly sensitive to temperature.
8. Discuss Pull up and pull down ratio (Nov 2017)
DETERMINATION OF PULL-UP TO PULL-DOWN RATIOS
Consider the inverter which is driven from the output of another similar inverter and
consider depletion mode for which Vgs=0 under all conditions.
Figure 13. Cascaded inverters
Cascaded inverter without degradation should have V in = Vout = Vinv = 0.5VDD. At this point
the transistors are in saturation and
In the depletion mode
, since Vgs=0 ...(1)
and in the enhancement mode
, since Vgs=Vinv ...(2)
where, K is the process gain factor
L is the length of the transistor
W is the width of the transistor
Aspect ratio (A.R): It is the ratio of length of the transistor to width of the transistor

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Inverter ratio (Pull-up to pull-down ratio): It is the ratio of impedance of pull-up transistor
to the impedance of pull down transistor.
Since currents are same equating equation (1) and (2)
Where Wp.d, Lp.d, Wp.u, and Lp.u are the widths and lengths of the pull-down and pull-up
transistors respectively.
we have
hence
...(3)
On substituting the typical values as follows
(for equal margins)
Thus, from equation (3)
hence
=2

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and thus
=4/1
for an inverter directly driven by an inverter

b.) Discuss Propagation delay (Nov 2017)
PROPAGATION DELAY:
Propagation delay measures the speed of the output reaction to the change in the
input. It is obtained by the mean of fall propagation delay and rise propagation delay.
where tp is the propagation delay
tpf is the fall propagation delay
tpr is the rise propagation delay
For calculating propagation delay we need to find the rise time and fall time by considering
the following circuit shown in the figure.13
Figure 13. CMOS inverter for propagation delay
c.) Discuss Design rules and layout (Nov 2017)

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Layout Design Rules
 The physical mask layout of any circuit to be manufactured using a particular process
must conform to a set of geometric constraints or rules, which are generally called
layout design rules.
 These rules usually specify the minimum allowable line widths for physical objects
on-chip such as metal and polysilicon interconnects or diffusion areas, minimum
feature dimensions, and minimum allowable separations between two such features.
 If a metal line width is made too small, for example, it is possible for the line to break
during the fabrication process or afterwards, resulting in an open circuit.
 If two lines are placed too close to each other in the layout, they may form an
unwanted short circuit by merging during or after the fabrication process.
 The main objective of design rules is to achieve a high overall yield and reliability
while using the smallest possible silicon area, for any circuit to be manufactured with
a particular process.
 Note that there is usually a trade-off between higher yield which is obtained through
conservative geometries, and better area efficiency, which is obtained through
aggressive, high- density placement of various features on the chip.
 The layout design rules which are specified for a particular fabrication process
normally represent a reasonable optimum point in terms of yield and density.
 It must be emphasized, however, that the design rules do not represent strict
boundaries which separate "correct" designs from "incorrect" ones.
 A layout which violates some of the specified design rules may still result in an
operational circuit with reasonable yield, whereas another layout observing all
specified design rules may result in a circuit which is not functional and/or has very
low yield.
 To summarize, we can say, in general, that observing the layout design rules
significantly increases the probability of fabricating a successful product with high
yield.
d.) Discuss about Scaling (2) (Nov 2017)

SCALING :

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The size of the circuits in IC’s continues to increase. Proper scaling allows to shrink a
design. Technology scaling rate is approximately 13% per year, halving every 5 years.
Besides increasing the number of devices, scaling has had a profound impact on both speed
and power.
Scaling - Proportional adjustment of the dimensions of an electronic device while

maintaining the electrical properties of the device, results in a device either larger or
smaller than the un-scaled device
Scale the devices and wires down, Make the chips ‘fatter’ in functionality, intelligence,
memory. Make more chips per wafer – increased yield
Impact of scaling is characterized in terms of several indicators:
 Minimum feature size

 Number of gates on one chip
 Power dissipation
 Maximum operational frequency
 Die size
 Production cost
Full Scaling (Constant Electrical Field Scaling)
 In the ideal model, all the dimensions of the MOS devices, e.g., the voltage supply
level and depletion widths are scaled by the same factor S.
 Keeping the electric field patterns constant avoids breakdown and other secondary
effects.
 This leads to greater device density, higher speed and reduced power consumption.
Ron remains constant -- performance is improved because of the reduced capacitance.
 Circuit speed increases linearly while the power scales down quadratically. Both
clearly indicate the benefits of scaling
Dimensions are scaled by S while voltages are scaled by U.

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Fixed Voltage Scaling
 Full scaling is not a feasible option.

 For example, to keep new chips compatible with existing chips, voltages cannot be
scaled arbitrarily. Providing multiple voltage supplies is expensive.
 5V was used up through the early 90s. Voltages of 3.3 and 2.5 used since the
introduction of 0.5 µm.
 The change from a fixed-voltage scaling model to the general scaling model used
today can be justified by reviewing the rightmost column.
 In velocity saturated device, keeping the voltage constant while scaling the device
dimensions: Does not provide a performance advantage over full scaling model (1/S
vs. 1/S) But has a major power penalty associated with it (1/S2 vs 1).
 Note the gain of increased current level is offset by the higher voltage swing, which
only hurts power dissipation and this is very different from the situation when
transistors were operating in the long-channel mode.
 Here, current was a quadratic function of the voltage. In this scenario, keeping
voltage constant gave a performance advantage (net reduction in "on resistance" Other
reasons for scaling the supply voltage include hot-carrier effect and oxide breakdown.
 These latter reasons played a significant role in the trend we see today. Bear in mind
that this is a first order analysis, in reality, there is a (small) performance benefit with
fixed voltage due to, e.g., channel length modulation.

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 Supply voltage is now being scaled, but at a slower rate than feature size.
 For example, from 0.5 μm to 0.1 μm, supply voltage reduced from 5 V to 1.5V. Then
why not stick with full scaling model if there is no benefit to keeping the supply
voltage higher.
 Voltage scaling is limited since making it too low makes it difficult to turn off the
devices completely. This is aggravated by large process variations.
 A more general scaling model is needed, where dimensions and voltages are scaled
independently using S and U respectively. Under fixed voltage scaling, U = 1 as
shown in the last column of the table
General Scaling
 Under general scaling model, performance scenario is identical (1/S) to other models
but power dissipation lies between the two models, S > U > 1.
9. Explain the process parameters and considerations for PMOS fabrication (7)
(Apr 2017)
PMOS Fabrication :
Same steps are followed are followed in PMOS fabrication as in NMOS fabrication expect n-
substrate is used as wafer and p-type impurities are diffused into substrate to form source and
drain regions.
NMOS Fabrication
Step 1 : P substrate
Processing is carried on a thin wafer cut from a single crystal of silicon of high purity into
which the required p-impurities are introduced as the crystal is grown.
Step 2: Oxide layer
A layer of silicon dioxide is grown all over the surface of the wafer to protect the surface, act
as a barrier to dopants during processing and provide a insulating surface on to which other
layers may be deposited.
Y
Step 3: Photoresist layer
The surface is now covered with photoresist which is deposited on the wafer.
Step 4 : Wafer exposed to UV rays
The photoresist layer is then exposed to ultraviolet light through a mask which defines those
regions into which diffusion is to take place together with transistor channels.
Step 5 : Etching
The exposed areas are now etched away together with the underlying silicon dioxide so that
the wafer is exposed in the window defined by the mask.

Y
Step 6 : Thin layer of silicon dioxide
The remaining photoresist is removed and a thin layer of silicon dioxide is grown over the
entire chip surface and then polysilicon is deposited on top of this to form the gate structure.
Step 7 : n+ diffusion
Thin oxide layer is removed to expose areas into which n- type impurities are diffused to
form the source and drain regions.
Step 8 : Thick oxide is grown
Thick oxide is grown over all again and is then masked with photoresist and etched to expose
selected areas of the polysilicon gate and the drain and source areas where connections
(contact cuts) are to be made.
Step 9 : Metallization
The whole chip has then metal (aluminium) deposited over its surface to a thickness typically
of 1 µm. This metal layer is then masked and etched to form the required interconnection
pattern.

Y


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RAJIV GANDHI COLLEGE OF ENGINEERING AND TECHNOLOGY PUDUCHERR

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

6. What is meant by power dissipation? (Nov 2018)

7. Compare Bipolar and CMOS technology. (Apr 2018)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Low static power dissipation High power dissipation

8. What are the advantages of EBL pattern generation? (Apr 2018)

10. Define power reduction technique. (Nov 2017)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

15. Define photoresist layer. (Apr 2016)

16. Expand CVD. (Apr 2016)

Power dissipation techniques

Figure 3.Components of Power in CMOS circuit

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Power and energy

• On falling output, charge is dumped to GND

• Suppose the system clock frequency = f

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

• Static power is consumed even when chip is quiescent.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

• Acts as an interface between symbolic circuit and the actual layout

• Wire lengths, wire widths, tub boundaries.

• Any other low level details such as parasitics

• It shows relative placement of components.

• Goes one step closer to the layout

• Helps plan the layout and routing

P diffusion : Yellow/Brown Metal1 : Blue

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

• When a poly crosses diffusion it represents a transistor.

CMOS NOR gate

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Layout design rules

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Exposing to high-purity oxygen and hydrogen at approximately 1000 oC in oxidation furnace,

Step 3: Photoresist coating

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Step 5: Removal of photoresist

Step 6: Acid etching

Step 7: Removal of photoresist

The remaining photoresist is stripped away using a mixture of acids

Step 8: Formation of n-well

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Step 9: Removal of SiO2

Step 10 : Polysilicon deposition

Step 11: N-diffusion

N-diffusion forms nMOS source, drain and well contact.

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Dopants were diffused or ion implanted

Strip off the remaining oxide

Step 12: P+diffusion

Step 13: Contact cuts

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Step 14: Metallization

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

5. Discuss about the different sources of power reduction techniques in CMOS.

INTRODCTION TO POWER REDUCTION TECHNIQUES: