File: C:/My_Designs/Contador_ascendente_y_desendente_comn_carga_en_paralelo/asendente y de

1 ------------------------------------------------------------------------
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2 --
3 -- Title : contador
4 -- Design : asendente y desendente en paralelo
5 -- Author : kirito11134532@gmail.com
6 -- Company : ALPHAMECATRONICS
7 --
8 ------------------------------------------------------------------------
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9 --
10 -- File : c:\My_Designs\Contador_ascendente_y_desendente_comn_carga_en_paralel
endente y desendente en paralelo\src\contador.vhd
11 -- Generated : Tue Nov 14 01:39:22 2023
12 -- From : interface description file
13 -- By : Itf2Vhdl ver. 1.22
14 --
15 ------------------------------------------------------------------------
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16 --
17 -- Description :
18 --
19 ------------------------------------------------------------------------
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20
21 --{{ Section below this comment is automatically maintained
22 -- and may be overwritten
23 --{entity {contador} architecture {modulo}}
24
25 library IEEE;
26 use IEEE.std_logic_1164.all;
27
28 entity contador is
29 port(
30 clk : in STD_LOGIC;
31 LD : in STD_LOGIC;
32 UP : in STD_LOGIC;
33 D : in STD_LOGIC_VECTOR(3 downto 0);
34 Q : inout STD_LOGIC_VECTOR(3 downto 0)
35 );
36 end contador;
37
38 --}} End of automatically maintained section
39
40 architecture modulo of contador is
41 begin
42
43
44 process (clk,LD,D,UP)
45 begin
46
47 if(clk'event and clk='1') then
48 if( LD<='0') then
49 Q<= D;
50 ELSIF
51 UP ='1' THEN
52 Q<= Q + 1;
53 ELSE
54 Q<= Q-1;
55 end if;
56 end if;

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File: C:/My_Designs/Contador_ascendente_y_desendente_comn_carga_en_paralelo/asendente y de

57 end process;
58
59
60
61
62
63
64 -- enter your statements here --
65
66 end modulo;
67

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