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    Contador Utilizando Datos Tipo Entero Intege

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    sisissmashxd
    This document contains the VHDL code for an integer counter entity and architecture. The entity is called "cont" and has ports for a clock, reset, and an integer output called Q that counts from 0 to 15. The architecture "arq_cont" contains a process that increments Q by 1 each clock cycle unless the reset is asserted or Q reaches its maximum value of 15, in which case it is reset to 0.

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    Contador Utilizando Datos Tipo Entero Intege

    Uploaded by

    sisissmashxd
    1 views1 page
    This document contains the VHDL code for an integer counter entity and architecture. The entity is called "cont" and has ports for a clock, reset, and an integer output called Q that counts from 0 to 15. The architecture "arq_cont" contains a process that increments Q by 1 each clock cycle unless the reset is asserted or Q reaches its maximum value of 15, in which case it is reset to 0.

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    Original Title

    Contador_utilizando_datos_tipo_entero_intege

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    This document contains the VHDL code for an integer counter entity and architecture. The entity is called "cont" and has ports for a clock, reset, and an integer output called Q that counts from 0 to 15. The architecture "arq_cont" contains a process that increments Q by 1 each clock cycle unless the reset is asserted or Q reaches its maximum value of 15, in which case it is reset to 0.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    1 views1 page

    Contador Utilizando Datos Tipo Entero Intege

    Uploaded by

    sisissmashxd
    This document contains the VHDL code for an integer counter entity and architecture. The entity is called "cont" and has ports for a clock, reset, and an integer output called Q that counts from 0 to 15. The architecture "arq_cont" contains a process that increments Q by 1 each clock cycle unless the reset is asserted or Q reaches its maximum value of 15, in which case it is reset to 0.

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    © All Rights Reserved
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    of 1

    File: C:/My_Designs/Contador_utilizando_datos_tipo_entero_integer/integer/src/integer.

    vhd

    1 ------------------------------------------------------------------------
    -------
    2 --
    3 -- Title : cont
    4 -- Design : integer
    5 -- Author : kirito11134532@gmail.com
    6 -- Company : ALPHAMECATRONICS
    7 --
    8 ------------------------------------------------------------------------
    -------
    9 --
    10 -- File : c:\My_Designs\Contador_utilizando_datos_tipo_entero_integer\integer\
    integer.vhd
    11 -- Generated : Tue Nov 14 00:56:10 2023
    12 -- From : interface description file
    13 -- By : Itf2Vhdl ver. 1.22
    14 --
    15 ------------------------------------------------------------------------
    -------
    16 --
    17 -- Description :
    18 --
    19 ------------------------------------------------------------------------
    -------
    20
    21 --{{ Section below this comment is automatically maintained
    22 -- and may be overwritten
    23 --{entity {cont} architecture {arq_cont}}
    24
    25 library IEEE;
    26 use IEEE.std_logic_1164.all;
    27
    28 entity cont is
    29 port(
    30 clk : in STD_LOGIC;
    31 reset : in STD_LOGIC;
    32 Q : inout integer range 0 to 15
    33 );
    34 end cont;
    35
    36 architecture arq_cont of cont is
    37 begin
    38 process (clk,reset) begin
    39 if (clk'event and clk='1')then
    40 if (reset ='1' or Q=9) then
    41 Q<=0;
    42 else
    43 Q<= Q + 1;
    44 end if;
    45 end if;
    46 end process;
    47
    48
    49
    50
    51 end arq_cont;
    52

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