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    Contador

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    sisissmashxd
    This document contains the VHDL code for a 4-bit counter called Contador. The code defines the Contador entity with a clock, reset, and 4-bit output port. It contains an architecture Modulo that describes a process to increment the output on each clock edge unless reset is asserted, in which case it resets the output to 0000.

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    Contador

    Uploaded by

    sisissmashxd
    7 views1 page
    This document contains the VHDL code for a 4-bit counter called Contador. The code defines the Contador entity with a clock, reset, and 4-bit output port. It contains an architecture Modulo that describes a process to increment the output on each clock edge unless reset is asserted, in which case it resets the output to 0000.

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    This document contains the VHDL code for a 4-bit counter called Contador. The code defines the Contador entity with a clock, reset, and 4-bit output port. It contains an architecture Modulo that describes a process to increment the output on each clock edge unless reset is asserted, in which case it resets the output to 0000.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    7 views1 page

    Contador

    Uploaded by

    sisissmashxd
    This document contains the VHDL code for a 4-bit counter called Contador. The code defines the Contador entity with a clock, reset, and 4-bit output port. It contains an architecture Modulo that describes a process to increment the output on each clock edge unless reset is asserted, in which case it resets the output to 0000.

    Copyright:

    © All Rights Reserved
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    of 1

    File: C:/My_Designs/Contador/Contador/src/Contador.

    vhd

    1 ------------------------------------------------------------------------
    -------
    2 --
    3 -- Title : Contador
    4 -- Design : Contador
    5 -- Author : kirito11134532@gmail.com
    6 -- Company : ALPHAMECATRONICS
    7 --
    8 ------------------------------------------------------------------------
    -------
    9 --
    10 -- File : c:\My_Designs\Contador\Contador\src\Contador.vhd
    11 -- Generated : Mon Nov 13 23:25:30 2023
    12 -- From : interface description file
    13 -- By : Itf2Vhdl ver. 1.22
    14 --
    15 ------------------------------------------------------------------------
    -------
    16 --
    17 -- Description :
    18 --
    19 ------------------------------------------------------------------------
    -------
    20
    21 --{{ Section below this comment is automatically maintained
    22 -- and may be overwritten
    23 --{entity {Contador} architecture {Modulo}}
    24
    25 library IEEE;
    26 use IEEE.std_logic_1164.all;
    27
    28 entity Contador is
    29 port(
    30 clk,reset : in STD_LOGIC;
    31 q : inout STD_LOGIC_VECTOR(3 downto 0)
    32 );
    33 end Contador;
    34
    35 --}} End of automatically maintained section
    36
    37 architecture Modulo of Contador is
    38 begin
    39
    40 process (clk,reset)
    41 begin
    42 if (clk'event and clk='1') then
    43 if(reset ='1' or q="1001" ) then
    44 q<="0000";
    45 else
    46 q<=q+1;
    47 end if;
    48 end if;
    49 end process;
    50
    51
    52 end Modulo;
    53

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