2019 International Conference on Electrical, Computer and Communication Engineering (ECCE), 7-9 February, 2019
A Novel Single Phase Multilevel Inverter Topology
with Reduced Number of Switching
Elements and Optimum THD Performance
1
Md. Halim Mondol, 1†Shuvra Prokash Biswas, Md. Kamal Hosain, Mst. Fateha Samad and Md. Waliur
Rahman
Department of Electronics & Telecommunication Engineering, Rajshahi University of Engineering & Technology
Rajshahi-6204, Bangladesh
1
halimreza18@gmail.com, 1†shuvraprokash@gmail.com
Abstract— In this paper, a novel single phase multilevel
inverter with reduced number of switches is presented
which is named as Half-height neutral point clamped
(NPC) inverter. The proposed inverter consists of a
single DC voltage source, a full bridge cell, switching
devices, and power diodes which are half in number as
compared to conventional topology. Unipolar
modulation technique is used to generate switching
signals for the proposed inverter, that provides optimum
total harmonic distortion (THD) performance in both
output voltage and current. The offered inverter
topology is described with the help of a single-phase
eleven-level inverter. The simulation of the topology is
carried out through MATLAB/ Simulink. A comparison
of the proposed topology with conventional one is also
presented.
Keywords— Multilevel inverter, Half-height NPC inverter,
total harmonic distortion (THD), unipolar modulation technique
I. INTRODUCTION
Multilevel power converters are considered as voltage
synthesizers, in which a high output voltage is synthesized
from many separated smaller voltage levels [1]. Multilevel
power converter was primarily represented in 1975 [2]. The
general concept of multilevel converters introduces
utilization of a higher number of semiconductor switches to
perform the power conversion in small voltage steps
resulting primary advantage of high power quality, better
electromagnetic compatibility, lower harmonic components,
and lower switching losses [3].
The term multilevel was primarily started with the three-
level inverter and later it has been raised to N number of
levels. Normally, four different kinds of multilevel inverter
topologies are noticed which are: (a) Cascaded H-bridges
converter (CHB) (b) Diode clamped (DC) converter (c)
Flying capacitors (FC) converter and (d) Neutral point
clamped (NPC) converter [4]. An obvious disadvantage of
CHB topology is the requirement of large number of
separated voltage sources to supply each cell. The CHB
topology was chased by the DC converter that uses a bank of
series capacitors [5]. Furthermore, the FC converter, includes
series connected capacitor-clamped switching cells [5]. This
topology has several attractive and indifferent characteristics
comparing to the DC inverter. For instance, the additional
978-1-5386-9111-3/19/$31.00 ©2019 IEEE
clamping diodes are not required for FC converter.
Moreover, the flying capacitor inverter has switching
luxuriance within the phase that can be used to balance the
flying capacitors and to require only one dc source [6].
However, the multilevel concept has mainly been arisen
to generate an AC voltage using small DC voltage levels
with better THD performances and lower losses. THD
mainly depends on the degree of the level of the inverter and
controlling technique of the switching devices. By efficient
control scheme and by increasing the level of the output
waveform, THD can be minimized. In order to increase the
level of the output voltage, the above mentioned topologies
require a huge number of switching devices, isolated dc
voltage sources, power diodes, and auxiliary capacitors
which make the inverter bulky. Hence, the toughest
challenge is to design the multilevel inverter with optimum
THD performance, lower losses, small in size, and lower
number of components. In recent years, several topologies
with reduced number of switches and sources have been
proposed in [7], [8].
In this paper, a new topology of multilevel inverter has
been proposed with reduced number of components
including dc voltage sources, switches, power diodes, and
dc bus capacitors which make the inverter smaller in size,
light in weight. It also reduces the losses and increases the
efficiency. The proposed inverter involves half of the
number of components as compared to the NPC topology to
generate equal number of voltage levels. Hence it can be
named as half-height NPC inverter. The unipolar
modulation technique has also been used to generate the
gate driving signals which provides optimum THD
performance for both output voltage and current.
The organization of this paper is as follows: The
proposed inverter topology is described in section II. The
performance analysis of the proposed inverter is represented
in section III. The comparison with the existing topologies is
shown in section IV. Finally, section V concludes the paper.
II. PROPOSED INVERTER TOPOLOGY
The configuration of the proposed inverter topology is
introduced in this section. The working principle of the
inverter is explained with the help of a single-phase eleven-
level inverter. The mathematical expressions for output
voltage levels, number of switches, number of power diodes
and number of dc bus capacitors are also presented.
A. Generalized Configuration of Inverter section III, the output voltage waveforms and current
The generalized single-phase structure of the proposed waveforms with the frequency spectrums of 21-level, 29-
topology is shown in Fig. 1. It presents the number of level and 37-level inverter have been presented from which
components required for any particular level of inverter. In the benefits of the unipolar switching scheme can be
Fig. 1, it is shown that only one dc voltage source is needed realized.
to design N level of inverter. This dc voltage is divided into Vref Vc(m-1)/2
m numbers of small dc voltage levels using dc bus Vc1
capacitors, where m determines the number of the output
voltage level. The generalized topology also consists of a
full bridge section with the load.

C (m-1)/2 S(m+7)/2
D(m-3)/2

S(m+7)/ 2

Switching Signals
C3 S7

D2 S5
VDC

C2 S6
S1, S4
D1

C1 S5 S2, S3
S2 S1

Fig. 2. Switching signals generation technique of m-level proposed

inverter topology.
Load
S4 S3

C. Operating Principle of the Proposed Topology

Fig. 1. Generalized single-phase structure of the proposed topology.
Hence, the number of dc bus capacitors required for m-
level inverter is,
m-1
Nc = (1)
2 2kVDC
The number of switches required for m-level inverter is,
m +7
Ns = (2)
2
The number of power diodes needed for m-level inverter is,
m−3
ND = (3)
2
B. Generation of Switching Signals
In Fig. 2 the method of generating switching signals is
shown using unipolar modulation technique. Here, level
shifted carrier signals are compared with a unipolar
reference signal resulting in gate drive signals. The lower
carrier signal is used to generate switching signal of S5
switch and the upper carrier signal is used to generate
switching signal for the last switch at the top. Each switch
requires individual carrier signal to generate switching pulse
for itself. Thus, gate drive signals are generated using
unipolar modulation technique. For using unipolar switching
scheme, the proposed inverter provides optimum THD
performance in both output voltage and current, hence
reduces conduction losses and increases efficiency. In
The operating principle of the proposed inverter
topology is described here with the help of an eleven-level
inverter. By connecting the dc bus capacitors with the dc
voltage source in series, the input dc voltage is divided into
five small dc voltage levels. The generalized formula for the
determination of each output voltage level of the inverter is:
Vk = (4)
m −1
where, VDC is the DC source voltage and k = 0, ±1, ±2, …
m-1
± . Thus, during the on state of every single switch
2
connected with the dc bus capacitor, a small dc voltage level
VDC
is produced with a value equal to . The individual
5
output voltage level with corresponding switching state is
summarized in Table I. Table I clearly shows the entire
operation of eleven-level proposed inverter.
During the positive half cycle, S1 and S4 switches are
always ON state; and, S2 and S3 switches are OFF state.
Hence, output voltage is considered as positive. At the time
of negative half cycle, S2 and S3 switches are always ON
state; and S1 and S4 are OFF state. So, the output voltage is
negative. Finally, applying gate driver signals to the
remaining switches, small dc voltage levels are generated.
During both positive and negative half cycle same voltage
levels are generated. S1, S2, S3 and S4 switches determine
whether the output voltage will be positive or negative.
 TABLE I. SWITCHING STATES WITH CORRESPONDING inverter, the THD of CHB, DC, FC, NPC and proposed are
VOLTAGE LEVELS 6.57%, 6.37%, 6.14%, 5.95% and 2.87% respectively.
Output Voltage Switching state (ON=1, OFF=0) Finally, 5.05%, 4.89%, 4.72%, 4.47% and 2.25% THDs are
provided by CHB, DC, FC, NPC and proposed inverters
S1 S2 S3 S4 S5 S6 S7 S8 S9 respectively. Hence the presented scheme leads to lower
losses and higher efficiency.
V5=VDC 1 0 0 1 1 1 1 1 1

V4=4VDC/5 1 0 0 1 1 1 1 1 0

V3=3VDC/5 1 0 0 1 1 1 1 0 0

V2=2VDC/5 1 0 0 1 1 1 0 0 0

V1=VDC/5 1 0 0 1 1 0 0 0 0

V0=0 0 0 0 0 0 0 0 0 0 (a) (b)

Fig. 4. The output waveforms of 29-level proposed inverter. (a) Output
V-1=-VDC/5 0 1 1 0 1 0 0 0 0 voltage, (b) Output current.
V-2=-2VDC/5 0 1 1 0 1 1 0 0 0

V-3=-3VDC/5 0 1 1 0 1 1 1 0 0

V-4=-4VDC/5 0 1 1 0 1 1 1 1 0

V-5=-VDC 0 1 1 0 1 1 1 1 1

III. PERFORMANCE ANALYSIS OF THE PROPOSED

INVERTER (a) (b)
In order to analyze the performances of the proposed Fig. 5. The output waveforms of 37-level proposed inverter. (a) Output
inverter topology, three different levels including 21-level, voltage, (b) Output current.
29-level and 37-level inverters have been simulated with
MATLAB/Simulink software. The value of the dc voltage
source is considered as 400V. The value of the switching
frequency fs is used as 10 kHz. In Fig. 3, Fig. 4 and Fig. 5
the simulated waveforms of output voltage and current for
21-level, 29-level and 37-level inverters are presented. Fig.
3, Fig. 4 and Fig. 5 show that with the increase of the output
voltage level, the entire output voltage waveform progresses
to pure sinewave. That is the 37-level inverter shows the
best output waveforms among these three particular level
(a) (b)
inverters.
Fig. 6. Harmonic spectrums of 21-level proposed inverter. (a) Harmonic
spectrum of output voltage, (b) Harmonic spectrum of output current.

(a) (b)
Fig. 3. The output waveforms of 21-level inverter. (a) Output voltage, (b)
Output current. (a) (b)
Fig. 7. Harmonic spectrums of 29-level proposed inverter. (a) Harmonic
The harmonic spectrums of the output voltage and spectrum of output voltage, (b) Harmonic spectrum of output current.
current waveforms of 21-level, 29-level, and 37-level
inverters are shown in Fig. 6, Fig. 7 and Fig. 8. From these
figures, it is obvious that the number of levels of the output
voltage increases, the value of the THD decreases.
Furthermore, the offered inverter topology provides better
THD performance than the existing topologies for same
number of level. In 21-level inverter, the CHB, DC, FC,
NPC and proposed inverters provide 7.70%, 7.58%, 7.28%,
7.07% and 3.93% THD respectively. Again in 29-level
 voltage source. The requirement of the total number of
power diodes and dc bus capacitors in the proposed
topology is also reduced. Thus, the size of the proposed
inverter becomes smaller and the weight becomes lighter.
As a result, the losses decreases and the efficiency increase.
The proposed inverter also shows optimum THD
performance over all the conventional multilevel topologies.
Table II represents the comparison in performance between
the proposed topology and existing topologies. It is
(a) (b) concluded from Table II that the proposed topology shows
Fig. 8. Harmonic spectrums of 37-level proposed inverter. (a) Output better performances than the existing topologies in terms of
voltage harmonic spectrum, (b) Output current harmonic spectrum.
all parameters.
V. CONCLUSION
IV. COMPARISON WITH EXISTING TOPOLOGIES
In this work, a multilevel inverter topology is proposed.
All the existing conventional topologies (e. g. CHB, DC,
The presented inverter has many advantages: (i) it requires
FC, NPC) require a large number of components including
lower number of switches, (ii) the size of the inverter is
switches, power diodes, dc voltage sources and dc bus
smaller and it weight is light, (iii) it shows low THD
capacitors. For example, 14 switches are needed for 21-level
performance, (iv) it offers higher efficiency and lower
proposed inverter whereas 40 switches are required to
losses. Hence, the proposed inverter is suitable for medium
design the same level inverter for all the existing topologies
and high voltage applications including grid integrated
as described earlier. Similarly, 18 and 22 switches are
distributed generation system, photovoltaic power system
needed to design 29-level and 37-level proposed inverter
and hybrid micro-grids. Using the concept of this topology,
whereas 56 and 72 switches are required for all the existing
three phase multilevel inverter can be designed with lower
topologies to design 29-level and 37-level inverters. Again,
complexity in the future.
the number of power diodes required for DC topology in 37-
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Hence, considering all of the issues, the proposed inverter is

designed with lower number of switches and a single DC