Dinesh Spicer Sham S

Design Verification Engineer

E-mail ID: spicersham97@gmail.com Mobile No:9606420408

Linkedin ID: www.linkedin.com/in/dinesh-spicer-sham-s-22b0b81a5/
EXPERIENCE SUMMARY
• Internship experience of 2 months at Entuple Technologies.

• Worked at AARK IC Technologies for 6 months.

• Currently working as Design Verification Engineer-I with Smartsoc Solutions from July 2022.
PROFESSIONAL SUMMARY
• 2 years of experience in Design Verification.
• Strong Knowledge on Verilog, System Verilog Constructs and OOPs concepts.
• Knowledge on UVM.
• Knowledge on python Scripting
• Strong knowledge on APB,AHB, AXI and SPI protocols.

TECHNICAL SKILLS:

• HDVL Known: System Verilog.

• HDL: Verilog.
• Testbench Methodology: UVM
• EDA tool: Synopsys VCS, Cadence, Questa sim.
• Programming Language: C/C++, Python.
• Protocol Knowledge: SPI, APB,AHB, AXI.

PROJECT DETAILS

1. Project Name: Verification of memory wrapper IP

Client: Scalinx Duration: May 2023-Till date
Summary: The purpose of the wrapper is to integrate all the capabilities of a memory cell inside a wrapper.
We have designed the testbench from the scratch. My role is to generate the test case and the sequence for
all the memory cells. We have used Advanced bus peripheral protocol (APB) VIP to do Write and Read
data from the wrapper. I have verified the registers which is responsible for different access policy using
RAL environment. In this project, I have analyzed the RTL and verified DUT using the UVM Testbench
Environment on Cadence Xcelium tool.

Roles and Responsibilities:

• Understood the Testbench architecture of the IP especially about the memory cells present in the Memory
Wrapper.
• To check the latency of the different Cells test cases
• Gone through the specs sheet and understood the functionalities as well as verified the using UVM test
Bench.
• Enhanced TB environment for its feature verification Enhanced the RAL access policies in the RAL
sequence.

2. Project Name: SCM subsystem register verification.

Client: AMD Duration: Dec 2022 – May 2023
Summary: SCM project involve memory subsystem verification. My role is to verify the register access
for each block. Register verification is done using RAL. Register are access using the SPI protocol. In this
project, I have analyzed the RTL and verified the DUT using the UVM TB Environment on the Synopsys
VCS tool. The key features include verification of data transfer in various modes, MOSI line, MISO line,
 Serial Clock and Slave Select line.

Roles and Responsibilities:

• Understood the architecture and Data flow in the SoC from Processor to various IPs, especially the SPI
Block via the Interface Bridges.
• Gone through the Specs Sheet and understood the various functionalities.
• Prepared the Test Plan consisting of all the features to be verified with their description.
• Enhanced the TB environment for its feature verification.
• Implemented the RAL model for SPI Registers and verified the register READ and WRITE accesses.

3. Project Name: Verification of RAM using Advanced Peripheral Bus (APB) using UVM.
Client: Internal R&D project Duration: Nov 2022-Dec 2022
Summary: The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture
(AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power consumption
and reduced interface complexity. The APB protocol relates a signal transition to the rising edge of the
clock, to simplify the integration of APB peripherals into any design flow.

Roles and Responsibilities:

• Created Verification Plan and architected the System Verilog based Environment.
• Created the test plan for APB.
• Created an APB master Environment including Driver, Monitor, and Scoreboard from the Scratch.
• Verified the APBs protocol by integrating the single master (BFM) and slave (DUT).

3. Project Name: Verification of Memory using Advanced eXtensible Interface (AXI Memory) using UVM.
Client: Internal project Duration: July2022-Oct 2022
Summary: The Advanced eXtensible Interface (AXI), is an on-chip communication bus protocol
developed by ARM. It is part of the Advanced Microcontroller Bus Architecture 3 (AXI3) and 4 (AXI4)
specifications. The AXI is a point-to-point interconnect that designed for high-performance, high-speed
microcontroller systems. The AXI protocol is based on a point-to-point interconnect to avoid bus sharing
and therefore allow higher bandwidth and lower latency.
Roles and Responsibilities:
• Created Verification Plan and architected the System Verilog based Environment.
• Created the test plan for AXI-3.
• Created an AXI master Environment including Driver, Monitor, and Scoreboard from the Scratch.
• Verified the AXI-3 protocol by integrating the single master (BFM) and slave (DUT).

4.Verification of Advanced High-speed Bus Memory (AHB-Memory) using UVM.

Client: Internal Project Duration: Feb 2022-June 2022
Summary: AHB bus is intended to address the requirements of high-performance synthesizable designs.
AMBA AHB supports features like Burst transfers, Split transactions etc.
Roles and Responsibilities:
• Created Verification Plan and architected the UVM based Environment.
• AHB protocol was verified in UVM for both basic and burst transfers.
• Verified the AHB protocol by integrating the single master and slave (DUT).
• Created Scenarios to verify the basic and burst transactions.

5. Project Name: APB VIP Development using UVM.

Client: Training project
Summary: APB bus is a part of the ARM AMBA family intended for interfacing low speed peripherals
with the processor.
Roles and Responsibilities:
• Created Verification Plan and architected the System Verilog based Environment.
 • Created the test plan for APB.
• Created an APB master Environment including Driver, Monitor, and Scoreboard from the Scratch.
• Verified the APB protocol by integrating the single master (BFM) and slave (DUT).

EDUCATION QUALIFICATIONS
1. Nitte Meenakshi Institute of Technology, Bangalore
Master of Technology in VLSI Design and Embedded Systems
CGPA:8.97
2. Dr. T Thimmaiah Institute of Technology, Kolar Gold Fields
Bachelor of Engineering in Electronics and Communications
CGPA: 7.1

PERSONAL STRENGTHS

• Can learn things quickly.

• Can be a good Team Leader
• Leadership quality and self-motivated.
• Flexible and adaptability.
• Hard working to complete the tasks assigned to me.
• Proficiency in the use of various computer packages

HOBBIES AND INTERESTS: Playing Piano, Gym, Playing Cricket and chess, Photography.

DECLARATION

I hereby declare that above furnished information and the particulars are true and correct to the best of my
knowledge and belief.

Place: Bangalore Yours Faithfully

DATE: (DINESH SPICER SHAM S)