Cmpe 30094 Logic Circuits and Design Instructional Materials Version 2.02

MODULE 1 – Introduction to Digital System
Introduction
In the modern world of electronics, the term Digital is generally associated with a computer
because the term Digital is derived from the way computers perform operation, by counting
digits. For many years, the application of digital electronics was only in the computer system.
But now-a-days, digital electronics is used in many other applications. Following are some of
the examples in which Digital electronics is heavily used:
 Industrial process control
 Military system
 Television
 Communication system
 Medical equipment
 Radar
 Navigation
Learning Objectives
After successful completion of this module, you should be able to:
 identify the importance of signal domains
 describe what is a digital system,
 differentiate analog signal from digital signal
 discuss the characteristics of an analog signal and a digital signal,
 identify the advantages and disadvantages of an analog signal
 discuss the advantages and disadvantages of a digital signal.
Course Materials:
Signal
Signal can be defined as a physical quantity, which contains some information. It is a function
of one or more than one independent variables. Signals are of two types.
 Analog Signal
 Digital Signal
Analog Signal
An analog signal is defined as the signal having continuous values. Analog signal can have
infinite number of different values. In real world scenario, most of the things observed in
nature are analog. Examples of the analog signals are following.
 Temperature
 Pressure
 Distance
 Sound
 Voltage
 Current
 Power
Analog Signal (Temperature)
Figure 1. Graphical representation of an analog signal

The circuits that process the analog signals are called as analog circuits or system. Examples
of the analog system are following.
 Filter
 Amplifiers
 Television receiver
 Motor speed controller
Disadvantage of Analog Systems

 Less accuracy
 Less versatility
 More noise effect
 More distortion
 More effect of weather
Digital Signal
A digital signal is defined as the signal which has only a finite number of distinct values.
Digital signals are not continuous signals. In the digital electronic calculator, the input is given
with the help of switches. This input is converted into electrical signal which have two discrete
values or levels. One of these may be called low level and another is called high level. The
signal will always be one of the two levels. This type of signal is called digital signal. Examples
of the digital signal are following.
 Binary Signal
 Octal Signal
 Hexadecimal Signal
A Digital Signal (Binary)
Figure 2. Graphical representation of digital signal
The circuits that process the digital signals are called digital systems or digital circuits.
Examples of the digital systems are following.
 Registers
 Flip-flop
 Counters
 Microprocessors
Advantage of Digital Systems

 More accuracy
 More versatility
 Less distortion
 Easy communicate
 Possible storage of information
The table below shows the comparison of Analog and Digital Signal.
Table 1. Comparison between analog and digital signals

Analog Signal Digital Signal
1 Analog signal has infinite values. Digital signal has a finite number of
values.
2 Analog signal has a continuous nature. Digital signal has a discrete

nature.
3 Analog signal is generated by transducers and Digital signal is generated by A to

signal generators. D converter.
4 Example of analog signal − sine wave, triangular Example of digital signal − binary
waves. signal.
Digitization/Quantization of Analog Signals

• Since the world around us is analog, and processing of digital parameters is much
easier, is it is fairly common to convert analog parameters (or signals) into a digital
form in order to allow for efficient transmission and processing of these parameters
(or signals)
• To convert an Analog signal into a digital one, some loss of accuracy is inevitable
since digital systems can only represent a finite discrete set of values.
• The process of conversion is known as Digitization or Quantization.
• Analog-to-digital-converters (ADC) are used to produce a digitized version of analog
signals.
• Digital-to-analog-converters (DAC) are used to regenerate analog signals from their
digitized form.
• A typical system consists of an ADC to convert analog signals into digital ones to be
processed by a digital system which produces results in digital form which is then
transformed back to analog form through a DAC.
Figure 3. Block diagram of Analog Digitalization
• In this module, we will only be studying digital hardware design concepts, where
both the input and output signals are digital signals.
Digitization Example
• As an example, consider digitizing the shown voltage signal assuming that the
digitized version allowed set of discrete voltages is {V1, V2, V3, V4}.
• Analog signal values are mapped to the closest allowed discrete voltage ∈ {V1, V2,
V3, V4} as shown in Figure 3 below.
Figure 4. The resulting digitalized waveform

Information Representation
How Do Computers Represent Values (e.g. V1, V2, V3, V4)?
1. Using Electrical Voltages (Semiconductor Processor, or Memory)
2. Using Magnetism (Hard Disks, Floppies, etc.)
3. Using Optical Means (Laser Disks, e.g. CD’s)
Consider the case where values are represented by voltage signals:

• Each signal represents a digit in some Number System
• If the Decimal Number System is used, each signal should be capable of
representing one of 10 possible digits (0-to-9)
• If the Binary Number System is used, each signal should be capable of representing
only one of 2 possible digits (0 or 1).
• Digital computers, typically use low power supply voltages to power internal signals,
e.g. 5 volts, 3.3 volts, 2.5 volts, etc.
• The voltage level of a signal may be anywhere between the 0 voltage level (Ground)
and the power supply voltage level (5 volts, 3.3 volts, 2.5 volts, etc.)
• Thus, for a power supply voltage of 5 volts, internal voltage signals may have any
voltage value between 0 and 5 volts.
• Using a decimal number system would mean that each signal should be capable
of representing 10 possible digits (0-to-9).
• With 5 volt range signals, the 10 digits of the decimal system are represented with
each digit having a range of only 0.5 a volt
• If, however, a binary number system is used only 2 digits {0, 1} need to be
represented by a signal, allowing much higher Voltage range of 5 volts between the
2 binary digits.
Figure 5. Decimal System and Binary System Equivalency diagram
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The Noise Factor
• Typically, lots of noise signals exist in most environments.
• Noise may cause the voltage level of a signal (which represents some digit value) to
be changed (either higher or lower) which leads to misinterpretation of the value this
signal represents.
Sender Receiver
Noise
Figure 6. Noise interference of signal from sender to receiver
• Good designs should guard against noisy environments to prevent misinterpretation

of the signal information.
• Q. Which is more reliable for data transmission; binary signals or decimal signals?
• A. Binary Signals are more reliable.
• Q. Why?
• A. The Larger the gap between voltage levels, the more reliable the system is. Thus,
a signal representing a binary digit will be transmitted more reliably compared to a
signal which represents a decimal digit.
• For example, with 0.25V noise level using a decimal system at 5V power supply is
totally unreliable
SUMMARY
• Information can be represented either in an analog form or in a digital form.
• Due to noise, it is more reliable to transmit information in a digital form rather than an analog
one.
• Processing of digitally represented information is much more reliable, flexible and powerful.
• Today’s powerful computers use digital techniques and circuitry.
• Because of its high reliability and simplicity, the binary representation of information is most
commonly used.
• The coming lessons in this module will discuss how numbers are represented and manipulated
in digital system.
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SELF-ASSESSMENT #1
MULTIPLE CHOICE TYPE. Select the best answer. Check your answer against the answers given in the answer
key portion at the back of this instructional materials.
1. Digital circuitry is the foundation of digital computers and many automated control systems.
True
False
2. Digital systems operate only on discrete digits that represent numbers, letters, or symbols
True
False
3. Greater accuracy and precision are possible with digital techniques.
True
False
4. A digital quantity has a discrete set of values.
True
False
5. The real world is mainly analog.
True
False
6. Temperature variation is normally a digital quantity.
True
False
7. A good example of the use of a digital representation of an analog quantity is the audio
recording of music.
True
False
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8. Which of the following statements does NOT describe an advantage of digital
technology?
The values may vary over a continuous range.

The circuits are less affected by noise.
The operation can be programmed.
Information storage is easy.
9. What is a digital-to-analog converter?
It takes the digital information from an audio CD and converts it to a usable form.
It allows the use of cheaper analog techniques, which are always simpler.
It stores digital data on a hard drive.
It converts direct current to alternating current.
10.Digital representations of numerical values of quantities may BEST be

described as having characteristics:
that vary in discrete steps in proportion to the values they represent.

that are difficult to interpret because they are continuously changing.
that vary constantly over a continuous range of values.
that vary in constant and direct proportion to the values they represent.
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Module 2 - Number System
Introduction
A digital system can understand positional number system only where there are a few symbols
called digits and these symbols represent different values depending on the position they occupy
in the number.
A value of each digit in a number can be determined using
 The digit
 The position of the digit in the number
 The base of the number system (where base is defined as the total number of digits
available in the number system).
Learning Objectives
 understand how integers and fractional numbers are represented in binary
 explore the relationship between decimal number system and number systems of other
bases (binary, octal, hexadecimal)
 understand signed numbers and unsigned numbers
 understand number representations in two’s complement
 perform arithmetic operations in every base
 understand the method of floating point number representation in IEEE format
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Course Materials:
Binary Numbers and Arithmetic

In order to perform functions such as comparison and arithmetic, it is necessary to represent
numbers in binary. This module introduces binary numbers, outlines their relationship with the
decimal number system and proceeds to introduce binary arithmetic. The decimal number system
is reviewed first to help understand the structure of other number systems.
Decimal Number System

It is not surprising that human anatomy helps describe the most common number system used
today. A human hand is characterized by four fingers and a thumb, thus this gives a range of ten
numbers from 0 to 9. This does not mean however that we are limited to a scale of ten numbers,
as the position of these numbers can be used to indicate their magnitude and thus can be assigned
a weight.
10n ….. 102 101 100  10-1 10-2 ….. 10-n
Decimal point
For example:
3410 = 30 + 4
3 4
4 * 100 = 4
3 * 101= 30
Sum=3410
As can be seen, the number 3 has a weighting of 10 (101) due to its position and the number 4 has
a weighting of 1 (100) due to its position
For example:
123.4510 = 100 + 20 + 3 + (4/10) + (5/100)
= (1 * 102) + (2 * 101) + (3 * 100) + (4 * 10-1) + (5 * 10-2)
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Note, a number with a subscript of 10 (i.e. Base 10) indicates that this is a decimal number.
However, decimal is the default number system, so usually the subscript is not included for decimal
numbers.
Binary Number System
The binary system has two symbols. This is just another way of counting, and it is less complicated
than decimal as it is composed of only two binary digits (bits), 0 and 1. Counting in binary is very
similar to counting in decimal. As previously stated, the decimal system only contains ten digits in
total but this does not limit us to counting only from 0 to 9. When the number 9 is reached, another
column (to the left) is started and the counting continues from 10 to 99, where the process is
repeated.
COUNT DECIMAL BINARY
zero 0 02
one 1 12
two 2 102
three 3 112
four 4 1002
five 5 1012
six 6 1102
seven 7 1112
eight 8 10002
nine 9 10012
ten 10 10102
eleven 11 10112
twelve 12 11002
thirteen 13 11012
fourteen 14 11102
fifteen 15 11112
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As can be seen from the table above, it takes four bits to count sixteen decimal numbers. A simple
formula is used to calculate how far it is possible to count with n bits, i.e. 2n-1, where n is the number
of bits available.
For Example: n=4
24-1 = 16 - 1
= 15
Therefore, it is possible to count to the decimal number fifteen with four binary digits. To count to
sixteen a fifth binary digit (bit) is needed.
Computers use binary numbers to select memory locations. Each location is assigned a unique
number (called an address). The Pentium Microprocessor has 32 address lines, which means it
has 232 = 4,294,967,296 unique locations.
Binary to Decimal conversion

Like the decimal number system, the binary number system is also a weighted system, i.e. the
position of a 1 or a 0 indicates its weighting. Using the weighted system, any binary number can
be divided into parts that are to the power of two. Then, using their weighting the binary number
can be converted to decimal.
Ex 1: Convert the binary number 10012 to a decimal number. [910]
Ex 2: Convert the binary number 1110112 to a decimal number. [5910]
Binary Representation of Fractional Numbers
The above examples are whole numbers, but fractional numbers can also be represented in binary
by placing bits to the right of the binary point.
2n ….. 22 21 20  2-1 2-2 ….. 2-n
Binary point
All bits to the left of the binary point have weights that are positive powers of 2 and all to the right
have weights that are negative powers of two, i.e. fractional weights:
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2-1 = 1/21 = 1/2
2-2 = 1/22 = 1/4
2-3 = 1/23 = 1/8
2-4 = 1/24 = 1/16
The same process is used when converting decimal fractions.
Ex 3: Convert the binary number 0.11012 to a decimal number. [0.812510]
Ex 4: Convert the binary number 11001.0112 to a decimal number. [25.37510]
Alternative method of converting Binary fractions into decimal numbers
If we ignore the decimal point and convert the binary number into a decimal number, then we know
how many binary digits there are. Thus we know how many possible combinations there are.
Dividing these two numbers we obtain the decimal fraction. Repeating Ex. 3 will illustrate the point:
 Convert the binary number 0.11012 into a decimal number.
 Ignoring the decimal point, we have the binary number 1101 2. This translates (via above
methods) into the decimal number 13 10. There are four binary digits in this number, this
implies that there are 24=16 possible combinations.
 Dividing 1310 by the total number of combinations, we obtain 13/16=0.8125 which is the
same as in the last calculation.
0.11012 = 0.812510
Decimal to Binary conversion
We can also convert a decimal number into a binary number by a successive division process. The
decimal number is divided continuously by 2 and the remainders indicate the equivalent binary
number. The binary number is read from the last remainder upwards to the first.
Ex 5: Convert the decimal number 123 to a binary number
[11110112]
14
Ex 6: Convert the decimal number 79 to a binary number.
[10011112]
Ex 7: Convert the decimal number 46 to a binary number.
[1011102]
The procedure is a little more complicated when we have a decimal number that has digits attached
to the right of the decimal point. The successive division method is used for those digits to the left
of the decimal point, as before. However, the digits to the right of the decimal point undergo a
different transformation. Instead of being divided continuously by two, they are multiplied
continuously by two. This happens until there are no numbers to the right of the decimal point. The
binary number is read from the first carry to the last carry.
Ex 8: Convert the decimal number 0.75 to binary. [0.1102]
If in doubt, you can verify your answer easily by doing a binary to decimal conversion.
For Ex 8,
0.112  1 1 2  1 1 4
 0.7510
Ex 11: Convert the decimal number 32.48 to binary (to 5 places). [100000.011112]
15
Binary Arithmetic
Binary Addition
There are four basic rules for adding binary digits

02 + 02 = 0 2 (Sum of 0 with a carry of 0)
12 + 12 = 102 (Sum of 0 with a carry of 1)
Some examples:
12 + 02 + 02 = 012 (Sum of 1 with a carry of 0)
Some more complex examples (given with their decimal equivalent)
Ex 12: 1012 (5)+ 0112 (3) [10002 (8)]
Ex 13: 1112 (7)+ 1102 (6) [11012 (13)]
Ex 14: 11112 (15)+ 1102 (6) [101012 (21)]
Ex 15: 10112 (11)+ 11102 (14) +10012 (9)+ 11012 (13) [1011112 (47)]
Ex 16: 0.010102 (0.3125)+ 0.110112 (0.84375) [1.001012 (1.15625)]
16
Negative numbers
Consideration is now given to how negative numbers are represented. A signed binary number
consists of both sign and magnitude information. The sign indicates whether the number is positive
or negative and the magnitude is the value of the number. There are three ways in which signed
whole numbers can be expressed in binary form:
Sign-Magnitude
The left-most bit is the sign bit, and the remaining bits are magnitude bits. In the sign magnitude
system, the negative number has the same magnitude as the corresponding positive number but
the sign bit is a 1 rather than a 0.
Example:
Sign Bit Magnitude Bits
00011001 +25
10011001 -25
Sign Bit Magnitude Bits
In this case, there are 7 magnitude bits, so the largest magnitude is 2 7-1=127. Therefore, this
number system ranges from –127 to +127.
1’s Complement System

Positive numbers here are the same as in the sign-magnitude system. However, a negative number
is the 1’s complement of the corresponding positive number. The 1’s complement of binary
numbers is found by changing all 1s to 0s and all 0s to 1s. Again the most significant bit (MSB)
indicates whether the number is positive or negative.
Example:
00011001 +25
11100110 -25
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2’s Complement System
Positive numbers here are again the same as for the 1’s Complement and Sign-Magnitude systems.
However, a negative number is the 2’s complement of the corresponding positive number. The 2’s
complement of a binary number is found by adding 1 to the least significant bit (LSB) of the 1’s
complement. Again the most significant bit (MSB) indicates whether the number is positive or
negative.
Example:
00011001 +25
11100111 -25
For 2’s complement signed numbers, the range of values for n-bit numbers is
-(2n-1) to (2n-1-1)
where in each case there is one sign bit and (n-1) magnitude bits.
So for this example, n=8, and numbers can be represented in 2’s Complement from –128 to +127.
In summary:
1011 0110 10002 Binary Number
0100 1001 01112 1’s Complement
+12 Add 1
0100 1001 10002 2’s Complement
An alternative method useful for finding the 2’s Complement of long binary numbers is to start at
the right, with the LSB, and write the bits as they are up to and including the first 1. Then take the
1’s complement of the remaining bits.
101101101000
These bits remain as
they are
010010011000
1’s complement of the
original bits
Ex 17: For each binary number in a 4-bit system, (n=4) find the decimal representation in sign
magnitude, one’s complement and two’s complement.
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4 –BIT SIGN- 1’S 2’S
BINARY MAGNITUDE
COMPLEMENT COMPLEMENT
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
When dealing with negative binary numbers, it is important to know where the sign bit is. Describing
the number system used as an n-bit binary number system specifies this. This indicates that the
nth bit is the sign bit.
When two numbers in two’s complement format are added, the result will be in two’s complement
format. Hence, computers use the 2’s complement to represent negative integer numbers in all
arithmetic operations.
Ex 18: Add the 8-bit 2’s comp. binary numbers 00000111 and 00000100. Verify your answer by
converting the numbers being added and the result to decimal. [000010112 (11)]
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converting the numbers being added and the result to decimal. [000010012 (9)]
converting the numbers being added and the result to decimal. [111110002 (-8)]
converting the numbers being added and the result to decimal. [111100102 (-14)]
Binary Subtraction
Subtraction is a special case of addition. For example, subtracting +6 from +9 is the same as
adding –6 to +9. Subtraction of two numbers is the same as taking the 2’s complement of the
number you are subtracting and adding the two numbers, while discarding any final carry bit.
Ex 22: Evaluate 000011102-000010012. Verify your answer by converting the numbers being
subtracted and the result to decimal. [000001012 (5)]
Ex 23: Evaluate 000010012-000011102. Verify your answer by converting the numbers being
subtracted and the result to decimal. [-000001012 (-5)]
20
When two numbers are added and the number of bits required to represent the sum exceeds the
number of bits in the two numbers, an overflow condition results and is indicated by an incorrect
sign bit.
Ex 24: Add the 8-bit binary numbers 01111101 and 00111010. Determine whether or not your
answer is correct by converting the numbers being added and the result to decimal. What is the
answer if a 12-bit binary system is used? [101101112 (183)]
Binary Multiplication
Binary Multiplication is analogous to decimal multiplication. Negative binary numbers must be
changed to uncomplemented form before binary multiplication.
Ex 25: Multiply 101012 by 1102. Verify your answer by converting the numbers being multiplied and
the result to decimal. [11111102 (126)]
21
Binary Division
Binary Division is analogous to decimal division. Negative binary numbers must be changed to
uncomplemented form before binary division.
Ex 26: Divide 110112 by 1102. Verify your answer by converting the numbers being divided and
the result to decimal. [100.102 (4.5)]
SUMMARY
• Introduced to the different numbering systems
• Procedure in converting one number system to another numbering system.
• Computed different arithmetic operation of binary numbers.
• Differentiated a 1’s complement to 2’s complement
• The coming lesson in this module will discuss the concept of digital logic circuits by
introducing the logic gates
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MODULE 3 – Logic Gates
Introduction
The term logic gate actually gives a clue as to the function of these devices in an electronic circuit.
‘Logic’ implies some sort of rational thought process taking place and a ‘gate’ in everyday language
allows something through when it is opened.
A Logic Gate in an electronic sense makes a ‘logical’ decision based upon a set of rules, and if the
appropriate conditions are met then the gate is opened and an output signal is produced.
Logic gates are therefore the decision making units in electronic systems and there are many
different types for different applications. We will now spend some time looking at the different type
of gates and the rules each one uses to decide an appropriate output.
These are basic building blocks of digital circuits. These are circuit elements that take one or more
inputs and perform operations on them to produce a single output. The output depends on type of
gate
Learning Objectives
 Identify the Boolean constants and variables
 identify and use NOT, AND, NAND, OR, NOR EXOR, and XNOR gates;
 express the operation of logic gates through Boolean expressions
 construct and recognise truth tables for these gates and simple combinations of them,
with up to four inputs.
 describe a logic circuit.
 enumerate and differentiate the types of logic circuits
 describe and construct a truth table
 Identify the IC pin configuration of the logic gates
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Course Materials:
Logic Gates
The term gate is used to describe a circuit that performs a basic logic operation. All gates have
both inputs and outputs. The number of inputs can vary depending on the gate in question but
there is generally only one output.
There are three primary logic gates from which, by various combinations, all other gates can be
made. These are the NOT Gate (inverter), the AND Gate and the OR Gate. This unit revisits these
gates and proceeds to introduce a number of other gates.
NOT Gate (Inverter)

The NOT gate has a single input and a single output. The gate very simply inverts the input. The
symbol and truth table for the NOT gate are shown below.
Symbol
Input A Output F
Figure 7. Logic symbol for NOT gate
The circle on the symbol indicates that the output F is the inverse (or complement) of the input A.
Truth Table
A F
0 1
1 0
The above table is known as a truth table. In this table, every possible combination of input is
written in order and the output is determined for each input. There are 2 n possible combinations
in the case of an n-input gate. In other words, there are two possible combinations in the case of a
one-input gate, four possible combinations of input in the case of a two-input gate etc.
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Boolean Expression
FA
or verbally
“F = A bar”
Boolean algebra is the mathematics of digital systems. A letter designates a variable and a bar
over a letter designates the inverse (or complement) of the variable. More generally, a bar over a
quantity designates the inverse (or complement) of that quantity.
AND Gate
The AND gate has multiple inputs and a single output. The output of any AND gate is HIGH only
when all of its inputs are HIGH.
Symbol
Input A
Output F
Input B
Figure 8. Logic symbol for AND gate
In this case the output is HIGH (or logic level 1) only if the inputs A and B are HIGH (or logic level
1). Thus we can write a table defining all the possible states that might occur for this two input AND
gate.
Truth Table
A B F
0 0 0
0 1 0
1 0 0
1 1 1
Boolean Expression
F = A.B
Or more commonly, it is written as F = AB or verbally “F = A and B”
25
The AND gate performs Boolean Multiplication as illustrated in the timing diagram below. Boolean
multiplication follows the same rules as binary multiplication, as discussed in Module 2.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an AND gate
Figure 9. Timing Diagram for an AND gate
3-Input AND Gate

Symbol
Input A
Output F
Input B
Input C
Figure 10. Logic Symbol for 3-input AND gate
Truth Table
A B C F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
26
As can be seen when we have a three input AND gate the same rule applies as did for the two input
gate, i.e. ALL the inputs must be HIGH if we are to achieve a HIGH on the output.
Boolean Expression
F = A. B. C
Or more commonly, it is written as

F = ABC
In Boolean expressions, when variables are written next to each other with no symbol in between,
it is implicitly assumed that they are ANDed.
OR Gate
The OR gate can have two or more inputs. The output of an OR gate is HIGH when one or more
of the inputs are HIGH.
Symbol
Input A
Output F
Input B
Figure 11. Logic symbol for OR gate
Truth Table
A B F
0 0 0
0 1 1
1 0 1
1 1 1
Boolean Expression
F=A+B
Or verbally
“F = A or B”
The OR gate performs Boolean Addition - not to be confused with binary addition as discussed in
module 2.
27
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an OR gate

Figure 12. Timing Diagram for an OR gate
3-Input OR Gate
Symbol
Input A
Input B Output F
Input C
Figure 13. Logic Symbol for 3-input OR gate
Truth Table
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
Again it can be seen from the table that the output is LOW only when all the inputs are LOW.
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Boolean Expression
F=A+B+C
Now that the three basic gates have been considered, they can be combined to generate other
operations.
NAND Gate
This is a combination of the AND gate and the NOT gate in that order.
Symbol
Input A
Output F
Input B
Input A
AB Output F  AB
Input B
Figure 14. Logic Symbol for 2-input NAND gate and its equivalent
Both representations are equivalent. Note that the “bubble” (o) in the top symbol indicates the
presence of an inverter on the output line. The top representation is more common. The bottom
representation indicates how a NAND gate may be broken down.
Truth Table
A B F
0 0 1
0 1 1
1 0 1
1 1 0
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Boolean Expression
F  AB
Or more commonly, F  AB
As can be seen from the table, the inputs are ANDed together and then NOTed (inverted) to give
the final output. The timing diagram shown below illustrates this.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for a NAND gate

Figure 15. Timing Diagram for a NAND gate
NOR Gate
This is a combination of the OR gate and the NOT gate in that order.
Symbol
Input A
Output F
Input B
Input A
A+B Output F  A  B
Input B
Figure 16. Logic Symbol for 2-input NOR gate and its equivalent
Both representations are equivalent. Note that the “bubble” (o) in the top symbol indicates the
presence of an inverter on the output line. The top representation is more common. The bottom
representation indicates how a NOR gate may be broken down.
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Truth Table
A B F
0 0 1
0 1 0
1 0 0
1 1 0
Boolean Expression
F  AB
As can be seen from the table, the inputs are ORed together and then NOTed (inverted) to give the
final output. The timing diagram shown below illustrates this.
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for a NOR gate

Figure 17. Timing Diagram for a NOR gate
XOR Gate (Exclusive OR)

Another gate which is made up of the AND, OR and NOT gates and which is commonly used is an
XOR gate. XOR gates connected to form an adder circuit allow a computer to perform addition,
subtraction, multiplication and division in its Arithmetic Logic Unit (ALU). Shown below is its basic
layout.
31
Logic Diagram
Input A
A.B
Input B B Output
F  A.B  A.B
A.B
Figure 18. Logic Diagram for Exclusive OR gate
Again this is too large to be commonly used so it is summarized into a small logic symbol, which is
shown below.
Symbol
Input A
Output F
Input B
Figure 19. Logic Symbol for Exclusive OR gate
The truth table for this symbol is shown below. It can be seen that the output goes HIGH only when
the inputs differ. If both inputs go HIGH, the output goes LOW. If both inputs go LOW, the output
goes LOW.
Truth Table
A B F
0 0 0
0 1 1
1 0 1
1 1 0
32
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an EXCLUSIVE OR (XOR) gate

Figure 20. Timing Diagram for an EXCLUSIVE OR(XOR) gate
Boolean Expression
The formula that describes the function of this gate is as follows.
F  ABAB
This is more commonly expressed in Boolean algebra by a dedicated symbol – an addition sign
enclosed in a circle, as follows:
F  AB
XNOR Gate (Exclusive NOR)

This is a combination of the XOR gate and the NOT gate (Inverter) in that order.
Symbol
Input A
Output F
Input B
Figure 21. Logic Diagram for Exclusive NOR gate
33
Truth Table
A B F
0 0 1
0 1 0
1 0 0
1 1 1
As can be seen from the truth table, the inputs are XORed together and then NOTed (inverted) to
give the final output.
Boolean Expression
F  AB
Timing Diagram
INPUT A
INPUT B
OUTPUT
Timing Diagram for an Exclusive NOR (XNOR) Gate

Figure 22. Timing Diagram for an EXCLUSIVE NOR(XNOR) gate
34
SELF-ASSESSMENT #2
1. Look at the following logic symbols labelled A – G.
i. Which is the correct symbol for an AND gate. ……………

ii. Which is the correct symbol for a NOT gate. ……………
iii. Which is the correct symbol for a NOR gate. ……………
iv. Which is the correct symbol for an EXOR gate. ……………
v. Which is the correct symbol for a NAND gate. ……………
vi. Which is the correct symbol for an XNOR gate. ……………
vii. Which is the correct symbol for an OR gate. ……………
2. Complete the following truth tables.

i. AND gate.
Inputs Output
A B Q
0 0
0 1
1 0
1 1
35
ii. NOR gate.
Inputs Output
A B Q
0 0
0 1
1 0
1 1
iii. XNOR gate.
Inputs Output
A B Q
0 0
0 1
1 0
1 1
iv. NAND gate.
Inputs Output
A B Q
0 0
0 1
1 0
1 1
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v. OR gate.
Inputs Output
A B Q
0 0
0 1
1 0
1 1
3. The Boolean equations labelled A – I, below are to be used to answer the following
questions.
A. Q  A.B
B. Q  A B
C. Q  A B
D. Q  A.B  A.B
E. Q  A B
F. Q  A.B  A.B
G. QA
H. Q  A.B
I. Q  A B
i. Which expression is correct for an AND gate. ……………
ii. Which expression is correct for a NOT gate. ……………
iii. Which expression is correct for a NOR gate. ……………
iv. Which two expressions are correct for an EXOR gate. ……… & ………
v. Which expression is correct for a NAND gate. ……………
vi. Which two expressions are correct for an XNOR gate. ……… & ………
vii. Which expression is correct for an OR gate. ……………
37
Practical Logic Gates.
Logic gates are usually supplied in plastic D.I.L. (dual in line) packages containing multiple copies
of one type of logic gate. The following diagram shows a picture of this type of package, although
logic gates are usually contained in 14 or 16 pin packages. (A larger device has been shown here
for clarity but the principles of identification are the same for smaller packages).
Figure 23. Logic gates packed in dual in line package

There are two common types available, TTL or 74xx series and CMOS or 4xxx series. It is likely
that you will come across both types in your practical work, so what’s the difference between
them? The key differences are outlined in the table below:
Parameter TTL (74xx family) CMOS (4xxx family)
Supply Voltage 5V ± 0.25V only 3V to 18V
Below 30% of
Logic 0 range 0 to 0.8V
supply voltage
Above 70% of
Logic 1 range 2.0 to 5.0V
supply voltage
Frequency of operation 50 MHz 4 MHz
Power consumption 10mW / gate 0.1mW / gate
This information will be needed when you carry out your practical work, as you will need to know
which type of logic gate you are using.
You will also need to be careful how you connect each logic gate into your circuit as each package
can contain up to six individual gates. To be able to identify which leads are connected to which
gate you need to look at a data sheet for the actual logic gate you are using. A couple of these have
been reproduced below.
38
Figure 24. Internal arrangement of logic gates in 7400 and 7432 ICs
It is important that you check the connections every time you use a logic gate as connecting these
incorrectly can result in the whole logic chip being destroyed.
From an examination situation you will not be required to know the difference between TTL and
CMOS devices, this is required for any practical tests that you carry out, and will be particularly
important for your project work.
SELF-ASSESSMENT #3
The pin out diagrams for a logic IC is shown below.
a) How many logic gates are contained in this IC? …..................
b) How many inputs does each gate have? .......................
c) Give the number of the pin connected to the output of gate G? ………………………
d) Which two pins should be connected to the power Supply? ...............
e) What is the name given to the type of logic gate contained in this IC?
Choose from the following list:
AND OR NOT NAND NOR
Answer: ………………………………………………………………………………………………
39
Analysis of simple logic circuits.
In the examination you may have to recognize truth tables for these basic gates individually, but it
is much more likely that these gates will be linked together in simple combinations and you will be
asked to complete a truth table for a larger system. We will now consider a couple of examples of
these systems.
1. Study the following logic system carefully and then complete the truth table that follows:
Inputs Outputs
B A C Q
0 0
0 1
1 0
1 1
In this problem, the output of the NOT gate has been labeled ‘C’. The first stage is to complete the
output column for ‘C’ which is the NOT of ‘A’ as shown below.
Inputs Outputs
B A C Q
0 0 1
0 1 0
1 0 1
1 1 0
Now we need to complete the final column Q which is the output of the AND gate with ‘B’ and ‘C’
as the inputs.
40
Inputs Outputs
A B C Q
0 0 1 0
0 1 0 0
1 0 1 1
1 1 0 0
Inputs Outputs
A B C F G Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
First complete the output column for the NOT gate (Column F) – {Remember the input is B.}
Then complete the output column for the AND gate (Column G) – {Remember the inputs
are F and C.}
Finally complete the final output from the NOR gate (Column Q) – {Remember the inputs
are A and G}
41
Solution:
Inputs Outputs
A B C F G Q
0 0 0 1 0 1
0 0 1 1 0 0
0 1 0 0 0 1
0 1 1 0 0 0
1 0 0 1 1 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 0 0 0
Here’s a couple for you to try:
Inputs Outputs
A B K Q
0 0
0 1
1 0
1 1
42
Inputs Outputs
A B C F G Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Transferring a truth table into a Logic Diagram

In the previous section we looked at how a system of logic gates could be used to complete a truth
table to illustrate the conditions needed for the output to operate. We will now consider how we can
reverse this process and construct a logic circuit diagram from a truth table. This is best done by
looking at a couple of examples.
Note
In the following examples the outputs have been chosen so that they are not the output of one of
the five logic gates considered previously.
Examples:
1. The following truth table represents a particular logic function. Use the information in the
table to draw a corresponding logic gate system that will produce this function.
43
Inputs Output
A B Q
0 0 0
0 1 0
1 0 1
1 1 0
We first have to identify all the combinations of the inputs that cause the output to come on. In this
case it only occurs once, when input A is on and input B is not on.
The description of what is required to cause the output to operate gives a very good clue as to the
logic gates required in this example. In this case two logic gates are required, a NOT gate and an
AND gate. The NOT gate is used to invert the B input, as shown below.
Figure 25. NOT gate used to have an inverted B output
The output of this NOT gate is then connected to the AND gate with input A to provide the full
solution, as follows:
Figure 26. The complete logic circuit of the truth table of example 1.
Quick Rule
In any 2-input logic system, for every row of the truth table for which the output is logic 1, this output
can be written in terms of the following input conditions: A, NOT A, B, NOT B depending whether
there is a 0 or a 1 in that cell. The 2 inputs are linked with an AND gate.
Going back to our example we identify the output row where Q is a logic 1 and note that A = 1
and B = 0. Because B is 0 we write it down as NOT B as shown:
Inputs Output
A B Q
0 0 0
1 0 0
1 0 1 Output Q = A AND NOT B
1 1 0
44
This gives the same answer as the longer method.
Inputs Output
A B Q
0 0 1
0 1 0
1 0 0
1 1 1
We first have to identify all the combinations of the inputs that cause the output to be logic 1. In
this case it occurs in 2 rows of the truth table.
We then label these output as explained above in the “Quick Rule”.
Inputs Output
A B Q
0 0 1 Output = NOT A AND NOT B

0 1 0
1 0 0
1 1 1 Output = A AND B
The output required for the first line of the truth table is therefore:
Figure 27. The equivalent logic circuit for the first line of the truth table
and the output required for the last line of the truth table is:
Figure 28. The equivalent logic circuit for the last line of the truth table
45
So far we have two separate logic systems providing the output Q. We need to link the two
systems together so that either system can produce the output.
This is achieved by using an OR gate as shown below:
Figure 29. The combined logic circuit of Fig. 27 and Fig. 28 using OR gate
We have some duplicated input terminals here now so the circuit diagram can be simplified by
linking these together as shown below.
Figure 30. The simplified logic circuit of Fig 29
Truth tables with multiple outputs
Quite often a logic system will have more than one output. For example, a set of traffic lights
might have 3 outputs.
For this type of system, we can follow a simple set of rules.
For each output column of the truth table ask yourself the following questions in the order listed
below
1. Is the output column pattern the same as one of the input column patterns?
If the answer is yes, then Q = “The Input” (e.g. Q = B)
2. Is the output column pattern the inverse of the input column pattern?
If the answer is yes, then Q = NOT “The Input” (e.g. Q = NOT C)
3. Is the output column pattern the same as a logic gate output?
If the answer is yes, then Q = “logic gate expression” (e.g. Q = A OR B)
46
4. Is the output column pattern the inverse of one of the other output patterns already
identified?
If the answer is yes, then Q = NOT “Other Output” (e.g. Q3 = NOT Q1)
5. Use the “Quick rule” by labelling rows of the outputs which are logic 1 and link with an OR
gate
e.g. Q = [NOT A AND NOT B] OR [A AND B]
Example
The following truth table shows the outputs required for three LEDs. LEDs used to represent the
operation of a set of traffic lights. Determine the combination of logic gates required to produce the
output pattern shown.
Inputs Outputs
A B Red Yellow Green
0 0 1 0 0
0 1 1 1 0
1 0 0 0 1
1 1 0 1 0
Here we have three separate outputs to be produced by just two inputs, to solve this we just treat
each individual output as a separate problem.
If you examine the input A column and Red output column carefully what do you notice?
They are reproduced below with these columns highlighted.
Inputs Outputs
0 0 1 0 0
0 1 1 1 0
1 0 0 0 1
1 1 0 1 0
Comparing the two highlighted columns we can see that the Red output is the exact opposite of
the A input column. This means that if we simply invert the input A signal, this will produce the
Red output.
i.e. Red = NOT A
47
Figure 31. Logic circuit for output Red
Now for the Yellow output, again check the truth table carefully.
The solution is that the Yellow output follows the B input exactly, and therefore to produce the
Yellow output no logic gates are required. It is simply a case of connecting the Yellow output to
the B input.
i.e. Yellow = B
Here is the solution for the Yellow output:
Figure 32. Circuit for output Yellow(simply a line)
Finally, we have to consider the Green output. A check of the truth table shows there is no simple
relationship to the inputs as was the case with the Red and Yellow outputs. Neither does the output
correspond to the output of a logic gate. We have no choice therefore other than to use the “Quick
rule” to solve this part of the problem. You should be able to produce the system as shown below.
Inputs Outputs
0 0 1 0 0
0 1 1 1 0
1 0 0 0 1 Green = A AND NOT B
1 1 0 1 0
This gives;
Figure 33. Logic circuit for output Green
48
If we connect all three sections together the final system design will look like this:
Figure 34. Combined logic circuit of Fig. 31, 32 and 33.
Note: If we were very observant we could have noticed that the Green output can be obtained
from a NOR gate connected to the Red and Yellow outputs.
Inputs Outputs
0 0 1 0 0
0 1 1 1 0
1 0 0 0 1
1 1 0 1 0
i.e. Green = Red NOR Yellow
The final system would then become:
Figure 35. simplified logic circuit of Fig. 34
It is left to you to check that both solutions produce the correct output pattern.
Now it’s time for you to have a go.
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SELF-ASSESSMENT #4
Inputs Output
A B Q
0 0 0
0 1 0
1 0 1
1 1 0
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Inputs Output
A B Q
0 0 0
0 1 1
1 0 1
1 1 0
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3. An electronic system has two input sensors A and B, and three outputs P, Q and R.
The truth table showing how the input sensors control the outputs is shown below.
Inputs Outputs
A B P Q R
0 0 1 0 1
0 1 1 0 0
1 0 0 0 0
1 1 0 1 0
(a) Study the P output. It is the inverse of one of the inputs.
Write down an expression to describe this output.
P = ...................................................................................
(b) Study the Q output. There is one type of logic gate that will provide this.
What is the name of this gate? .............................................................
(c) Study the R output. There is one type of logic gate that will provide this.
What is the name of this gate? .............................................................
(d) You have a selection of AND, OR, NOT, NAND and NOR gates available. Draw a
labelled diagram to show how the logic system can be made.
4. The following truth table shows the outputs required for three LEDs used to represent the
operation of a set of traffic lights. Determine the combination of logic gates required to
produce the outputs required.
Inputs Outputs
0 0 0 1 0
0 1 0 0 1
1 0 1 1 0
1 1 1 0 0
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Boolean Notation (Higher Level Topic)

There is also a shorthand way of writing down the function of logic gates, using a special type of
algebra called Boolean Algebra. This is used extensively for advanced work in digital electronics.
We shall briefly consider how to express the output of a truth table and logic gates in Boolean
notation. We will start by looking at the five basic gates we have introduced previously.
There are 3 basic things to remember
1. A dot “.” between two input labels is read as “AND”
2. A plus “+” between two input labels is read as “OR”
3. A bar “_” over the top of an input label is read as “NOT”
Gate Symbol Boolean Notation
A Q
NOT QA (read as Q = NOT A )
A
AND
B
Q
Q  A.B (read as Q = A AND B)
Q  A B
A
OR Q (read as Q = A OR B)
B
53
Q  A.B
NAND A (read as Q = A NAND B)
Q
B
A
NOR
B
Q
Q  A B (read as Q = A NOR B)
In addition to the five Boolean notations shown above, each line of a truth table for which the output
is a “1” can also be written in Boolean notation
SELF-ASSESSMENT #5
1. The Boolean equations labelled A – E, below are to be used to answer the following
questions.
A. Q  A.B
B. Q  A B
C. Q  A B
D. QA
E. Q  A.B
i. Which expression is correct for an AND gate. ……………
ii. Which expression is correct for a NOT gate. ……………
iii. Which expression is correct for a NOR gate. ……………
iv. Which expression is correct for a NAND gate. ……………
v. Which expression is correct for an OR gate. ……………
54
2. Write down the Boolean expressions for outputs X, Y and Z:
A B X Y Z
0 0 1 0 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
X = …………………………………………………………
Y = …………………………………………………………
Z = …………………………………………………………
SUMMARY
• Logic gates are the major building block of combinational logic circuits
• Introduced with the different logic gates such as NOT, AND, NAND, OR, NOR,
EXOR, XNOR.
• Constructed truth tables based on the given logic diagram.
• Constructed logic diagram based on a given truth table
• Familiarized with the Physical Logic gate in IC packages
• The coming lesson in this module will discuss the application of Boolean Algebra in
simplifying Boolean expression.
55
MODULE 4 – BOOLEAN ALGEBRA
Introduction
Boolean algebra is formal a way to express digital logic equations, and
to represent a logical design in an alpha-numeric way. The present
Boolean algebra format, and many of the logic manipulation rules and
techniques were formalized around 1850 by George Boole, an Irish
mathematician. It was used as a systematic approach to solving
problems in logic and reasoning. With the advent of modern electronics,
and digital systems in particular, Boolean algebra found a natural home. In addition to being used
as a tool for deductive reasoning, it is now an almost indispensable tool for designing digital logic
circuits and machines.
Boolean Algebra is a mathematical technique that provides the ability to algebraically simplify logic
expressions. These simplified expressions will result in a logic circuit that is equivalent to the original
circuit, yet requires fewer gates.
Learning Objectives
 describe logic circuits algebraically
 discuss the objectives of simplifying Boolean expressions
 enumerate the methods of Boolean expressions simplification
 evaluate logic circuit outputs
 acquaint with Boolean Identities
 apply De Morgan’s Theorem to Boolean Expressions and to logic circuits
 implement the DeMorgan's theorem
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Course Materials:
Boolean Algebra
In our previous module we discovered that logic systems can become quite complex if we don’t use
any simplification techniques. In this topic you will be introduced to the first method of simplification,
Boolean Algebra.
We have already introduced some of the ideas behind Boolean Algebra in simple terms in the
previous module. Here is a brief summary of the idea’s we have covered so far.
 A bar, on top of an input variable, is used to represent the NOT function. E.g. NOT C =
C
 A dot ‘.’, is used to represent the AND function. E.g. A and B =A.B
 A plus ‘+’, is used to represent the OR function. E.g. E OR F = E F
 A plus with a circle ‘’, is used to represent the Exclusive OR (EXOR) function. E.g. C
EXOR D = C D
Write down the Boolean Expressions for the following examples:
1. NOT X …………………………………………
2. R AND T …………………………………………
3. S OR R …………………………………………
4. C EXOR G …………………………………………
5. NOT B AND C …………………………………………
6. NOT X OR NOT Y …………………………………………
7. P EXOR NOT B …………………………………………
8. NOT (A AND B) …………………………………………
9. X NOR Y …………………………………………
57
The following table should remind you of the work we did in Module 3.
Gate Symbol Boolean Equation
NOT A Q QA
AND A
Q Q  A.B
B
OR A
Q Q  A B
B
Q  A.B
NAND A
Q
B
NOR A
Q Q  A B
EXOR A Q  A  B or
Q
B
Q  A.B  A.B
EXNOR A Q  A  B or
Q
B
Q  A.B  A.B
Now let us put this into practice. There are two ways in which Boolean expressions for a logic
system can be formed, either from a truth table or from a logic circuit diagram. We will now consider
each of these in turn starting with the easiest, which is to complete a Boolean expression from a
truth table.
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Deriving a Boolean Expression from a Truth Table
Consider the following truth table of a particular logic system. (Note: at this stage it does not
matter what the system is meant to do).
A B C Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0
In this table there are four combinations of inputs that will produce an output at Q. In order to write
down the Boolean Expression for the whole system we first have to write down the Boolean
Equation for each line in the truth table where the output is a 1. All input variables (three in this
case) must be included in each Boolean Equation on each line, as shown below
A B C Q Boolean Equation
0 0 0 0
0 0 1 1
A.B.C
0 1 0 0
0 1 1 1
A.B.C
1 0 0 1
A.B.C
1 0 1 1
A.B.C
1 1 0 0
1 1 1 0
To obtain the Boolean expression for the whole system we simply take each of these terms and
‘OR’ them together.
Q  A.B.C  A.B.C  A.B.C  A.B.C
59
The expression we obtain from this may not be the simplest possible, we will look at simplification
later. We will concentrate to start with on obtaining a correct Boolean expression for a logic system
before we attempt to simplify them. After all there is not a lot of point being able to simplify an
expression if this is not correct to start with.
SELF-ASSESSMENT #6
Here are a few for you to try:
1.
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
Boolean Expression for system: ………………………………………………
2.
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
60
Boolean Expression for system:
…………………………………………………………………………………………………
3. Now try one with four inputs, the process is exactly the same, it’s just that you now have
four variables in each term.
D C B A Q Boolean Equation
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
Boolean Expression for system:
……………………………………………………………………………………………………………
Hopefully you will have found these tasks fairly straight forward as they are quite easy once you
understand how to write down the variables in Boolean terms.
61
We will now look at how to generate the Boolean expressions from a logic circuit diagram, which
can be a little more difficult depending on the type of gates involved.
Deriving a Boolean Expression from a Logic Circuit.

Sometimes we are not given a truth table, but a logic circuit diagram from which we have to derive
the Boolean expression. This sounds complicated but as long as you are careful in what you do
and work sensibly from the inputs across to the outputs you should be o.k. Let us work through an
example together.
Example 1: Derive the Boolean expression for the following logic circuit.
Figure 36. The logic circuit for example 1

To start the process, try to divide the circuit into stages as shown above. This breaks down a large
circuit into smaller more manageable chunks. It would be virtually impossible to write down the
expression for Q immediately just by looking at the logic diagram, so don’t even try, you are more
than likely to make a mistake.
Having identified the different stages in the circuit diagram, we now proceed to write down the
Boolean expressions for all of the output sections of stage 1, as shown on the following page.
Figure 37. The logic circuit showing the outputs at stage 1
62
Now we move on to look at the outputs of stage 2, as shown below:
And finally we can complete stage 3, to arrive at the expression for the system as
Q  A.B  C
This was a relatively small system of logic gates, and the full system Boolean expression was
determined quite quickly. Now consider a much larger system as shown below. Don’t be put off, we
will again work through this slowly, one stage at a time
Figure 39. A logic circuit showing 4 stages
So to begin with we will work out all of the outputs in stage 1.
63
Then we look at stage 2. Now for stage 3, we have to be very careful as for the first time we are
going to come across NAND gates, and it is really important to keep terms together, so we use
brackets to keep things together.
64
In stage 4 we combine these two large expressions with a NOR function. Again notice the use of
brackets to keep terms together.
Q  (A.B  C)  (A.B).(C  D)
There is no easy way of learning how to complete these logic expressions from circuit diagrams
other than through practice. So the following examples should help you practice the skills needed.
SELF-ASSESSMENT #7
Derive the Boolean Expression for the output of the following logic systems.
1.
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2.
3.
4.
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So now we are able to derive a Boolean Expression for a logic system either from a truth table or
from a logic diagram. The expression we end up with is often very long and complex and can result
in very complicated logic systems being built. What is needed is a method of simplifying these logic
expressions using Boolean algebra.
Laws of Boolean Algebra
The three basic laws of Boolean Algebra are:
(1) Commutative Laws

(a) Law of Addition A B  B  A
(b) Law of Multiplication A.B  B.A
(2) Associative Laws

(a) Law of Addition A  B  C  A  B  C
(b) Law of Multiplication A.B.C  A.B.C
(3) Distributive Law

A.B  C  A.B  A.C
Commutative Laws
The commutative law of Boolean addition for two variables is written as:
A B  B  A
The law states that the order in which the variables are ORed makes no difference to the outcome.
This law can be extended to any number of variables.
A B
A+B B+A
B A
Figure 42. OR gates with interchanged inputs produce the same result
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B A B+A
A B A+B
0 0 0
0 0 0
0 1 1
0 1 1
1 0 1
1 0 1
1 1 1
1 1 1
The commutative law of Boolean Multiplication for two variables is written as:
A.B  B.A
The law states that the order in which the variables are ANDed makes no difference to the
outcome. This law can be extended to any number of variables.
A B
AB BA
B A
S
Figure 43. AND gates with interchanged inputs produce the same result
A B A.B B A B.A
0 0 0 0 0 0
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 1 1 1
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Associative Laws
The associative law of Boolean addition for three variables is written as:
A  B  C  A  B  C
The law states that the result of ORing several variables together is the same regardless of
the grouping of these variables. This law can be extended to any number of variables.
A
A+B
B (A+B)+C
C
Figure 44. Logit circuit in which A and B serves as inputs for the first OR gate, then its
output together with C serves as input for the second OR gate.
A B C A+B (A+B)+C
0 0 0 0 0
0 0 1 0 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
B A+(B+C)
B+C
Figure 45. Logit circuit in which B and C serves as inputs for the first OR gate, then its
output together with A serves as input for the second OR gate.
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A B C B+C A+(B+C)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 0 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
The associative law of Boolean multiplication for three variables is written as:
A.B.C  A.B.C
The law states that the result of ANDing several variables together is the same regardless of
the grouping of these variables. This law can be extended to any number of variables.
A
A.B
(A.B).C
B
Figure 46. Logit circuit in which A and B serves as inputs for the first AND gate, then
its output together with C serves as input for the second AND gate.
A B C A.B (A.B).C
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 1 0
1 1 1 1 1
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A
A.(B.C)
B
B.C
Figure 47. Logit circuit in which B and C serves as inputs for the first AND gate, then
its output together with A serves as input for the second AND gate.
A B C B.C A(BC)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Distributive Law
The distributive law for three variables is written as:
A.B  C  A.B  A.C
The law states that ORing two or more variables and then ANDing the result with a single
variable is the same as ANDing the single variable with each of the two or more variables and
then ORing the result. This law can be extended to any number of variables.
B
B+C
A.(B+C)
C
Figure 48. Logit circuit in which A and B serves as inputs for the OR gate, then its
output together with C serves as input for the AND gate.
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A B C B+C A.(B+C)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
B A.B
(A.B)+(A.C)
A = AB+AC
A.C
Figure 49. Logit circuit in which A and B serves as inputs for the first AND gate, and
inputs A and C serves as inputs for the second AND gate, then their
outputs as input for the OR gate.
A B C A.B A.C A.B+A.C
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 1
Rules of Boolean Algebra
(1) A0  A (7) A.A  A

(2) A 11 (8) A.A  0
(3) A.0  0 (9) AA
(4) A.1 A (10) A  A.B  A
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(5) A A  A (11) A  A.B  A  B
(6) A  A 1 (12) A  B. A  C  A  B.C
These 12 rules are useful in manipulating and simplifying Boolean expressions.
Rule 1
A 0  A
This rule states that if you OR a variable with 0 then you will get that variable at the output.
Shown below is a diagram describing this rule.
A=0 A=1
0 1
0 0
Figure 42. Diagram describing Rule 1

INPUT INPUT OUTPUT
A B
0 0 0
0 1 1
1 0 1
1 1 1
Rule 2
A 1 1
This rule states that if you OR a variable with 1 then you will always get a 1 (logic HIGH) at
the output. Shown below is a diagram describing this rule.
A=0 A=1
1 1
1 1
INPUT INPUT OUTPUT

A B
0 0 0
0 1 1
1 0 1
1 1 1
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Rule 3
A.0  0
When a 0 is ANDed with any logic level then the output of the AND gate is always 0 (logic
LOW). Shown below is a diagram describing the rule.
A=0 A=1
0 0
0 0
INPUT INPUT OUTPUT

A B
0 0 0
0 1 0
1 0 0
1 1 1
Rule 4
A.1 A
When a 1 is ANDed with any variable logic level then the output of the AND gate is always
that variable logic level. Shown below is a diagram describing the rule.
A=0 A=1
0 1
1 1
INPUT INPUT OUTPUT

A B
0 0 0
0 1 0
1 0 0
1 1 1
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Rule 5
A A  A
This rule states that the output of an OR gate when the two inputs are the same is the same
as the inputs. Shown below is a diagram describing the rule.
A=0 0 A=1 1
0 1
0 1
INPUT INPUT OUTPUT

A B
0 0 0
0 1 1
1 0 1
1 1 1
Rule 6
A  A 1
This rule states that when a variable is ORed with the variables inverse, the answer is the
always 1 (logic HIGH). Shown below is a diagram describing the rule.
A=0 1 A=1 0
1 1
0 1

INPUT INPUT OUTPUT
A B
0 0 0
0 1 1
1 0 1
1 1 1
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Rule 7
A.A  A
This rule states that if a variable is ANDed with itself then the output of the AND gate is the
variable input itself. Shown below is a diagram describing the rule.
A=0 0 A=1 1
0 1
0 1

INPUT INPUT OUTPUT
A B
0 0 0
0 1 0
1 0 0
1 1 1
Rule 8
A.A  0
This rule states that when a variable is ANDed with its inverse then the output of the AND
gate is always 0. Shown below is a diagram describing the rule.
A=0 1 A=1 0
0 0
0 1

INPUT INPUT OUTPUT
A B
0 0 0
0 1 0
1 0 0
1 1 1
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Rule 9
AA
This rule states that any variable that goes through two NOT gates successively will be
returned to its original logic level. Shown below is a diagram describing the rule.
A=0 A 1 A0
A=1 A0 A 1
Figure 50. Diagrams describing Rule 9
Rule 10
A  A.B  A
This rule uses the Distributive Law in its proof. The proof is as follows:
A  A.B  A.1  A.B Rule 4

 A.1  B Distributive Law
 A.1 Rule 2
A Rule 4
Shown below is a diagram describing the rule.
A
A+AB
AB
A A
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INPUT INPUT AB OUTPUT
A B A + AB
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 1
Identical
Rule 11
A  A.B  A  B
Rule 11 is proved as follows

A  A.B  ( A A.B)  A.B Rule10
 A  B.( A A) Distributive Law
 A  B.1 Rule 6
 A B Rule 4
A
A  AB
AB
A
A+B

The proof can also be derived using the truth table shown below
INPUT INPUT OUTPUTS

AB
A B
A  AB A+B
0 0 0 0 0
0 1 1 1 1
1 0 0 1 1
1 1 0 1 1
IDENTICAL
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Rule 12
A  B. A  C  A  B.C
This rule is proved as follows
(A+B).(A+C)=A.A+A.C+A.B+B.C Distributive Law
=A+A.C+A.B+B.C Rule 7
= A .( 1 + C ) + A . B + B . C Distributive Law
=A.1+A.B+B.C Rule 2
= A .( 1 + B ) + B . C Distributive Law
=A.1+B.C Rule 2
=A+B.C Rule 4
A
(A+B)
(A+B)(A+C)
A (A+C)
B A+BC
BC
Figure 53. Diagrams describing Rule 12
The proof can also be derived using the truth table shown below:
INPUT INPUT INPUT A+B A+C B.C OUTPUT OUTPUT
A B C (A+B).(A+C) A+B.C
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 1 1 1 1
1 0 0 1 1 0 1 1
1 0 1 1 1 0 1 1
1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1
Identical
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SELF-ASSESSMENT #8
Simplify the following Boolean expressions.
1. Q  A.B  B
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
2. Q  C.(A  C)
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
3. Q  A.B.C  A.C  A.C.D  A.C.D
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
4. Q  A.B.(B  C)  B.C  B
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
5. Q  B.(A  C)  A  A.(A  B)
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
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…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
6. Q  A.B.C  B.C  A.B.C  A.B.B
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
7. Q  A.B.C  B.C.D  B.C.D  B.C.D  A.B.C  A.B.C
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
8. Q  A.B.C.D  A.B.D  A.B.D  A.B.C.D  A.C.D  A.C.D
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
………………………………………………………………………………………………..
De Morgan’s Theorems
De Morgan’s Theorems are expressed for two variables in the following way.
X .Y  X  Y Equation 1
X  Y  X .Y Equation 2
Equation 1 states that the complement of two or more variables ANDed together is equivalent
to the OR of the complements of the individual variables. This can be seen very clearly in the
diagram and truth table below.
X X.Y X XY
Y Y
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X Y X Y X.Y (X  Y) X Y
0 0 1 1 0 1 1
0 1 1 0 0 1 1
1 0 0 1 0 1 1
1 1 0 0 1 0 0
Identical
Equation 2 states that the complement of two or more variables ORed together is equivalent
to the AND of the complements of the individual variables. This can be more clearly seen in
the diagram and the truth table below.
X X
XY X.Y
Y Y
X Y X Y X+Y X Y X Y
0 0 1 1 0 1 1
0 1 1 0 1 0 0
1 0 0 1 1 0 0
1 1 0 0 1 0 0
Identical
De Morgan’s Theorems are not specific to just two variables. They can be applied to more
than two variables. For three variables, De Morgan’s theorems are written as follows.
X .Y .Z  X  Y  Z
X  Y  Z  X .Y .Z
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SELF-ASSESSMENT #9
Simplify the following expressions as much as possible.
1. Q  (A  B).(A.B)  A.B
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
2. Q  A.C.B.D  C.D
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
……………………………………………………………………………………………………………
…………………………………………………………………………………………………………
Creating a Logic Circuit Diagram from Boolean Equation.
Once the simplest Boolean expression has been obtained from a logic description or a truth
table, you will often need to draw the logic circuit diagram. This just means working backwards
from the Boolean expression, and as a general rule of thumb we start with any bracketed
terms, then AND and finally OR functions. Let’s have a look at a couple of examples.
Example 1: Draw the logic diagram for the simplified Boolean expression shown below:
Q  B.(A  C)
First we make up the logic for the bracketed term.
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A
The output of this arrangement then needs to be connected to an AND gate with
input B as shown below:
C Q
Here are a couple for you to try!
SELF-ASSESSMENT #10
Draw the Logic Circuit diagram for the Boolean expressions given.
1. Q  A.B  B.C
2. Q  A  B  A.(C  B)
We have now covered all of the material needed for system simplification via Boolean Algebra.
Together with the work we have done on logic system design, we are now in a position to
tackle some of the examination style questions that brings all of the work we have done so far
together.
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SUMMARY
• Boolean algebra is basically used in simplifying Boolean expression.
• There are Boolean theorems can be applied in simplifying Boolean expression.
• Familiarized with the DeMorgan’s Theorem.
• Creating Logic diagram from the given Boolean expression.
• The coming lesson in this module will discuss the application of Karnaugh
Mapping in simplifying Boolean expression using graphical method.
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MODULE 5 – KARNAUGH MAPPING
Introduction
Congratulations on reaching this point in the course, which will mean that you have
successfully battled your way through some pretty tough Boolean simplification techniques,
which became very complex at times.
In this module, we are going to show you another method of simplification, which you will
hopefully find much quicker and less prone to error, as in many cases the simplest Boolean
expression is obtained immediately, without the need for any further manipulation using
Boolean algebra.
Learning Objectives
 Draw a Karnaugh map for a logic system with up to four inputs and use it to
minimise the number of gates required;
 Determine cell adjacencies in a 2- , 3- and 4- variable K-Maps.
 Form cell groupings in the 2- , 3- and 4- variable K-Maps.
 Minimize the 2- , 3- and 4- K-Maps variables Boolean expressions using K-Maps.
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Course Materials:
Domain of a Boolean Expression
The domain of a general Boolean expression is the set of variables contained in the
expression in either complemented or uncomplemented form.
Find the domain of the expressions:
a.) A’B + AB’C ans. The set of variables are A, B, and C
b.) ABC’ + CD’E + B’CD’ ans. The set of variables are A, B, C, D, and E
Convert any SOP Expression to Standard SOP
 Each product term in an SOP (Sum of Products) expression that does not contain all the
variables in the domain can be expanded to standard form to include all variables in the
domain and their complements.
 As stated in the following steps, a nonstandard SOP expression is converted into
standard form using Boolean algebra rule, (A + A’) = 1.
 A variable added to its complement equals 1.
Steps:
1. Multiply each nonstandard product term by a term made up of the sum of a missing variable
and its complement. This results in two product terms.
2. Repeat Step1 until the resulting product terms contain all the variables in the domain in
either complemented or uncomplemented form.
Note: In converting a product term to standard form, the number of product terms is
doubled for each missing variable.
Example: Convert the following Boolean expression into standard SOP form:
AB’C + A’B’ + ABC’D
Solution:
The domain of this SOP expression is A, B, C, D. Take one term at time.
1st term AB’C lacks variable D
= AB’C (D + D’)
= AB’CD + AB’CD’
2nd term A’B’ lacks variables C and D
= A’B’ (C + C’)
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= A’B’C + A’B’C’ A’B’C + A’B’C’
= A’B’C (D + D’) + A’B’C’ (D + D’)
= A’B’CD + A’B’CD’ + A’B’C’D + A’B’C’D’
3rd term ABC’D is already in standard form.
Finally, AB’C + A’B’ + ABC’D
= AB’CD + AB’CD’ + A’B’CD + A’B’CD’ + A’B’C’D + A’B’C’D’ + ABC’D
Short Notation Form (Canonical Form)

• Any Boolean function that is expressed as a sum of minterms or as a product
of maxterms is said to be in its canonical form.
Let F = AB’C + A’B’ + ABC’D Then

F = AB’CD + AB’CD’ + A’B’CD + A’B’CD’ + A’B’C’D + A’B’C’D’ + ABC’D
write 1 for uncomplemented variable; 0 for complemented variable
= 1011 + 1010 + 0011 + 0010 + 0001 + 0000 + 1101
11 10 3 2 1 0 13
F (A, B, C, D) = ∑ (0, 1, 2, 3, 10, 11, 13)
CONVERT ANY POS EXPRESSION TO STANDARD POS

Each product term in an SOP (Sum of Products) expression that does not contain all the
variables in the domain can be expanded to standard form to include all variables in the
domain and their complements.
• As stated in the following steps, a nonstandard POS expression is converted into
standard form using Boolean algebra rule, (A∙A’) = 0.
• A variable multiplied by its complement equals 0.
Steps:
1. Add to each nonstandard product term a term made up of the product of a missing
variable and its complement.
This results in two sum terms.
2. Apply rule A + BC = (A + B) (A + C)
3. Repeat Step1 until the resulting sum terms contain all the variables in the domain in
either complemented or uncomplemented form.
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Example: Convert the following Boolean expression into standard POS form:
(A + B’ + C) (B’ + C + D’) (A + B’ + C’ + D)
Solution:
The domain of this POS expression is A, B, C, D. Take one term at time.
1st term (A + B’ + C)
= (A + B’ + C) + DD’
= (A + B’ + C + D) (A + B’ + C + D’)
2nd term (B’ + C + D’)
= (B’ + C + D’) + AA’
= (A + B’ + C + D’) (A’ + B’ + C + D’)
3rd term (A + B’ + C’ + D) is already in standard form.
Finally, (A + B’ + C) (B’ + C + D’) (A + B’ + C’ + D)
= (A+B’+C+D)(A+B’+C+D’)(A+B’+C+D’)(A’+B’+C+D’)(A+B’+C’+D) by examination,
terms 2 & 3 are the same
=(A+B’+C=D) (A+B’+C+D’) (A’+B’+C+D’) (A+B’+C’+D)
Short Notation Form (Canonical Form)

Let
F = (A + B’ + C) (B’ + C + D’) (A + B’ + C’ + D)
then
F = (A + B’ + C + D)(A + B’ + C + D’)(A’ + B’ + C + D’)(A + B’ + C’ + D)
Write: 0 for uncomplemented variable; 1 for complemented variable
= (0100) (0101) (1101) (0110)
4 5 13 6
F (A, B, C, D) = (4, 5, 6, 13)
SELF-ASSESSMENT #11
1. Convert the expression below to standard SOP form.
WX’Y + X’YZ’ + WXY’
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2. Convert the expression below to standard POS form.
(A + B’) (B + C)
Simplification of Logic Circuits using Karnaugh Mapping

A Karnaugh map provides a systematic method for simplifying a Boolean expression to
produce the simplest SOP form possible. Like a truth table, it presents all possible values of
input variables and the resulting output for each.
A Karnaugh map is composed of “adjacent cells”. Each cell represents one particular
combination of variable values. The total number of possible combinations of n variables is 2n.
Therefore, there are 2n cells in the Karnaugh map, which is the same as the number of rows
in the corresponding truth table.
The Karnaugh Map
 It is a simple straightforward method for “minimizing” a Boolean expression.

 This method utilizes a map, called a Karnaugh map or K-map, representation of the
truth table.
 Each map is made up of squares called cells.
 Each minterm/maxterm is represented by a cell.
 The cells are arranged such that adjacent cells are assigned to adjacent
minterms/maxterms.
 The cells contain the Boolean values of the expression.
 The Boolean expression is minimized by recognizing various patterns in the Karnaugh
map.
 The simplest recognizable patterns lead to either a sum-of-product terms (SOP)
expression or a product-of-sum terms (POS) expression with a minimum number of
literals.
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Two-variable Karnaugh Map
• There are four minterms for two variables.

• Each minterm is associated with a cell identified by the intersection of the values of A
and B.
• The K-map of an expression is obtained by filling up the map with the values
corresponding to each input combination.
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Three-variable K-map
Input Input Input Minterms
A B C
0 0 0 m0= A.B.C
0 0 1 m1= A.B.C
0 1 0 m2= A.B.C
0 1 1 m3= A.B.C
1 0 0 m4= A.B.C
1 0 1 m5= A.B.C
1 1 0 m6= A.B.C
1 1 1 m7= A.B.C
• Take note that the columns are labeled in reflected order and not in binary progression.
This is to maintain the property that adjacent minterms occupy adjacent cells.
• It should also be noted that both ends are adjacent to each other.
Four-variable K-mapping
Input Input Input Input Minterms
A B C D
0 0 0 0 m0= A.B.C.D
4-Variable Karnaugh Map
0 0 0 1 m1= A.B.C.D
0 0 1 0 m2= A.B.C.D CD
AB 00 01 11 10
0 0 1 1 m3= A.B.C.D
00 m0 m1 m3 m2
0 1 0 0 m4= A.B.C.D
01 m4 m5 m7 m6
0 1 0 1 m5= A.B.C.D
11 m12 m13 m15 m14
0 1 1 0 m6= A.B.C.D
m8 m9 m11 m10
0 1 1 1 m7= A.B.C.D 10
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1 0 0 0 m8= A.B.C.D
1 0 0 1 m9= A.B.C.D
1 0 1 0 m10= A.B.C.D
1 0 1 1 m11= A.B.C.D
1 1 0 0 m12= A.B.C.D
1 1 0 1 m13= A.B.C.D
1 1 1 0 m14= A.B.C.D
1 1 1 1 m15= A.B.C.D
The cells in the Karnaugh map are arranged so that there is only a single variable change
between the minterms in adjacent cells.
For example, for a four variable function (with inputs A, B, C and D), m 0 and m1 are adjacent.
This is because the only change between A.B.C.D and A.B.C.D is D replaced by D. In a
 
similar fashion, m 5 and m13 are adjacent A.B.C.D and A.B.C.D . Note that m 12 and m14 are

also adjacent A.B.C.D and A.B.C.D . 
It can be concluded that each cell in a Karnaugh map is adjacent to cells that are immediately
next to it on any of its four sides. Cells on the top row are adjacent to the corresponding cells
on the bottom row and cells in the left-most column are adjacent to the corresponding cells on
the right-most column (This is called wrap-around). However, a cell is not adjacent to the cells
that diagonally touch any of its corners.
Once a Boolean expression is in the SOP form it can be plotted by placing 1s in the cells
corresponding to the minterms that make up the function.
Grouping the cells
The 1s on a Karnaugh map are grouped according to the following rules by enclosing those
adjacent cells containing 1s. The goal is to maximize the size of the groups and to minimize
the number of groups.
(1) Cells may be combined in groups of 1s, 2s, 4s, 8s 16s, i.e. in groups of 2n.
(2) Cells may combine horizontally and vertically, but NOT diagonally. Each cell in the
group must be adjacent to one or more cells in that same group.
93
(3) As many maximum-sized groups as possible should be formed, until all cells
containing 1s are included in at least one group.
(4) Each 1 on the map should be contained in at least one group. The 1s already in a
group can be included in another group as long as the overlapping groups include
the 1s that are not common.
Simplifying the Boolean expression
This is very easy to do once the cells have been grouped.
(1) Each group of 1s that appears in the table creates a minimized product term. Variables
that occur both uncomplemented and complemented within the group have been
eliminated for that product term.
(2) The final expression is composed of all the product groupings ORed together. This
produces the minimum SOP form.
SELF-ASSESSMENT #12
Now write down the minimized product terms of the functions of Ex. 1 to Ex. 5.
Ex 1: Minimize the following function using Karnaugh Mapping. Verify your result using
Boolean Algebra. F1  X.Y  X.Y  X.Y
Boolean Algebra. F2  A.B  A.B
Boolean Algebra. F3  A.B.C  A.B.C  A.B.C
F4  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
Boolean Algebra.
 A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
F5  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
Boolean Algebra.
 A.B.C.D  A.B.C.D  A.B.C.D
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Don’t Care combinations
In certain cases, some combinations of the inputs can never occur, or if they do it does not
matter what function the output is. This may allow us to further minimize the Boolean function.
However, great care should be taken when using this as part of the minimization process.
When grouping the 1s, the Xs can be treated as 1s to make a larger grouping, or as 0s if they
cannot be used to advantage. Remember, the larger the grouping, the simpler the resulting
Boolean expression.
Example:
F  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
1 1 0 0 m12 1
Truth Table
1 1 0 1 m13 0
Input Input Input Input Minterms Output 1 1 1 0 m14 1
A B C D F 1 1 1 1 m15 0
0 0 0 0 m0 0
Karnaugh Map
0 0 0 1 m1 0
0 0 1 0 m2 0 CD
AB 00 01 11 10
0 0 1 1 m3 0
00 0 0 0 0 B.C.D
0 1 0 0 m4 0
0 1 0 1 m5 0 01 0 0 0 1
0 1 1 0 m6 1 1 0 0 1
11
0 1 1 1 m7 0
1 0 0 1
10
1 0 0 0 m8 1
1 0 0 1 m9 0 A.D
1 0 1 0 m10 1
1 0 1 1 m11 0
F  A.D  B.C.D
Now say that this function had some “don’t care” states denoted by X. The resulting Boolean
function can be minimized further.
95
Karnaugh Map
Truth Table
CD
Input Input Input Input Minterms Output AB 00 01 11 10
A B C D F 00 X 0 0 X
0 0 0 0 m0 X
01 X 0 0 1
0 0 0 1 m1 0
11 1 0 0 1
0 0 1 0 m2 X
0 0 1 1 m3 0 1 0 0 1
10
0 1 0 0 m4 X
D
0 1 0 1 m5 0
0 1 1 0 m6 1
0 1 1 1 m7 0
1 0 0 0 m8 1
1 0 0 1 m9 0
1 0 1 0 m10 1
1 0 1 1 m11 0
1 1 0 0 m12 1
1 1 0 1 m13 0
1 1 1 0 m14 1
1 1 1 1 m15 0
96
It can be seen that the output function has been reduced to contain just one variable. The output
function is
FD
SELF-ASSESSMENT #13
Minimize the following Boolean expressions using Karnaugh Mapping:
Ex. 7: F  A.B.C  A.B.C  A.B.C  A.B.C
Ex. 8: F  A.B.C  A.B.C  A.B.C  A.B.C  A.B.C  A.B.C
F  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D 

Ex. 9:
A.B.C.D  A.B.C.D

Ex. 10:
A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
Ex. 11: F  A.B.C.D  A.B.C.D  A.B.C.D and there are six disallowed combinations (i.e. they
never occur) as follows A.B.C.D, A.B.C.D, A.B.C.D, A.B.C.D, A.B.C.D and A.B.C.D.

Ex. 12:
A.B.C.D  A.B.C.D  A.B.C.D
Ex. 13: The function of Ex. 12, in which minterms m 10 to m15 are not allowed.
Ex. 14: F  A.B.C  A.B.C  A.B.C  A.B.C
 
Ex. 15: F  A.C B  B. B  C 
Ex. 16: F  A.B.C  A.B.C  A.B.C
F  B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D 

Ex. 17:
A.B.C.D  A.B.C.D  A.B.C.D
Ex. 18: F  A.B  A.B.C  A.B.C
Ex. 19: F  A  B.C
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Ex. 20: F  A.B.C.D  A.C.D  B.C.D  A.B.C.D
Ex. 21: F  A.B  A.B.C.D  C.D  B.C.D  A.B.C.D
[
Ex. 22: F  C. A.B.(C  D).B  ( A  D).B ]
Ex. 23: F  B.(A.C.A.D.C.A.D.C)  ( A  B  C D)
[ ]
Ex. 24: F  A. B.D  B.C.D  BC.D  A  B  C  D
Ex. 25: F  A.(BD  C  BD)  CB( AD.AD)
SUMMARY
• Converting Boolean Expression in Sum-of-product form (SOP)
• Converting Boolean Expression in Product-of-sum form (POS)
• Familiarized with the Karnaugh mapping in simplifying Boolean expression.
• Use of Don’t care to maximize the looping for more simplified Boolean expression.
• The coming lesson in this module will discuss the design of combinational logic
circuits.
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MODULE 6 – DESIGN OF COMBINATIONAL LOGIC CIRCUITS
Introduction
In this module, we will be developing the process needed to convert the design brief of a problem
into a truth table. Before we can start we must have a problem that needs to be solved so let’s
begin with something fairly simple to explain the process.
Learning Objectives
 identify the steps in designing Combinational logic circuits
 identify the number of inputs and outputs required by the given design problem
 assign variables to the inputs and outputs of the given design problem
 construct truth table for the given design problem
 simplify the Boolean expression using K-map
 draw the corresponding logic diagram using available ICs
 design and implement the different types of combinational circuits such as decoder,
encode, multiplexer, demultiplexer, comparators, adders, and subtractor.
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Course Materials:
DESIGNING COMBINATIONAL LOGIC CIRCUITS
Definition
Combinational logic circuit is a circuit make up of combination of logic gates, where the output
depends on the present inputs.
Procedure in Designing Logic Circuit to satisfy a given set of requirement.
 Set up the truth table based on the problem statement.

 Derive the output expression from the truth table using the following steps:
o Write an AND terms for each case in the table where the output is 1.
o Each AND term contains each input variable in either 0 or 1. If the variable is 0 for
that particular case in the table, it is inverted in the AND term.
o All the AND terms are then ORed together (sum) to produce the final expression for
the output.
 Simplify the output expression using BOOLEAN THEOREMS or
K- MAP
 Draw the logic circuit.

Problem 1:
A warning light is to be placed on a skip at night to warn any approaching drivers that there is
a hazard in the road. The light should only operate in the dark and the light should be flashing.
Solution:
In any problem of this nature the first stage is to identify the type of inputs needed to
convert external factors e.g. light or temperature into an electrical signal that can be processed
to perform the function required in the design brief. In our problem two input systems are
required, a light sensor and a pulse generator. In a real situation you would design the light
sensor to give the output characteristics. In all problems, you will be given the characteristics
of the light sensor to enable the system to be constructed so for now we will assume the
following:
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The light sensor produces a logic 1 in the dark, and Logic 0 in daylight.
The pulse generator will be producing a continuous series of on / off or Logic 1 / Logic 0 pulses
as soon as the power is switched on.
A simple block diagram of the system can now be constructed.
Light
Sensor (A)
Logic Warning
System Lamp (Q)
Pulse
Generator (B)
Figure 54. Block diagram of the system in problem 1
You will notice that the two inputs have now been given a letter so that we can identify them in a
truth table. In this case there are only two inputs, and therefore there will be four possible
combinations of A and B that we have to consider. The next stage is to construct a truth table to
show all the possible input conditions and for each set of inputs determine when an output is
required.
Input A Input B Output Q Comments
Light Sensor (A) = 0 = Daylight, Pulse Generator (B)

0 0 0
= 0 = Off, Output (Q) Off
Light Sensor (A) = 1 = Dark, Pulse Generator (B) = 0

0 1 0
= Off, Output (Q) Off
Light Sensor (A) = 0 = Daylight, Pulse Generator (B)

1 0 0
= 1 = On, Output (Q) Off
Light Sensor (A) = 0 = Dark, Pulse Generator (B) = 1

1 1 1
= On, Output (Q) On
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A close examination of the Output column reveals that the truth table is that of a simple AND gate.
i.e. Q = A.B so the only logic gate we need is a single AND gate and our system diagram can
now be redrawn as shown below.
Figure 55. Block diagram converted to a logic circuit

In this case the solution has worked out to be quite simple, however let us reconsider this problem
again with a different specification for the Light sensor. What if this had been given as follows:
The light sensor produces a logic 0 in the dark, and Logic 1 in daylight.
In this scenario we would have to redefine our truth table, so let’s do that now.
Input A Input B Output Q Comments
Light Sensor (A) = 0 = Dark, Pulse Generator (B)

0 0 0
= 0 = Off, Output (Q) Off
Light Sensor (A) = 1 = Daylight, Pulse Generator

0 1 0
(B) = 0 = Off, Output (Q) Off
Light Sensor (A) = 0 = Dark, Pulse Generator (B)

1 0 1
= 1 = On, Output (Q) On
Light Sensor (A) = 0 = Daylight, Pulse Generator

1 1 0
(B) = 1 = On, Output (Q) Off
Careful consideration of the Output Column now reveals that it is no longer the output of a simple
logic gate. The output is on when A is a Logic 0 and B is a Logic 1. In Boolean terms we would
write this as Q  A.B.
Our system diagram will now have changed slightly to incorporate the changes determined above
so that we now have:
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Figure 56. The logic circuit of the revised system
Now let us increase the complexity of the system a little bit.
Problem 2:
A market gardener wants to install an automatic watering system for his green houses to ensure
that his prizewinning plants do not suffer from a lack of water. The system however, must have
some safeguards whereby plants should only be watered in daylight, when the soil is dry and the
door to the greenhouse is closed.
The following sensors are available:
A moisture sensor (A) which outputs a Logic 0 when dry, and Logic 1 when wet.
A light sensor (B) which outputs a Logic 1 in daylight, and Logic 0 at night.
A door switch (C) which outputs a Logic 0 when closed and Logic 1 when open.
An overview of the system is therefore as shown below:
Figure 57. Block diagram of the system in problem 2

The next stage is to construct a truth table for this system, as shown on the next page.
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Input A Input B Input C Output Q Comments
Moisture Sensor (A) = 0 = Dry,
Light Sensor (B) = 0 = Night,
0 0 0 0
Door Sensor (C) = 0 = Closed,
Output (Q) = Off
Moisture Sensor (A) = 1 = Wet,
0 0 1 0
Output (Q) = Off
Light Sensor (B) = 1 = Daylight,
0 1 0 1
Output (Q) = On
0 1 1 0
Output (Q) = Off
1 0 0 0
Door Sensor (C) = 1 = Open,
Output (Q) = Off
1 0 1 0
Output (Q) = Off
1 1 0 0
Output (Q) = Off
1 1 1 0
Output (Q) = Off
Careful study of the truth table shows that the output must come on when A is Logic 0, AND B
is Logic 1 AND C is Logic 0 or in Boolean Algebra terms this can be written as: Q  A.B.C .
The complete system diagram therefore now becomes the following:
Figure 58. Block diagram of the system converted to a logic circuit
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An alternative design that does the same thing can be formed if only two input AND gates are
available, by combining two such units together as shown below:
Figure 59. Alternative logic circuit for Fig 58
Spend a few minutes convincing yourself that these two designs are indeed the same. Now it’s
time for you to have a go.
SELF-ASSESSMENT #14
Design Problem 3:
An expensive painting in an art gallery is protected by a modest security system. The picture is
protected by a pressure switch which is normally closed when the picture is in place, but opens if
the picture is removed from the wall. Design a system to sound the alarm if the picture is removed
from the wall only when the gallery is closed at night.
The specification for the available sensors are as follows:
 Picture Pressure sensor (A) which outputs a Logic 0 when picture is in place, and Logic 1
when the picture is removed.
 A light sensor (B) which outputs a Logic 0 during the day, and Logic 1 at night.
 A door switch (C) which outputs a Logic 0 when locked and Logic 1 when unlocked.
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Complete the following system diagram:
Now complete the truth table opposite.
Pressure Sensor (A) = 0 = Picture Present,
Light Sensor (B) = 0 = Daytime,

0 0 0
Door Sensor (C) = 0 = Locked,
Output (Q) = ______
Pressure Sensor (A) = 1 = Picture Missing,

0 0 1
Output (Q) = ______
Light Sensor (B) = 1 = Night-time,

0 1 0
Output (Q) = ______
0 1 1 Light Sensor (B) = 1 = Night-time,
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Output (Q) = ______

1 0 0
Door Sensor (C) = 1 = Un-locked,
Output (Q) = ______

1 0 1
Output (Q) = ______

1 1 0
Output (Q) = ______

1 1 1
Output (Q) = ______
Write down the conditions needed to sound the alarm:

………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
………………………………………………………………………………………………………………
Boolean Equation: ………………………………………
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Now draw a suitable arrangement of logic gates to meet the needs of your system.
If we reconsider the specification for the alarm that you have just designed, you should have
realised that it is a pretty poor design for an alarm, since if someone walked in during the day and
removed the picture from the wall no alarm would sound.
This is clearly an unacceptable position and a better system would sound the alarm every time
the picture was removed from the wall. The owner of the gallery was not happy with this
suggestion as once a week the picture was removed for cleaning, and the alarm should not sound
during this period. The owner stated that when cleaning was taking place, the gallery was closed,
and only took place during daytime hours.
The modified truth table opposite shows the modifications needed to meet the demands of this
enhanced alarm system.
Check through the table carefully to see if you agree!
0 0 0 0 Door Sensor (C) = 0 = Locked,
Output (Q) = Off
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0 0 1 0
Output (Q) = Off (Cleaning in progress)

0 1 0 0
Output (Q) = Off

0 1 1 1
Output (Q) = On

1 0 0 0
Output (Q) = Off

1 0 1 1
Output (Q) = On

1 1 0 0
Output (Q) = Off

1 1 1 1
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Output (Q) = On
Now there are three possible conditions that cause the alarm to sound:
i. A on AND B on AND C off OR

ii. A on AND B off AND C on OR
iii. A on AND B on AND C on.
In Boolean terms this would be written as: Q  A.B.C  A.B.C  A.B.C
This does however make the logic diagram for the alarm much more complicated as shown
below.
This is quite a complex system for what is essentially quite a straight forward system. Imagine
what this would look like if only two input gates were available! It would appear that system design
is going to become very complicated – surely there must be an easier way? Well you will be
pleased to know that there are some additional techniques we can use to make our designs a
little bit more straight forward.
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Coding
The following is a simple example of an application for coding. Digital computers use the binary
number system to perform calculations. However, data is usually fed into the computer in decimal
form and the computer provides results in decimal form. A coding system provides the solution
to these conversion problems.
Decimal Coding
The most common form of decimal coding is Binary Coded Decimal (BCD). In binary coded
decimal, every decimal is expressed by four bits, each having a specified weighting. The best
known code in this group of codes is the BCD 8421 code. When BCD code is used without
qualification, 8421 code is assumed. In this code, the group of four bits has a binary value that
represents the equivalent decimal number. Note that not all possible combinations of the four
bits are used.
Decimal Digit Binary Coded Decimal Output line selected on a

Decoder
Input (8421 Code)
0 00002 Line 0
1 00012 Line 1
2 00102 Line 2
3 00112 Line 3
4 01002 Line 4
5 01012 Line 5
6 01102 Line 6
7 01112 Line 7
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8 10002 Line 8
9 10012 Line 9
The availability of a large variety of codes for the same discrete elements of information results in
the use of different codes by different digital systems. It is sometimes necessary to use the output
of one system as the input to another. A conversion circuit must be inserted between the two
systems if each uses different codes for the same information.
Decoders
A decoder is a circuit used to detect the presence of a certain combination of bits (code) on its
inputs, and to indicate that presence by a specified output level. In its general form, a decoder
has n input lines to handle n bits and from 1 to 2 n output lines to indicate the presence of one or
more n-bit combinations.
In the examples shown in the figure below, the output of the first circuit F1  detects the presence
of the code 1001 on its input, and the output of the second circuit F2  detects the presence of
1100. Each circuit sets its output to high only when the input conditions are met.
A A
B B
F1  A.B.C.D F2  A.B.C.D
C C
D D
Figure 60. Examples of decoders
A 4-bit binary decoder using 16 AND gates is shown below. Note that a 4-bit binary decoder is
also known as a 4-line to 16-line decoder because there are four inputs and sixteen outputs or as
a 1-of-16-line decoder because for any given code of inputs, one of sixteen outputs is activated.
This circuit can be used as a binary to hexadecimal converter. An example of an IC that performs
4-bit binary decoding is the 74HC154.
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A
O0
B
A C
D
A O1
B
B C
D
D
A
O15
B
C
D
Figure 61. A 4-bit binary decoder using 16 AND gates
BCD to Decimal Decoder
A BCD instruction representing one decimal digit can be decoded by a 4 input AND gate using a
BCD to decimal decoder as shown below. Note that a BCD to decimal decoder is also known as
a 4-line to 10-line decoder because there are four inputs and ten outputs or as a 1-of-10-line
decoder because for any given code of inputs, one of ten outputs is activated.
Figure 62. A BCD to Decimal Decoder
It is sometimes desirable to decode only during certain intervals of time. For example, sometimes
the input data on ABCD is not always valid. To account for such cases a strobe input is added to
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each AND gate and all are tied together and excited by a single binary signal, S. If S=1 a gate is
enabled and decoding takes place. If S=0, a gate is disabled and no decoding takes place. An
example of an IC that performs BCD-to-decimal decoding is the 74HC42.
Encoders
An encoder performs the reverse function of a decoder. It accepts an active level on one of its
inputs, representing a digit such as a decimal or octal, and converts this input to a coded output
such as a binary number or BCD. Encoders can also be used to encode various symbols and
alphabetic characters, a good example being the keyboard encoder of a calculator or computer.
The process of converting from familiar symbols or numbers to a coded format is called encoding.
Decimal-To-BCD Encoder
This type of encoder has ten inputs (one for each decimal digit) and four outputs corresponding
to the BCD code. This is a basic 10-line to 4-line encoder.
Decimal Digit BCD Code
A3 A 2 A1A0
0 0 0 0 02
1 0 0 0 12
2 0 0 1 02
3 0 0 1 12
4 0 1 0 02
5 0 1 0 12
6 0 1 1 02
7 0 1 1 12
8 1 0 0 02
9 1 0 0 12
From the table we can determine the relationship between each BCD bit and the decimal digits.
For this circuit, A0 (the LSB) is 1 for digits 1,3,5,7,9, A1 is 1 for digits 2,3,6,7, A2 is 1 for digits 4,5,6,7
and A3 (the MSB) is 1 for digits 8 or 9.
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Figure 63. A Decimal to BCD Encoder
Multiplexers
A digital multiplexer (MUX) is a combinational logic circuit that selects binary information from one
of many input lines and directs it to a single output line. The selection of a particular input line is
controlled by a set of data-select lines. Normally there are 2 n input lines and n data-select lines
whose combinations determine which input is selected.
Ex 1: Build a 2-input to 1-output Multiplexer
I0
O
2-1 MUX
I1
Select, S
Figure 64: Logic symbol of a 2-input to 1-output Multiplexer
In this example, when the select function, S is LOW (0), I 0 is selected and when the select
function, S is HIGH (1), I1 is selected.
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I0 I0
O O
I1 I1
S=0 S=1
Figure 65: Simple illustration of multiplexer
Therefore, the output function, O is
O  I 0 S  I1 S
When S  0 ,
O  I 0 .0  I1.0
 I 0 .1  0
 I0
When S  1,
O  I 0 .1  I1.1
 I 0 .0  I1
 I1
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Figure 66. The logic circuit for a 2-1 Multiplexer
Ex. 2: Build a 4-input to 1-output Multiplexer
I0
I1
O
I2 4-1 MUX
I3
S1 S2
Figure 67. Logic symbol of a 4-1 Multiplexer
The data selection for a 4-1 multiplexer is as follows (Note that this is not a truth table).
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There are four input lines. This data is multiplexed onto one output line. The select lines are
used to select the input lines to pass through the MUX to the output line. If the select code is 01,
then I1 appears at the output O. If the select code is 11 then the output is D 3. The logic circuit for
a 4-1 Multiplexer is given below.
Figure 68. The logic circuit for a 4-1 Multiplexer
The output of this circuit is
O  S2 .S1.I 0  S2 .S1.I1  S2 .S1.I 2  S2 .S1.I 3
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Examples of commercially available multiplexers are a Quad 2 to 1-line multiplexer (74HC157A)
and an 8 to 1-line multiplexer (74LS151).
16-to-1-line IC packages are also available. For example, a 16-input MUX is implemented on a
24 pin IC with 16 data inputs, a 4-bit select code, a strobe enable input, one output, a power
supply pin and a ground pin. In this case there are sixteen 6-input AND gates (4 select inputs
can select 24 = 16 data inputs).
Demultiplexer
A demultiplexer (demux) essentially reverses the multiplexer function. It takes digital information
from one line (serial data) and distributes it to one of a number of output lines. The selection of a
particular output line is controlled by a set of data-select lines. Normally there are 2n output lines
and n data-select lines whose combinations determine which output is selected. Non-selected
outputs are either non-active or are open circuit.
Ex 3: Build a 1-line to 4-line demultiplexer.
 
It receives information on a single line and transmits this information to one of four 2 2 possible
output lines. The selection of the output lines is controlled by the two data select lines, S1 and S2
.
Figure 69. Logic symbol of a 1-to-4 demultiplexer
The data selection for a 1-4 demultiplexer is as follows (Note that this is not a truth table).
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The logic circuit for a 1-to-4 demultiplexer is given below.
Figure 70. Logic circuit for a 1-to-4 demultiplexer
A decoder can be converted to a demultiplexer by applying the data signal at the strobe input, S
of the decoder. The signal appears at all the AND gates but only the gate which has “ones” at all
of its other inputs selects the data signal and allows it through.
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Ex 4: Show how a 2-line to 4-line Decoder may be used as a 1-line to 4-line Demultiplexer
A decoder and a demultiplexer have essentially the same circuit.
Figure 71. A 2-line to 4-line Decoder
Figure 72. A 1-line to 4-line Demultiplexer
 
When the input data, I is low, the active low strobe signal is high, I  0  S  1 S  0 , then all
of the outputs are disabled. When the input data, I is high, the active low strobe signal is low
I  1 S  0  S  1 then whichever output is enabled by the select inputs S ,S 1 2 (i.e. A, B) is
selected. All of the other outputs are deselected. For the example shown, above, the outputs
D0 to D3  are active high. Therefore, if an output is selected, it goes LOW. All of the other
(deselected) outputs go HIGH.
In the case of Philips Semiconductor’s 74HCT139 (a dual 2-to-4-line decoder/demultiplexer), all

the outputs are active low. Therefore, if an output is selected, it goes LOW. All of the other
(deselected) outputs go HIGH.
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SELF-ASSESSMENT #15
Ex. 1: State the function performed by a Demultipexer. Draw the logic diagram for a 1-to-4 line
Demultiplexer.
Ex. 2:
(a)What binary number is this decoder looking for, assuming A is the least significant bit:
(b)State the function performed by an encoder. Draw the truth table and logic diagram for a 10-
to-1-line encoder
(c) What is the BCD code for the decimal number 10
Ex. 3:
(a)State the function performed by a Multiplexer. Draw the logic diagram for a 4-to-1-line
Multiplexer.
(b)If a Multiplexer has 3 select lines, what is the maximum number of input lines that can be
selected?
SUMMARY
• Implemented the steps in designing combinational logic circuits
• Design and constructed a digital system based on worded-problem
specifications.
• Implemented the application of decoder and encoder in digital system.
• Implemented the application of multiplexer and demultiplexer in digital
system.
• The coming lessons in this module will discuss the introduction to sequential
logic circuits.
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MODULE 7 – INTRODUCTION TO SEQUENTIAL CIRCUITS
Introduction
Combinational logic refers to circuits whose output is strictly depended on the present value of
the inputs. As soon as inputs are changed, the information about the previous inputs is lost, that
is, combinational logics circuits have no memory. In many applications, information regarding
input values at a certain instant of time is required at some future time. Although every digital
system is likely to have combinational circuits, most systems encountered in practice also include
memory elements, which require that the system be described in terms of sequential logic.
Circuits whose outputs depends not only on the present input value but also the past input value
are known as sequential logic circuits. The mathematical model of a sequential circuit is usually
referred to as a sequential machine.
Learning Objectives
 construct the RS flip-flop by using NOR gate and NAND gate.
 draw the symbol and create a truth table for RS flip-flop.
 draw the timing diagram for the RS flip-flop and sketch the output for this flip-flop.
 draw the symbol; create a truth table and timing diagram for the clocked RS flip-flop.
 draw clocked RS flip-flop with Preset and Clear control input.
 draw the symbol, truth table and timing diagram for clocked RS flip-flop.
 draw the symbol, truth table and timing diagram for JK, T and D flip-flop.
 construct a T and a D flip-flop using a JK flip-flop.
 draw the symbol, truth table and timing diagram for MASTER/SLAVE JK flip-flop.
 state the applications of JK flip-flop, T flip-flop and D flip-flop
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Course Materials:
This is an introductory lesson on sequential logic circuits.
 The general block diagram of a combinational circuit is shown in Figure 1.

 A Combinational logic circuit consists of input variables (X), logic gates (Combinational
Circuit), and output variables (Z).
Figure 73. General Block Diagram of a Combinational Circuit
 Unlike combinational circuits, sequential circuits include memory elements (See

Figure 2).
 The memory elements are circuits capable of storing binary information.
 The binary information stored in these memory elements at any given time defines the
state of the sequential circuit at that time.
 The outputs, Z, of a sequential circuit depends both on the present inputs, X, and the
present state Y (i.e., information stored in the memory elements).
 The next state of the memory elements also depends on the inputs X and the present
state Y.
Figure 74. General Block Diagram of a Sequential Circuit
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The diagram consists of combinational circuit to which memory elements are connected to form
a feedback path. The memory elements are devices capable of storing binary information within
them. The combinational part of the circuit receives two sets of input signals: one is primary
(coming from the circuit environment) and secondary (coming from memory elements). The
particular combination of secondary input variables at a given time is called the present state of
the circuit. The secondary input variables are also known as the state variables.
The block diagram shows that the external outputs in a sequential circuit are a function not only
of external inputs but also of the present state of the memory elements. The next state of the
memory elements is also a function of external inputs and the present state. Thus a sequential
circuit is specified by a time sequence of inputs, outputs, and internal states.
Self-Assessment #16
These short quizzes are to refresh on what you have learned so far.
1. A sequential circuit is a digital circuit whose logic A. True B. False

states depend on a specified time sequence.
2. Sequential circuits contain only combinational A. True B. False

logics.
3. Sequential circuits contain memory and A. True B. False

combinational circuits do not.
4. The outputs of a sequential circuit are computed A. True B. False

using both the present and past input values.
Synchronous and Asynchronous Operation

Sequential circuits are divided into two main types: synchronous and asynchronous. Their
classification depends on the timing of their signals.
Synchronous sequential circuits change their states and output values at discrete instants of
time, which are specified by the rising and falling edge of a free-running clock signal. The clock
signal is generally some form of square wave as shown in Figure 2 below.
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Figure 75. Clock Signal
From the diagram you can see that the clock period is the time between successive transitions
in the same direction, that is, between two rising or two falling edges. State transitions in
synchronous sequential circuits are made to take place at times when the clock is making a
transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge). Between successive clock pulses
there is no change in the information stored in memory.
The reciprocal of the clock period is referred to as the clock frequency. The clock width is
defined as the time during which the value of the clock signal is equal to 1. The ratio of the clock
width and clock period is referred to as the duty cycle. A clock signal is said to be active high if
the state changes occur at the clock's rising edge or during the clock width. Otherwise, the clock
is said to be active low. Synchronous sequential circuits are also known as clocked sequential
circuits.
The memory elements used in synchronous sequential circuits are usually flip-flops. These
circuits are binary cells capable of storing one bit of information. A flip-flop circuit has two outputs,
one for the normal value and one for the complement value of the bit stored in it. Binary
information can enter a flip-flop in a variety of ways, a fact which give rise to the different types of
flip-flops.
In asynchronous sequential circuits, the transition from one state to another is initiated by the
change in the primary inputs; there is no external synchronization. The memory commonly used
in asynchronous sequential circuits are time-delayed devices, usually implemented by feedback
among logic gates. Thus, asynchronous sequential circuits may be regarded as combinational
circuits with feedback. Because of the feedback among logic gates, asynchronous sequential
circuits may, at times, become unstable due to transient conditions. The instability problem
imposes many difficulties on the designer. Hence, they are not as commonly used as synchronous
systems.
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Self-Assessment #17
1. Sequential circuits can be synchronous and A. True B. False

asynchronous.
2. A synchronous sequential circuit changes its A. True B. False

states at discrete instants of time.
3. Asynchronous sequential circuits can have state A. True B. False

transitions at discrete instants of time.
4. Synchronous sequential circuits are also known as A. True B. False

clocked sequential circuits.
5. A transition of a clock from 0 to 1 is called the A. True B. False

falling edge.
6. The clock period is the time when the clock signal A. True B. False
is equal to 1.
7. The memory used in synchronous sequential A. True B. False

circuits are flip-flops.
Basic Flip-flop Circuits

Sequential logic is a form of binary circuit design that employs one or more inputs and one or
more outputs, whose states are related by defined rules that depend, in part, on previous states.
Each of the inputs and output(s) can attain either of two states: logic 0 (low) or logic 1 (high).
The most common electronic circuit for storing a single binary digit, or bit, is a Flip-Flop. The Flip-
Flop belongs to a family of sequential logic circuits known as multivibrators. There are three types
of multivibrators: The bistable, monostable and astable.
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1. There are two categories of bistable devices, the Latch and the Flip-Flop. Bistable
devices have two stable states called SET and RESET and can remain in either state
indefinitely, making them useful as storage devices. The basic difference between a Latch
and a Flip-Flop is the way in which they are changed from one state to the other. The Flip-
Flop is the basic building block for registers, counters and memories.
2. The monostable multivibrator, commonly called a one-shot, has only one stable state. It
produces a single controlled-width pulse in response to a triggering input. It is generally
used as a timing device and is used in the triggering circuit of an oscilloscope.
3. The astable multivibrator has two unstable states and switches constantly, or oscillates,
from one state to the other. In digital electronics it is used to generate clock pulses.
There are several different kinds of flip-flop circuits, with designators such as D, T, J-K, and R-S.
Sequential logic differs from combinational logic. In the latter scheme, the output states depend
only on the input states at a specific moment in time, and not on previous states.
A flip-flop circuit can be constructed from two NAND gates or NOR gates. These flip-flops
are shown in Figure 1.1 and Figure 1.3. Each flip-flop has two outputs, Q and Q , and two inputs,
Set and Reset. This type of flip-flop is referred to as an RS flip-flop or RS latch. The flip-flop in
Figure 1.1 has two useful states. When Q= 1 and Q = 0, it is in set state (or logic ‘1’). When Q=
0, and Q = 1, it is in clear state. The outputs Q and Q are complements of each other and are
referred to as the normal and complement outputs respectively. The binary state of the flip-flop is
taken to be the value of the normal output.
When logic ‘1’ is applied to both of the set and reset inputs in Figure 1.1, both Q and Q outputs
go to logic ‘0’. This condition violates the fact that both outputs are complements of each other.
In normal operation this condition must be avoided by making sure that 1’s is not applied to both
inputs simultaneously.
R (reset ) Q
S (set ) Q
Figure 76. NOR gate RS latch
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Table 1.1: Truth table for NOR gate RS latch
SET
RESET
Invalid
Figure 77. Timing diagram of NOR gate SR latch
S (set ) Q
R (reset ) Q
Figure 78. NAND gate SR latch
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Table : Truth table for NAND gate RS Latch
Figure 79. Timing Diagram for NAND gate RS Latch
The NAND basic flip-flop circuit in Figure 1.3 operates with inputs normally at 1 unless the state
of the flip-flop has to be changed. A logic ‘0’ applied momentarily to the set input causes Q go to
logic ‘1’ and Q to logic ‘0’, putting the flip-flop in the set state. When both inputs go to logic ‘0’,
both outputs go to logic ‘1’. This condition should be avoided in normal operation.
Clocked RS Flip-Flop
Two different methods for constructing a RS flip-flop were discussed in section 1.1. The addition
of two AND gates at the S and R inputs as shown in Figure 1.5 will result in a flip-flop that can be
enabled or disabled. When the ENABLE input is low, the AND gate outputs must both be low and
changes in neither S nor R will have any effect on the flip-flop output Q.
The clocked RS flip-flop shown in Figure 1.5 consists of a basic NOR flip-flop and two AND gates.
The outputs of the two AND gates remain at logic ‘0’ as long as the clock pulse (or CP) is logic
‘0’, regardless of the S and R input values. When the clock pulse goes to logic ‘1’, information
from the S and R inputs passes through to the basic flip-flop. With both S= 1 and R= 1, the
occurrence of a clock pulse causes both outputs to momentarily go to logic ‘0’. When the clock
pulse is removed, the state of the flip-flop is indeterminate, i.e., either state may result, depending
on whether the set or reset input of the flip-flop remains logic ‘1’ longer than the transition to logic
‘0’ at the end of the pulse.
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R (reset )
Q
CP
(clock pulse)
S (set ) Q
Figure 80. Logic circuit of clocked SR Flip-flop
Table 1.3: Truth table for the clocked RS flip-flop
SET
RESET
Invalid
Figure 81: Timing diagram of SR flip-flop
Example 1
Determine the Q and Q output waveforms of the flip-flop in figure (a) below for the S, R, and CLK
inputs in figure (b). Assume that the positive edge-triggered flip-flop is initially RESET.
SET
S Q
CLK
R CLR
Q
(a)
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CLK 1 2 3 4 5 6
(b) R
(c) Q
At clock pulse 1, S is LOW and R is LOW, so Q does not change.

2. At clock pulse 2, S is LOW and R is HIGH, so Q remains LOW (RESET).
3. At clock pulse 3, S is HIGH and R is LOW, so Q goes HIGH (SET).
4. At clock pulse 4, S is LOW and R is HIGH, so Q goes LOW (RESET).
5. At clock pulse 5, S is HIGH and R is LOW, so Q goes HIGH (SET).
6. At clock pulse 6, S is HIGH and R is LOW, so Q stays HIGH.
Once Q is determined, Q is easily found since it is simply the complement of Q. The resulting
waveforms for Q and Q are shown in figure (c) for the input waveforms in figure (b).
Clocked RS Flip-flop with ‘Preset’ and ‘Clear’ Input Control
Most integrated circuit flip-flops also have asynchronous inputs. These are inputs that
affect the state of the flip-flop independent of the clock. They are normally labeled preset (PRE)
and clear (CLR). An active level on the preset input will SET the flip-flop, and an active level on
the clear input will RESET it. A logic symbol for a RS flip-flop with preset and clear inputs is shown
in Figure 1.6. These inputs are active-LOW, as indicated by the bubbles. These preset and clear
inputs must both be kept HIGH for synchronous operation.
PRE
S Q
R Q
CLR
Figure 82. Logic symbol of the SR flip-flop with Preset and Clear input
control
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Input Output
Asynchronous Synchronous
Mode
Preset Clear S R CLK Q (t+1)
Asynchronous set 0 1 x x x 1
Asynchronous reset 1 0 x x x 0
No change 1 1 0 0 1 No change
Reset 1 1 0 1 1 0
Set 1 1 1 0 1 1
Invalid 1 1 1 1 1 Invalid
1 2 3 4 5 6 7 8 9
Preset
Clear
Invalid
Figure 83. Timing diagram of the RS flip-flop
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SELF-ASSESSMENT # 18
1. If an RS latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0,
the latch will be
(a) set (b) reset (c) invalid (d) clear
2. The invalid state of an RS latch occurs when

(a) S= 1, R= 0 (b) S=0, R= 1
(c) S= 1, R= 1 (d) S= 0, R= 0
3. The purpose of the clock input to a flip-flop is to
(a) clear the device (b) set the device (c) always cause the output change states
(d) cause the output to assume a state dependent on the controlling inputs.
4. Develop the truth table for the active-HIGH input RS latch in figure below.
R (reset ) Q
S (set ) Q
5. How does a JK flip-flop differ from an RS flip-flop in its basic operation?
JK Flip-flop
A JK flip-flop is a refinement of the RS flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop
(note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic ‘1’ inputs
are applied to both J and K simultaneously, the flip-flop switches to its complement state, i.e., if
Q=1, it switches to Q= 0 and vice versa.
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A clocked JK flip-flop is shown in Figure 1.8. Output Q is ANDed with K and CP inputs so that the
flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1
(while J = K = 1) after the outputs have been complemented once will cause repeated and
continuous transitions of the outputs. To avoid this, the clock pulses must have time duration less
than the propagation delay through the flip-flop. The restriction on the pulse width can be
eliminated with a master-slave or edge-triggered construction.
K Q
CP
J Q
Figure 84. Logic circuit of the JK flip-

flop
J Q
CP
K Q
Figure 85. Logic symbol of the JK flip-flop
Q J K Q (t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Table 1.5: Truth table for the clocked JK flip-flop
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CLK
Figure 86. Timing diagram of the JK flip-flop
Example:
The waveforms in figure (a) below are applied to the J, K, and clock inputs are indicated.
Determine the Q output, assuming that the flip-flop is initially RESET.
SET
J Q
CLK
K CLR
Q
CLK 1 2 3 4 5
(a) K
(b) Q No
Toggle Change Reset Set Set
Solution:
1. First, since this is a negative edge-triggered flip-flop, as indicated by the “bubble” at the
clock input, the Q output will change only on the negative-going edge of the clock pulse.
2. At the first clock pulse, both J and K are HIGH; and because this is a toggle condition, Q
goes HIGH.
3. At clock pulse 2, a no-change condition exists on the inputs, keeping Q at a HIGH level.
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4. When clock pulse 3 occurs, J is LOW and K is HIGH, resulting in a RESET condition; Q
goes LOW.
5. At clock pulse 4, J is HIGH and K is LOW, resulting in a SET condition; Q goes HIGH.
6. A SET condition still exists on J and K when clock pulse 5 occurs, so Q will remain HIGH.
The resulting Q waveform is indicated in figure (b).
T Flip-Flop
The toggle, or T, flip-flop is a bistable device that changes state on command from a
common input terminal. The standard symbol for a T FF is illustrated in Figure 1.11. The T input
may be preceded by an inverter. An inverter indicates a FF will toggle on a HIGH-to-LOW
transition of the input pulse. The absence of an inverter indicates the FF will toggle on a LOW-to-
HIGH transition of the pulse. The most commonly used T FFs are J-K FFs wired to perform a
toggle function as shown in Figure 1.12.
T Q T
J Q
CLK
Q K Q
Figure 87. Logic symbol of the T flip-flop
T Q
CP
Figure 88. Logic circuit of the T flip-flop
Table 1.6: Truth table for the T flip-flop
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The timing diagram in Figure 1.13 shows the toggle input and the resulting outputs. We will
assume an initial condition (T0) of Q being LOW and Q being HIGH. At T1, the toggle changes
from a LOW to a HIGH and the device changes state; Q goes HIGH and Q goes LOW. The
outputs remain the same at T2 since the device is switched only by a LOW-to-HIGH transition. At
T3, when the toggle goes HIGH, Q goes LOW and Q goes HIGH; they remain that way until T 5.
Figure 89. Timing diagram of T flip-flop
Between T1 and T5, two complete cycles of T occur. During the same time period, only one cycle
is observed for Q or Q. Since the output cycle is one-half the input cycle, this device can be used
to divide the input by 2.
D Flip-Flop
The D FF is a two-input FF. The inputs are the data (D) input and a clock (CLK) input. The clock
is a timing pulse generated by the equipment to control operations. The D FF is used to store data
at a predetermined time and hold it until it is needed. This circuit is sometimes called a delay FF.
In other words, the data input is delayed up to one clock pulse before it is seen in the output.
The D flip-flop shown in Figure 1.14 is a modification of the clocked SR flip-flop. The D input goes
directly into the S input and the complement of the D input goes to the R input. The D input is
sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state
(unless it was already set). If it is 0, the flip-flop switches to the clear state.
D
Q
CP
(clock pulse)
Figure 90. Logic circuit of the D flip-flop
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D Q D J Q
CLK
CP
Q
K Q
Figure 91. Logic symbol of the D flip-flop
CLK D Q Operation
0 1 0 start
↑ 1 1 store 1
0 0 Q no change
↑ 0 0 store 0
Table 1.7: Truth table for the D flip-flop
Depending on the circuit design, the clock (CLK) can be a square wave, a constant frequency,
or asymmetrical pulses. In this example the clock (CLK) input will be a constant input at a given
frequency. This frequency is determined by the control unit of the equipment. The data (D) input
will be present when there is a need to store information. Notice in the Truth Table that output Q
reflects the D input only when the clock transitions from 0 to 1 (LOW to HIGH).
Let's assume that at T0, CLK is 0, D is 1, and Q is 0. Input D remains at 1 for approximately 2½
clock pulses. At T1, when the clock goes to 1, Q also goes to 1 and remains at 1 even though D
goes to 0 between T2 and T3. At T3, the positive-going pulse of the clock causes Q to go to 0,
reflecting the condition of D. The positive-going clock pulse at T5 causes no change in the output
because D is still LOW. Between T5 and T6, D goes HIGH, but Q remains LOW until T7 when the
clock goes HIGH.
Figure 92. Timing diagram of D flip-flop
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The key to understand the output of the D FF is to remember that the data (D) input is seen in
the output only after the clock has gone HIGH.
Master/Slave JK Flip-flop
Another class of flip-flop is the master/slave. Although this type of flip-flop has largely been
replaced by the edge-triggered devices, a limited selection is still available from IC manufacturers
and you may encounter this type of flip-flop in some existing equipment.
The logic symbol of master/slave JK flip-flop is shown Figure 1.17. The truth table operation is
the same as that for the edge-triggered JK flip-flop except for the way it is clocked. Internally,
though, it is different.
This type of flip-flop is composed of two sections, the master section and the slave section. The
master section is basically a gated latch, and the slave section is the same except that it is clocked
on the inverted clock pulse and is controlled by the outputs of the master section rather than by
the external JK inputs.
PRE
J Q
CLK
K Q
CLR
Figure 93. Circuit diagram and logic symbol of master/slave JK

flip-flop
Any input to the master-slave flip-flop at J and K is first seen by the master FF part of the circuit
while CLK is High (=1). This behavior effectively "locks" the input into the master FF. An important
feature here is that the complement of the CLK pulse is fed to the slave FF. Therefore, the outputs
from the master FF are only "seen" by the slave FF when CLK is Low (=0). Therefore, on the
High-to-Low CLK transition the outputs of the master are fed through the slave FF. This means
that the at most one change of state can occur when J= K= 1 and so oscillation between the
states Q= 0 and Q= 1 at successive CLK pulses does not occur.
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Table 1.8: Truth table for the master/slave JK flip-flop
CLK
Figure 94. Timing diagram of master/slave JK flip-flop
SELF-ASSESSMENT # 19
1. A feature that distinguishes the JK flip-flop from the RS flip-flop is the

(a) toggle condition (b) preset input
(c) type of clock (d) clear input
2. A flip-flop is in the toggle condition when
(a) J= 1, K= 0 (b) J=0, K= 1
(c) J= 0, K= 0 (d) J= 0, K= 1
3. For an edge-triggered D flip-flop,
(a) a change in the state of the flip-flop can occur only at a clock pulse edge
(b) the state that the flip-flop goes to depends on the D input
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(c) the output follows the input at each clock pulse
(d) all of these answers
4. A JK flip-flop is presently in the RESET state and True False

must go to the SET state on the next clock pulse. J
must be 1 and K must be X (don't care).
5.A JK flip-flop is presently in the SET state and must True False
remain SET on the next clock pulse. Then J must be
X and K must be 1.
6.A RS flip-flop is presently in a SET state and must True False

go to the RESET state on the next clock pulse. S
must be 1 and R must be 0.
7. For a D flip-flop, the next state is always equal to True False

the D input.
8. For a D flip-flop, when the present state Q=0 goes True False
to the next state Q=1, the required D input is D=1
9.Describe the basic difference between pulse-triggered and edge-triggered flip-flops.

10.Suppose that the D input of a flip-flop changes from LOW to HIGH in the middle of a positive-
going clock pulse.
i. Describe what happens if the flip-flop is a positive edge-triggered type.
ii. Describe what happens if the flip-flop is a pulse-triggered master/slave type.
State Tables and State Diagrams
We have examined a general model for sequential circuits. In this model the effect of all previous
inputs on the outputs is represented by a state of the circuit. Thus, the output of the circuit at any
time depends upon its current state and the input. These also determine the next state of the
circuit. The relationship that exists among the inputs, outputs, present states and next states can
be specified by either the state table or the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections labelled present
state, next state and output. The present state designates the state of flip-flops before the
occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse,
and the output section lists the value of the output variables during the present state.
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State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be represented graphically
by a state diagram. In this diagram, a state is represented by a circle, and the transition between
states is indicated by directed lines (or arcs) connecting the circles. An example of a state diagram
is shown in Figure 3 below.
Figure 95. State Diagram

The binary number inside each circle identifies the state the circle represents. The directed lines
are labelled with two binary numbers separated by a slash (/). The input value that causes the
state transition is labelled first. The number after the slash symbol / gives the value of the output.
For example, the directed line from state 00 to 01 is labelled 1/0, meaning that, if the sequential
circuit is in a present state and the input is 1, then the next state is 01 and the output is 0. If it is
in a present state 00 and the input is 0, it will remain in that state. A directed line connecting a
circle with itself indicates that no change of state occurs. The state diagram provides exactly the
same information as the state table and is obtained directly from the state table.
Consider a sequential circuit shown in Figure 4. It has one input x, one output Z and two state
variables Q1Q2 (thus having four possible present states 00, 01, 10, 11).
Figure 96. A Sequential Circuit
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The behavior of the circuit is determined by the following Boolean expressions:
Z = x*Q1
D1 = x' + Q1
D2 = x*Q2' + x'*Q1'
These equations can be used to form the state table. Suppose the present state (i.e. Q1Q2) = 00
and input x = 0. Under these conditions, we get Z = 0, D1 = 1, and D2 = 1. Thus the next state of
the circuit D1D2 = 11, and this will be the present state after the clock pulse has been applied.
The output of the circuit corresponding to the present state Q1Q2 = 00 and x = 1 is Z = 0. This
data is entered into the state table as shown in Table 2.
Present State Next State Output
Q1Q2 x=0 x=1 x=0 x=1
00 11 01 0 0
01 11 00 0 0
10 10 11 0 1
11 10 10 0 1
Table 2. State table for the sequential circuit in Figure 96.
The state diagram for the sequential circuit in Figure 96 is shown in Figure 97.
Figure 97. State Diagram of circuit in Figure 96.
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State Diagrams of Various Flip-flops
Table 3 shows the state diagrams of the four types of flip-flops.
NAME STATE DIAGRAM
RS
JK
Table 3. State diagrams of the four types of flip-flops.
You can see from the table that all four flip-flops have the same number of states and transitions.
Each flip-flop is in the set state when Q=1 and in the reset state when Q=0. Also, each flip-flop
can move from one state to another, or it can re-enter the same state. The only difference between
the four types lies in the values of input signals that cause these transitions.
A state diagram is a very convenient way to visualize the operation of a flip-flop or even of large
sequential components.
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SELF-ASSESSMENT #20
1. State table and state diagram represents exactly A. True B. False

the same information.
Table 1. State table

Q0 Q1 x=0 x=1 x=0 x=1
00 00 01 0 0
01 11 10 0 1
10 01 10 0 0
11 00 11 1 1
2. Consider the state table in Table 1. If the circuit is A. True B. False

in the present state 01, for input x=0, the next state
would be 11 and the output is equal to 1.
3. Consider the state table in Table 1. Initially,
present state is 00. For an input x=1, the next state of A. True B. False
the circuit is 01. After the next clock pulse, the
present state would become 10.
Figure 1. State diagram

4. For the state diagram in Figure 1. When the circuit A. True B. False
is in state 00, the label 1/0 means that the circuit will
go to the next state 10.
5. For the same state diagram in Figure 1. If the A. True B. False

present state is 01, and the input is 0, the next state
would be 10.
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6. For the same state diagram in Figure 1. If the
circuit is presently in state 11, it will remain in its
present state 11 if the input is 0 and the output is 0.
SUMMARY
• Flip-flops and latches are the building blocks of a sequential logic circuits.
• There are two (2) types of digital circuits; the combinational logic circuits and the
sequential logic circuits.
• Clocking is an external input signal to the sequential circuits, that prevents it from
changing transition at the prescribe time.
• Transition table is a table that list the behavior of a sequential circuits by showing
its present state and next-state.
• Excitation table is a table that list the required input/s of a flip-flop in order to achieve
a pre-determined transition.
• State diagram is a graphical representation of a state transition table.
• The coming lessons in this module will discuss you on how to design and analyze
synchronous sequential circuits.
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MODULE 8 - Analysis and Design of Sequential Circuits
Introduction
The behavior of a sequential circuit is determined from the inputs, the outputs and the states of
its flip-flops. Both the output and the next state are a function of the inputs and the present state.
Learning Objectives
 describe the behavior of a synchronous sequential circuit;
 discuss the steps in analyzing a synchronous sequential circuit;
 identify the state inputs and next-state equations of a given sequential circuit;
 draw the state diagram of the given sequential circuit;
 construct the state table of the given sequential circuit and;
 discuss the steps in designing a synchronous sequential circuits
Course Materials:
We start with the logic schematic from which we can derive excitation equations for each flip-flop
input. Then, to obtain next-state equations, we insert the excitation equations into the
characteristic equations. The output equations can be derived from the schematic, and once we
have our output and next-state equations, we can generate the next-state and output tables as
well as state diagrams. When we reach this stage, we use either the table or the state diagram to
develop a timing diagram which can be verified through simulation.
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Figure 98. Analysis procedure of sequential circuits
Now let's look at some examples, using these procedures to analyze a sequential circuit.
Example 1. Modulo-4 counter
Derive the state table and state diagram for the sequential circuit shown in Figure 7.
Figure 99. Logic schematic of a sequential circuit.
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SOLUTION:
STEP 1:
First we derive the Boolean expressions for the inputs of each flip-flops in the schematic, in
terms of external input Cnt and the flip-flop outputs Q1 and Q0. Since there are two D flip-
flops in this example, we derive two expressions for D1 and D0:
D0 = Cnt Q0 = Cnt'*Q0 + Cnt*Q0'

D1 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
These Boolean expressions are called excitation equations since they represent the inputs
to the flip-flops of the sequential circuit in the next clock cycle.
STEP 2:
Derive the next-state equations by converting these excitation equations into flip-flop
characteristic equations. In the case of D flip-flops, Q(next) = D. Therefore, the next state
equals the excitation equations.
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'

Q1(next) = D1 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
STEP 3:
Now convert these next-state equations into tabular form called the next-state table.
Present State Next State

Q1Q0 Cnt = 0 Cnt = 1
00 00 01
01 01 10
10 10 11
11 11 00
Each row is corresponding to a state of the sequential circuit and each column represents
one set of input values. Since we have two flip-flops, the number of possible states is four -
that is, Q1Q0 can be equal to 00, 01, 10, or 11. These are present states as shown in the
table.
For the next state part of the table, each entry defines the value of the sequential circuit in the
next clock cycle after the rising edge of the Clk. Since this value depends on the present state
and the value of the input signals, the next state table will contain one column for each
assignment of binary values to the input signals. In this example, since there is only one input
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signal, Cnt, the next-state table shown has only two columns, corresponding to Cnt = 0 and
Cnt = 1.
Note that each entry in the next-state table indicates the values of the flip-flops in the next
state if their value in the present state is in the row header and the input values in the column
header.
Each of these next-state values has been computed from the next-state equations in STEP
2.
STEP 4: The state diagram is generated directly from the next-state table, shown in Figure
8.
Each arc is labelled with the values of the input signals that cause the transition from the
present state (the source of the arc) to the next state (the destination of the arc).
In general, the number of states in a next-state table or a state diagram will equal 2m , where
m is the number of flip-flops. Similarly, the number of arcs will equal 2 m x 2k , where k is the
number of binary input signals. Therefore, in the state diagram, there must be four states and
eight transitions. Following these transition arcs, we can see that as long as Cnt = 1, the
sequential circuit goes through the states in the following sequence: 0, 1, 2, 3, 0, 1, 2, .... On
the other hand, when Cnt = 0, the circuit stays in its present state until Cnt changes to 1, at
which the counting continues.
Since this sequence is characteristic of modulo-4 counting, we can conclude that the
sequential circuit in Figure 7 is a modulo-4 counter with one control signal, Cnt, which enables
counting when Cnt = 1 and disables it when Cnt = 0.
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Example 2
Derive the next state, the output table and the state diagram for the sequential circuit
shown in Figure 10.
Figure 101. Logic schematic of a sequential circuit.
SOLUTION:
The input combinational logic in Figure 10 is the same as in Example 1, so the excitation
and the next-state equations will be the same as in Example 1
Excitation equations:
D0 = Cnt Q0 = Cnt'*Q0 + Cnt*Q0'

D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
Next-state equations:
Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'

Q1(next) = D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'
In addition, however, we have computed the output equation.
Output equation: Y = Q1Q0
As this equation shows, the output Y will equal to 1 when the counter is in state Q1Q0 = 11,
and it will stay 1 as long as the counter stays in that state.
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Next-state and output table:

Q1 Q0 Cnt=0 Cnt=1 Z
00 00 01 0
01 01 10 0
10 10 11 0
11 11 00 1
State diagram:
Figure 102. State diagram of sequential circuit in Figure 101
SELF-ASSESSMENT #21
1. Derive a) excitation equations, b) next state equations, c) a state/output table, and d) a

state diagram for the circuit shown in Figure 1.1.
Figure 1.1
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2. Derive a) excitation equations, b) next state equations, c) a state/output table, and d) a
state diagram for the circuit shown in Figure 1.2.
Figure 1.2
Design of Synchronous Sequential Circuits

The design of a synchronous sequential circuit starts from a set of specifications and
culminates in a logic diagram or a list of Boolean functions from which a logic diagram can
be obtained. In contrast to a combinational logic, which is fully specified by a truth table, a
sequential circuit requires a state table for its specification. The first step in the design of
sequential circuits is to obtain a state table or an equivalence representation, such as a
state diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates. The

design of the circuit consists of choosing the flip-flops and then finding the combinational
structure which, together with the flip-flops, produces a circuit that fulfils the required
specifications. The number of flip-flops is determined from the number of states needed in
the circuit.
The recommended steps for the design of sequential circuits are set out below.
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Figure 103: Flowchart of steps for design of sequential circuit
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Example 1: We wish to design a synchronous sequential circuit whose state diagram is
shown in Figure 13. The type of flip-flop to be use is J-K.
From the state diagram, we can generate the state table shown in Table 9. Note that there
is no output section for this circuit. Two flip-flops are needed to represent the four states and
are designated Q0Q1. The input variable is labelled x.
Present State Next State

Q0 Q1 x=0 x=1
00 00 01
01 10 01
10 10 11
11 11 00
Table 9. State table.
We shall now derive the excitation table and the combinational structure. The table is now
arranged in a different form shown in Table 11, where the present state and input
variables are arranged in the form of a truth table. Remember, the excitable for the JK flip-
flop was derive in Table 1.
Table 10. Excitation table for JK flip-flop
Output Transitions Flip-flop inputs

Q Q(next) JK
0  0 0 X
0  1 1 X
1  0 X 1
1  1 X 0
Table 11. Excitation table of the circuit
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Present State Next State Input Flip-flop Inputs
Q0 Q1 Q0 Q1 x J0K0 J1K1
00 00 0 0X 0X
00 01 1 0X 1X
01 10 0 1X X1
01 01 1 0X X0
10 10 0 X0 0X
10 11 1 X0 1X
11 11 0 X0 X0
11 00 1 X1 X1
In the first row of Table 11, we have a transition for flip-flop Q0 from 0 in the present state
to 0 in the next state. In Table 10 we find that a transition of states from 0 to 0 requires that
input J = 0 and input K = X. So 0 and X are copied in the first row under J0 and K0
respectively. Since the first row also shows a transition for the flip-flop Q1 from 0 in the
present state to 0 in the next state, 0 and X are copied in the first row under J1 and K1. This
process is continued for each row of the table and for each flip-flop, with the input conditions
as specified in Table 10.
The simplified Boolean functions for the combinational circuit can now be derived. The input
variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information
from the truth table is plotted on the Karnaugh maps shown in Figure 14.
Figure 104. Karnaugh Maps
The flip-flop input functions are derived:
J0 = Q1*x' K0 = Q1*x
J1 = x K1 = Q0'*x' + Q0*x = Q0 x
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Note: the symbol is exclusive-NOR.
The logic diagram is drawn in Figure 106.
Figure 106. Logic diagram of the sequential circuit
Example 2. Design a sequential circuit whose state tables are specified in Table 12,
using D flip-flops.0
Table 12. State table of a sequential circuit.

Q0 Q1 x=0 x=1 x=0 x=1
00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1
Table 13. Excitation table for a D flip-flop.
Output Transitions Flip-flop inputs

QQ(next) D
0
0  0
0  1 1
1  0 0
1  1
1
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Next step is to derive the excitation table for the design circuit, which is shown in Table
below. The output of the circuit is labelled Z.
Flip-flop
Present State Next State Input Output
Inputs
Q0 Q1 Q0 Q1 x Z
D0 D1
00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
01 10 1 1 0 0
10 11 0 1 1 0
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1
Table 14. Excitation table
Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the
Boolean expressions, which is shown in Figure 16.
Figure 107. Karnaugh maps
The simplified Boolean expressions are:
D0 = Q0*Q1' + Q0'*Q1*x
D1 = Q0'*Q1'*x + Q0*Q1*x + Q0*Q1'*x'
Z = Q0*Q1*x
Finally, draw the logic diagram.
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Figure 108. Logic diagram of the sequential circuit.
SELF-ASSESSMENT #22
1. Design a sequential circuit specified by Table A below, using JK flip-flops.
Table A

Q0 Q1 x=0 x=1 x=0 x=1
00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1
2. Design the sequential circuit in question 1, using T flip-flops.
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SUMMARY
 Steps in analyzing a synchronous sequential circuits:
- Derive the excitation equation (Boolean Expression)
- Derive the next-state and output equations
- Generate the next-state and output tables
- Generate the state diagram
- Develop the timing diagram
 Steps in designing a synchronous sequential circuits:
- Derive the state diagram
- Obtain the state table
- The number of states may be reduced by state reduction method
- Determine the number of flip-flops needed
- Choose the type of flip-flops to be used
- Derive excitation equations
- Using K-map or any other simplification method, derive the output
functions and the flip-flop input functions.
• The coming lessons in this module will discuss you on how to design and apply
the use of counters in most sequential circuits.
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MODULE 9 - DESIGN AND APPLICATIONS OF COUNTERS
Introduction
One common requirement in digital circuits is counting, both forward and backward.
Digital clocks and watches are everywhere, timers are found in a range of appliances
from microwave ovens to VCRs, and counters for other reasons are found in everything
from automobiles to test equipment.
Although we will see many variations on the basic counter, they are all fundamentally
very similar. In this unit, we will examine the different types of asynchronous and
synchronous counters.
Learning Objectives
 state that the basic counter circuit can be constructed using JK and T flip-flop.
 describe the operation of the synchronous counter.
 draw the circuit diagram, truth table and timing diagram of the synchronous
counter.
 state the applications of multi-stage counter.
 analyze the design of the synchronous counter circuit.
 analyze the design of the synchronous counter using Karnaugh Map.
 state the applications of IC counter
Course Materials:
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Basic Counter Circuit
There are basically two types of counter; asynchronous and synchronous. In an asynchronous
counter, each flip-flop does not trigger exactly in step with the clock pulse. On the contrary, all
flip-flops in a synchronous counter will trigger simultaneously.
The basic counter circuits can be built using T flip-flops or JK flip-flops. The figure below shows
the circuit of a basic counter using the above mentioned flip-flops.
Figure 109: Counter circuit forms by JK flip-flop
A B C D
SET SET SET SET

DT Q DT Q DT Q DT Q
CLK
CLR
Q CLR
Q CLR
Q CLR
Q
Figure 110 Counter circuit forms by T flip-flop
Synchronous Counter
A synchronous counter is an arrangement of flip-flops and logic gates in which all flip-flops are
clocked simultaneously. The advantage is that a synchronous counter does not suffer false states
during its output sequence. On the other hand, there is a requirement for extra gates between
flip-flops to produce the correct sequence.
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Procedure in designing a synchronous counter
Illustrative Example 1: Design a 3-bit binary counter whose state diagram is given:
Figure 111. State Diagram
Step 1: Obtain the state table using the state diagram:
Step 2: Derive the transition table:
Use the equation below to determine the number of flip-flops to be used in the design of the
circuit.
Since there are eight states, the number of flip-flops required would be three. Now we want to
implement the counter design using JK flip-flops. Next step is to develop an excitation from the
state table.
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Step 3. Derive the simplified Boolean expression for each flip-flop input using Karnaugh map.
The 1s in the Karnaugh maps are grouped with "don't cares" and the following expressions for J
and K inputs of each flip-flop are obtained:
J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1 * Q2
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Step 4: Draw the sequential circuit diagram.
Implement the combinational logic from the equations and connect the flip-flops to form the
sequential circuit. The complete logic diagram of a 3-bit binary counter is shown below.
Figure 112. A 3-bit binary counter
Illustrative example 2: Design a 3-bit Gray code counter using JK Flip-flop.

Step 1: Draw the state diagram.
Figure 113. State diagram for a 3-bit Gray code counter

Step 2: Construct the Next-state Table:
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Step 3: Construct the Flip-flop Transition table:
Step 4: Karnaugh Maps

Karnaugh maps for present-state J and K inputs for the 3-bit Gray code counter.
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Step 5: Logic Expressions for the flip-flops inputs
The next-state J and K outputs for the 3-bit Gray code counter.
Step 6: Draw the sequential logic diagram.
Figure 114 3-bit Gray code counter
SELF-ASSESSMENT #23
1. Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, 4. Use JK flip-
flops.
2. Design a counter that has the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6, 7. Use
RS flip-flop.
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3. Design a 3-bit UP/DOWN counter which uses an external input from a switch. That is,
 if SW = ON, the counter should count 0, 1, 2, 3, 4, 5, 6, 7 and repeats

 if is SW = OFF, the counter should count 7, 6, 5, 4, 3, 2, 1, 0 and repeats
Use JK flip-flop.
SUMMARY
 Counter is a specialized synchronous sequential circuit that generates predetermined
number of sequences repeatedly.
 A synchronous counter is a counter wherein all the flip-flops of the counter are clocked
by the same clock signal.
 An asynchronous counter if a counter in which the individual flip-flop of the counters
are clocked at different times.
 The coming lessons in this module will discuss how to design and apply the use of
registers in most digital systems.
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MODULE 10 – DESIGN AND APPLICATIONS OF REGISTERS
Introduction
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a
group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of
the next flip-flop. A typical example of a shift register at work is found within a calculator. As you
enter each digit on the keyboard, the numbers shift to the left on the display. In other words, to
enter the number 156 you must do the following. First, you press and release the “1” on the
keyboard; a “1” appears at the extreme right on the display. Next, you press and release the “5”
on the keyboard causing the “1” to shift one place to the left allowing for “5” to appear on the
extreme right; “15” appears on the display. Finally, you press and release the “6” on the keyboard;
“156” appears on the display.
In this module, we are going to learn the basic types of shift registers, such as Serial In - Serial
Out, Serial In - Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out, and bidirectional
shift registers. A special form of counter - the shift register counter, is also introduced.
Learning Objectives
 draw a basic shift register circuit using JK flip-flop and D flip-flop
 describe the basic function of the register
 identify the basic forms of data movement in shift registers
 describe the operation of serial in/serial out(SISO), serial in/parallel out(SIPO), parallel
in/serial out(PISO), and parallel in/parallel out(PIPO) shift registers
 state the applications of shift register in arithmetic operations; division and multiplication.
 construct a ring counter from a shift register
 state the application of shift register IC
Course Materials:
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SHIFT REGISTERS
Shift registers are very important devices in applications that involve the storage and the transfer
of data in a digital system. The difference between a register and a counter is that the register
has no specified series of states. A register is solely used for storing and shifting data (that is 1s
and 0s) that have been entered from an external source.
The storage capacity of a register is the number of bits (of digital data) it can retain. Each stage
of a shift register represents the one bit of information it can store, so the number of stages in a
shift register represents the total storage capacity of a register. Shown below is how a Flip-Flop
is used as a storage device.
Figure 115. D flip-flop showing the response of the output with the change of input and
rising edge of the clock
It can be seen that when the clock is going HIGH, that is on a rising edge, the input on the D
becomes the output. There is various type of shift register, and shown below are simplified
diagrams of the most commonly used.
Figure 116. Different modes of operation of shift registers
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Serial in, Serial out Shift Registers
This type of shift register accepts data serially, that is, one bit at a time on a single line. It produces
the stored information on its output also in serial form.
Figure 117. An example of serial in serial out shift register
The diagram above shows a shift register that will hold four bits at any one time. On the rising
edge of a clock pulse, the data is fed into the register. After four clock pulses the register is full
and the next pulse will start to release the data in the order in which it entered.
Shown below is a 5-bit shift register and the corresponding timing diagram.
Figure 118. A serial in serial out shift register that can hold 5-bits of information
The timing diagram is shown below. The main point to note is the data shifting through the
registers.
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Figure 119. Timing diagram of a five-bit serial in serial out shift register
Shown above are the values contained in each Flip-Flop after five clock pulses.
Serial in, Parallel out Shift Registers

Data is entered serially into this type of register as was described in the last section. The
difference is the way in which the Data bits are taken out of the register. In a parallel output
register, the output of each stage is available. Once the data bits are stored, each bit appears on
its respective output line, and all bits are available simultaneously, rather than on a bit by bit basis
as was the case for the serial output. Shown below is a 4-bit serial input parallel output register.
Figure 120. A serial in parallel out shift register
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The above Serial Input Parallel Output (SIPO) shift register has the summarized symbol shown
below.
Figure 121. Logic symbol of a serial in parallel out shift register
Below is shown the timing diagram for this 4-bit serial input parallel output shift register.
Figure 122. Timing diagram of a four-bit serial in parallel out shift register
This looks very similar to the serial-input serial-output timing diagram, but in this timing diagram
the clock pulse signifies that the serial data is on the output.
Parallel-in, Serial-out Shift Register
Here the data is entered simultaneously into the respective stages on parallel lines rather than on
a bit by bit basis as is the case with the serial input shift register. The serial output appears at the
output terminal one bit at a time with each new bit coinciding with another clock pulse. The
diagram below shows a 4-bit parallel-in serial-out shift register.
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Figure 123. A 4-bit parallel-in serial-out shift register.
Notice that there are four input Lines. The key feature of this shift register is the SHIFT / LOAD
line. When this line is LOW then the AND gates on the right hand side of each grouping is enabled
and thus any parallel data can get through to the Flip-Flops. When this line is HIGH then the AND
gate on the left hand side of each grouping is enabled and the data can flow through the Flip-
Flops to be seen as a serial data output. Like before this gate is summarized into a more
convenient logic symbol as shown below.
Figure 124. Logic symbol of a 4-bit parallel-in serial-out shift register.
Shown below is the corresponding timing diagram.
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Figure 125. Timing diagram of a 4-bit parallel-in serial-out shift register.
SUMMARY
 A flip-flop is a single (1) bit memory cell which can be used for storing the digital data.
 A register is used to hold a number of bits depending on how many flip-flops are cascaded
connect.
 Counter is different from a register, since a register store string of bits at no particular
sequence unlike a counter does.
 Parallel mode transfers allow us to move a number of bits simultaneously whereas Serial
mode transfers a bit one at a time.
 A shift register allows binary data to move within the register from one flip-flop to another.
 There are four (4) mode of operations of a shift register.
- Serial Input Serial Output (SISO)
- Serial Input Parallel Output (SIPO)
- Parallel Input Serial Output (PISO)
-Parallel Input Parallel Output (PIPO)
 The 74LS194SR is a four (4) bit Shift register that is widely used in different applications
of digital systems.
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ANSWER KEY TO SELF-ASSESSMENTS
Self-assessment #1
1. True 6. False
2. True 7. True
3. True 8. The values may vary over a continuous range.
4. True 9. It takes the digital information from an audio CD and converts it to a usable form.
5. True 10. that vary in discrete steps in proportion to the values they represent
Self-assessment #2
1.
i. The correct symbol for an AND gate is D.

ii. The correct symbol for a NOT gate is A.
iii. The correct symbol for a NOR gate is E.
iv. The correct symbol for a NAND gate is B.
v. The correct symbol for an OR gate is C.
2.
i. AND gate.
Inputs Output
A B Q
0 0 0
0 1 0
1 0 0
1 1 1
177 | P a g e
ii. NOR gate.
Inputs Output
A B Q
0 0 1
0 1 0
1 0 0
1 1 0
iii. NAND gate.
Inputs Output
A B Q
0 0 1
0 1 1
1 0 1
1 1 0
iv. OR gate.
Inputs Output
A B Q
0 0 0
0 1 1
1 0 1
1 1 1
SELF-ASSESSMENT #3
a) 4 b) 2 c) Pin 10 d) 7 & 14 e) NOR
178 | P a g e
SELF-ASSESSMENT #4
1.
Inputs Outputs
A B K Q
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1
2.
Inputs Outputs
A B C F G Q
0 0 0 1 1 1
0 0 1 0 0 1
0 1 0 1 1 1
0 1 1 0 1 1
1 0 0 1 1 0
1 0 1 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
179 | P a g e
3.
Inputs Outputs
A B C D E F G Q
0 0 0 1 1 0 1 1
0 0 1 1 0 0 1 1
0 1 0 1 1 1 0 1
0 1 1 1 0 1 1 1
1 0 0 0 1 0 1 1
1 0 1 0 0 0 1 1
1 1 0 0 1 0 0 0
1 1 1 0 0 0 1 1
SELF-ASSESSMENT #5:
i. Expression A is correct for an AND gate.

ii. Expression D is correct for a NOT gate.
iii. Expression B is correct for a NOR gate.
iv. Expression E is correct for a NAND gate.
v. Expression C is correct for an OR gate.
2. X= B
Y = A.B
Z = A.B
180 | P a g e
SELF-ASSESSMENT #6
1. Q  A.B.C  A.B.C  A.B.C
2. Q  A.B.C  A.B.C  A.B.C
3. Q  A.B.C.D  A.B.C.D  A.B.C.D  A.B.C.D
SELF-ASSESSMENT #7
1. Q  C  (A  B)
2. Q  (A  B).C  (A  B)  (C  D)
3. Q  A.B  C  (A.B).(D.C)
4. Q  (A.B).C  (A.B).(C  D)
SELF-ASSESSMENT #8
1.
Q  (A  B).(A.B)  A.B
Q  (A  B)  (A.B)  A.B
Q  (A  B)  (A.B)  A.B
Q  A  B  A.B  A.B
Q  A.(1 B)  (B  A.B)
Q  A.1 (B  A)
Q  A B A
Q  B  (A  A)
Q  B1
Q 1
181 | P a g e
2.
Q  A.C.B.D  C.D
Q  A.C.B  D  C  D
Q  A.C.B  D  C
Q  (A  C).B  D  C
Q  A.B  B.C  D  C
Q  A.B  C.(B  1)  D
Q  A.B  C.1 D
Q  A.B  C  D
SELF-ASSESSMENT #9
1. Q  A.B  B.C
182 | P a g e
2. Q  A  B  A.(C  B)
B
Q
183 | P a g e

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MODULE 1 – Introduction to Digital System

Analog Signal (Temperature)

Figure 1. Graphical representation of an analog signal

Disadvantage of Analog Systems

A Digital Signal (Binary)

Figure 2. Graphical representation of digital signal

Advantage of Digital Systems

Table 1. Comparison between analog and digital signals

2 Analog signal has a continuous nature. Digital signal has a discrete

3 Analog signal is generated by transducers and Digital signal is generated by A to

Digitization/Quantization of Analog Signals

Figure 4. The resulting digitalized waveform

Consider the case where values are represented by voltage signals:

Figure 5. Decimal System and Binary System Equivalency diagram

• Good designs should guard against noisy environments to prevent misinterpretation

3. Greater accuracy and precision are possible with digital techniques.

4. A digital quantity has a discrete set of values.

5. The real world is mainly analog.

6. Temperature variation is normally a digital quantity.

The values may vary over a continuous range.

9. What is a digital-to-analog converter?

10.Digital representations of numerical values of quantities may BEST be

that vary in discrete steps in proportion to the values they represent.

A value of each digit in a number can be determined using

 The position of the digit in the number

available in the number system).

After successful completion of this module, you should be able to:

 understand how integers and fractional numbers are represented in binary

bases (binary, octal, hexadecimal)

 understand signed numbers and unsigned numbers

 understand number representations in two’s complement

 perform arithmetic operations in every base

 understand the method of floating point number representation in IEEE format

Binary Numbers and Arithmetic

Decimal Number System

10n ….. 102 101 100  10-1 10-2 ….. 10-n

= (1 * 102) + (2 * 101) + (3 * 100) + (4 * 10-1) + (5 * 10-2)

COUNT DECIMAL BINARY

Binary to Decimal conversion

Ex 1: Convert the binary number 10012 to a decimal number. [910]

Ex 2: Convert the binary number 1110112 to a decimal number. [5910]

Binary Representation of Fractional Numbers

2n ….. 22 21 20  2-1 2-2 ….. 2-n

2-2 = 1/22 = 1/4

2-3 = 1/23 = 1/8

2-4 = 1/24 = 1/16

The same process is used when converting decimal fractions.

Ex 3: Convert the binary number 0.11012 to a decimal number. [0.812510]

Ex 4: Convert the binary number 11001.0112 to a decimal number. [25.37510]

Alternative method of converting Binary fractions into decimal numbers

Decimal to Binary conversion

Ex 5: Convert the decimal number 123 to a binary number

Ex 7: Convert the decimal number 46 to a binary number.

Ex 8: Convert the decimal number 0.75 to binary. [0.1102]

Ex 9: Convert the decimal number 0.875 to binary. [0.11102]

Ex 10: Convert the decimal number 27.125 to binary. [11011.0012]

There are four basic rules for adding binary digits