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Extendable Bidirectional DC–DC Converter With Improved Voltage Transfer

Ratio and Reduced Switch Count

Article in IEEE Journal of Emerging and Selected Topics in Industrial Electronics · December 2022
DOI: 10.1109/JESTIE.2022.3233295

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295
Extendable Bidirectional DC-DC Converter with
Improved Voltage Transfer Ratio and Reduced
Switch Count
V. Seshagiri Rao, IEEE Student Member., S. Tapaswi and Kumaravel S., IEEE Senior Member.
Abstract— Bidirectional dc-dc converter (BDC) plays an
important role in battery-based applications. This paper
presents an extendable BDC using 8+5n components, including
3+n MOSFETs, where n is the number of stages. The detailed
analysis of single-stage of the proposed converter is discussed.
The voltage transfer ratio (VTR) of the converter during the
step-up and step-down modes is derived. The effect of parasitic
elements on the VTR and the efficiency is discussed. The state-
space model is derived, and the open-loop transfer functions,
� 𝑯𝑯 and 𝒗𝒗
�𝑯𝑯 ⁄𝒅𝒅
𝒗𝒗 � 𝑳𝑳 for both the modes are obtained. These
�𝑳𝑳 ⁄𝒅𝒅
transfer functions are validated using circuit level simulation.
The operating modes of the converter are validated using a
300 W, 650 V, and 50 kHz prototype, and the experimental
results are presented. Using the derived transfer functions, the
PI controllers are designed using Ziegler–Nichols method for
step-up and step-down modes. Using the Xilinx system
generator (XSG), the designed controllers are implemented, and
the experimental closed-loop results are presented. The
performance comparison shows that the VTR of the single-stage
converter using four MOSFETs is significantly improved
compared to the other converters which achieve the quadratic
VTR. Each extended stage requires a single MOSFET along
with 4 passive components.
Keywords— bidirectional converter - battery storage – e-
mobility – high gain – reduced switch count – voltage transfer ratio
I. INTRODUCTION
The attraction towards the fossil fuel-based electricity
generation methods decreases day-by-day due to the factors
such as global warming, increased fuel price, etc. Hence,
modern energy devices like solar PV and batteries are used in
various applications such as UPS, DC microgrid, low-power
e-mobility devices like E-bikes, 2- & 3-wheel scooters, etc.
A battery storage is preferred as a primary storage in most of
the applications because of its compactness, high power
density and low cost compared to other storage devices like
ultra-capacitor and flywheel. Modern batteries, like Li-ion
and Ni-Cad, have a higher demand nowadays. Power
electronic interface is mandatory to perform the charging and
the discharging process in any battery. Hence, a bidirectional
dc-dc converter (BDC) plays a major role in the utilization of
the battery [1-2]. The required features of a well-designed
BDC are continuous source current, common ground
between the input/output ports, capable to produce high VTR
with reduced voltage and current stress and should utilize a
minimum number of components (especially switches).
Several isolated [3-6] and non-isolated [7-24] type BDC
topologies are presented in the literature. In [3], a “dual active
bridge (DAB)” with a hybrid modulation strategy is reported.
Although the dual-side flow back current is minimized, the
current stress of the switches is higher. To overcome this
current stress, a dual-bridge series resonant converter is
reported in [4]. The peak to average current ratio of the high
frequency transformer is 1.6. However, the voltage across the
resonant capacitor increases when the DC-bus voltage is
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increased. The converter reported in [5] has a peak to average
current ratio of unity, but the converter does not have bi-
directional capability. A bidirectional buck–boost current-fed
isolated dc–dc converter is reported in [6], and it overcomes
the limitations of the converter reported in [5]. Nevertheless,
the switch count is higher compared to the other topologies.
Even though galvanic isolation is provided in the DAB and
the other related converters [3-6][26][29], more components,
high leakage current and bulk in size limit the utilization of
such converters in the aforementioned applications.
In non-isolated BDC type, a boost BDC is presented in [7].
The VTR of the converter is 1/(1-DH) during step-up, and it is
DL during the step-down operations, where DH and DL are the
corresponding mode duty ratios. Here, achieving a higher
VTR is limited due to the effect of parasitic. A voltage
doubler-based BDC is reported in [8] with a VTR of
(1+DH)/(1-DH), and the similar VTR BDCs are reported in [9-
10]. Although a lesser component is used in these converters,
limited voltage gain is a major drawback. BDCs with a VTR
of 2/(1-DH) is reported in [11-14]. These converters produce
only twice the VTR of the boost BDC. In [15], a BDC with a
VTR of (2+DH)/(1-DH) by adding a switched capacitor (SC)
cell in the converter described in [9]. However, it does not
have common ground. A BDC is reported in [16] with sixteen
components, including eight switches. It produces a VTR of
3/(1-DH). In [17] an extendable BDC is reported with a VTR
of (3+DH)/(1-DH), but it lacks the common ground. A BDC
with switched inductor (SL) and SC is reported in [18] with a
VTR of 4/(1-DH), but a greater number of switches are used.
Researchers have tried to suggest quadratic gain-based
BDC topologies [19–21][25][27-28]. In a BDC in [19] with a
VTR of 1/(1-DH)2, one of the switches is exposed to voltage
stress more than the output voltage. In the case of the BDCs
disclosed in [20–21] with the VTR of 1/(1-DH)2, the voltage
stress on one of the switches is equal to the output voltage.
The BDC in [25] achieves the VTR of 1/(1-DH)2, but pulsating
source current is a key demerit. Recently, a BDC with a VTR
of (3-DH)/(1-DH)2 is described in [22], and it uses 13
components including six switches. This converter uses more
active components and also does not have common ground.
Although the voltage stress across the switches is lower in
the BDCs described in [7-14], their voltage gain is
constrained. The BDCs described in [15–18] generate a
comparatively better VTR, but a greater number of active
components are used. In [19-21], the converters produce better
VTR using nominal components, but the voltage stress across
the switches is higher. However, the converters' [12], [17-19]
source current is pulsing in nature and converters' [8], [17]
lack of a common ground. The BDC reported in [22][24]
produce improved VTR with lower voltage stress across the
switches. However, higher number of switches and no
common ground are the drawbacks in these topologies.
To overcome the above-said drawbacks, a converter is
proposed in this paper that produces improved VTR by using
reduced number of switches, lower voltage stress across the
switches, continuous source current and common ground.
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

S-L-C-2D D
11 C3
network D12 D1n
S11 S12 S1n S2 S3
L1 L21 L22 L2n L3
L
O VH
C2 CH A
VL C11 C12 C1n
D01 D02 D0n D
S4
Stage 1 Stage 2 Stage n

Fig. 1 Proposed BDC topology for n-stage

State-1: In this state, the S4 is turned ON, and the equivalent
The structure of the proposed BDC converter with n-stage is
shown in Fig. 1. Each stage of the n-stage structure is derived circuit for this state is shown in Fig. 3(a). The equivalent
using an active impedance network, namely the S-L-C-2D circuit shows that the inductor L1 is charged from the source
network (as shown in Fig. 1) which consists of a MOSFET, D1 C3
two diodes, an inductor, and a capacitor. The basic stage, i.e., S1 S2 S3
for n = 1, the BDC converter utilizes 13 components, L1 L2 L3
SD1 SD2 SD3
including 4 MOSFETs. Whereas n = 2 requires 18 L
components, including 5 MOSFETs. Although the number of VL D0 C1 C2 CH
O VH
S4 A
components is 18 in the second stage, only one more D

MOSFET is required in addition to the existing 4 MOSFETs.

The main attraction of the proposed n-stage converter
structure is that in each additional stage, the total number of Fig. 2 SSBDC during step-up mode
components increases at rate of five per stage, which includes voltage through the path VL-L1-D1-S4. At the same time, the
a single MOSFET. In this paper, the detailed analysis of the inductor L2 is also charged from the capacitor C1 with a
proposed ‘single stage BDC’ (SSBDC) is carried out. The voltage of VC1 through the path C1-L2-S4 and the inductor L3
SSBDC achieves symmetrical VTR of 45:1. During step-up is charged from the capacitor C2 with a voltage of VC2-VC3
mode, the VTR i.e., VH/VL at DH = 80% is 45:1 and during step through the path C2-L3-C3-S4. The power for load is provided
down mode, the VTR i.e., VL/VH at DL =20% is 1:45. by the capacitor CH. Fig. 4(a) shows the inductors analytical
The operation of the converter is discussed in Section II, waveforms. The voltage and current equations are derived as
and the component design is carried out in Section III. The
dynamic model of the SSBDC is reported in Section IV. V=
L1 VL ;V=
L2 VC1 ;V=
L3 VC 2 − VC 3
Performance analysis of the SSBDC with parasitic elements is (1)
−iL 2 ; iC 2 =
iC1 = −iL 3 ; iC 3 =
iL 3 ; iCH =
−iH
presented in Section V. The performance comparison is
reported in Section VI. Analysis of extendable structure of the State-2: In this state, the S4 is turned OFF, and the equivalent
proposed BDC is carried out in Section VII. In Section VIII, circuit for this state is given in Fig. 3(b). The inductor L1 is
the experimental results of a 300 W, 50 kHz for VH = 650 V discharged of its stored energy along with the input source VL
and VL = 48 V hardware prototype of the proposed SSBDC are to C1 through the path of VL-L1-SD1-C1. The L2 is discharged
presented. Finally, the conclusion is reported in Section IX. to the capacitor C2 through the path of C1-L2-SD2-C2. The
II. SINGLE STAGE BIDIRECTIONAL CONVERTER inductor L3 is discharged simultaneously into the capacitor C3
through the path L3-C3-S2 and to the load through the path C2-
The proposed SSBDC for n = 1 consists of 13 L3-SD3-CH. The voltage and current equations corresponding
components, i.e., four semiconductor switches, two diodes, to this state are derived as in (2).
three inductors and four capacitors as shown in Fig. 2. It
performs two modes of operation: i) step-up mode and ii) D1 C3
S1 S2 S3
step-down mode. The step-up mode utilizes the MOSFET S4
L1 L2 L3
and four diodes including the body diodes of three other SD1 SD2 SD3
MOSFETs. Similarly, step-down mode utilizes three VL L
O VH
C1 C2 CH
MOSFETs and two diodes, including the body diode of S4. D0 S4 A
D

A. STEP-UP MODE
In this mode, the power is delivered from the low voltage
(a)
side (i.e., VL) to the high voltage side (i.e., VH). The switches
S1, S2 and S3 are permanently turned OFF, and their D1 C3
S1 S2 S3
corresponding body diodes are used in the operation. The
L1 L2 L3 SD3
diode D0 is in the reverse biased condition during the entire SD1 SD2
mode of operation. The switch S4 alone is controlled to VL L
O
C1 C2 CH VH
achieve the step-up voltage across the load with the step-up D0 S4 A
D
duty ratio DH. Based on the ON and OFF conditions of the
switch S4, there are two states (state 1 & state 2) are presented
in this mode.
(b)
Fig. 3 Equivalent circuits during step-up mode (a) state 1(b) state 2

© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY CALICUT. Downloaded on December 31,2022 at 08:52:38 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

VL − VC1 ;VL 2 =
VL1 = VC1 − VC 2 ;VL 3 =
−VC 3 are energized from the supply voltage with a voltage of VH-
(2) VC2 through the path of VH-S3-L3-C2. At the same time, the
iC1 = iL1 − iL 2 ; iC 2 = iL 2 + iC 3 − iL 3 ; iCH + iH = iL 3 − iC 3 inductor L2 is energized from the C2 with a voltage of VC2-
VC1 through the path of C2-S2-L2-C1. The inductor L1 is
By applying volt-second balance to the inductors, the voltage charged from the capacitor C1 with a voltage of VC1-VL
across the capacitors is computed as, through the path of C1-S1-L1-VL. Fig. 4(b) shows the
VL VL VL DH analytical waveforms of these inductors. The voltage and
=VC1 = ;VC 2 = 2
;VC 3 (3) current equations corresponding to this state are expressed as,
1 − DH (1 − DH ) (1 − DH ) 2
VC1 − VL ;VL 2 =
VL1 = VC 2 − VC1 ;VL 3 =
VH − VC 2 ;VH =
VC 2 + VC 3
Using (3), the output voltage of the proposed SSBDC during (5)
the step-up mode of operation is derived as, iC1 = iL 2 − iL1 ; iC 2 = iL 3 − iL 2 + iC 3 ; iCL = iL1 − iL

VL (1 + DH ) State-4: In this state, the S1, S2 and S3 are turned OFF, and
VH = (4) the equivalent circuit diagram of the converter during this
(1 − DH ) 2
state is shown in the Fig. 6(b). The equivalent circuit indicates
that the inductor L3 de-energizes energy to the capacitor C2
S4 Ts Ts
S1,S2, with a voltage of VC2-VC3 through the path of L3-C2-SD4-C3.
(1-DH)Ts S3 DLTs (1-DL)Ts
vL3
DHTs At the same time, the inductor L2 is de-energized to the
vL3 capacitor C1 through the path of SD4-L2-C1. Whereas the
VC2 -VC3 V H- VC2
inductor L1 de-energizes to the load through the path of D0-
vL2
V H- VC2
vL2 VC2 -VC3 L1-VL. The current and voltage equations are derived as,
VC1 VC2 -VC1 −VL ;VL 2 =
VL1 = −VC1 ;VL 3 =
VC 3 − VC 2
VC2 -VC1 VC1 (6)
vL1 vL1 iL 2 ; iC 2 =
iC1 = iL 3 ; iC 3 =
−iL 3 ; iCL =
iL1 − iL
VL V C1- VL
VC1 -VL VL
D1 C3
iL1 ILP11 iL1 ILP11
IL10 IL10 S1 S2 S3
L1 L2 L3
iL2 ILP21 iL2 ILP21
IL20 IL20 L
O C1 C2 VH
VL A
CL D0 S4 SD4
iL3 ILP31 ILP31 D
IL30 iL3 IL30

t0 t1 t2 t t0 t1 t2 t
(a)
state 1 2 state 3 4
(a) (b) D1
Fig. 4 Analytical waveforms (a) step-up mode (b) step-down mode S1 S 2 C3 S3
L1 L2 L3
B. STEP-DOWN MODE
In this mode, the power is delivered from the high L
O
CL D 0 C1 C2 VH
VL A S4 SD4
voltage side to the low voltage side, as shown in Fig. 5. The D
switch S4 is permanently OFF during this mode, but its
corresponding body diode is used. The diode D1 is reverse
biased during the entire mode of operation. The switches S1, (b)
Fig. 6 Equivalent circuits during step-down mode (a) state 3 (b) state 4
S2 and S3 are controlled to achieve the step-down operation
with the step-down duty ratio DL. During the operation, these By applying volt-second balance to the inductors, the
three switches are either turned ON or turned OFF corresponding capacitor voltages are derived as,
simultaneously. Based on the ON and OFF conditions of the
switches, two states (state 3 & state 4) are presented. VH DL VH VH (1 − DL )
= VC1 = ;VC 2 = ;VC 3 (7)
2 − DL 2 − DL 2 − DL
D1 C3
S1 S2 S3 The output equation of the converter during the step-down
L1 L2 L3 mode is expressed as,
L VH DL 2
O
CL D0 C1 S4
C2 VH VL = (8)
VL A SD4 2 − DL
D

III. CONVERTER DESIGN

Fig. 5 SSBDC during step-down mode A proper design procedure is followed for the selection
of various components present in the proposed SSBDC by
State-3: In this state, the switches S1, S2 and S3 are turned ON considering both the modes of operation. The output power
at a time, and the equivalent circuit for this state is shown in of 300 W, the VL of 48 V and the VH of 650 V are considered
Fig. 6(a). The equivalent circuit indicates that the L3 and C3
for the selection of components. The switching frequency of

© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY CALICUT. Downloaded on December 31,2022 at 08:52:38 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

the converter is considered 50 kHz. The design of various
components of the SSBDC converter for the step-up
operation is described as follows. By considering the current
ripple ∆iL of the inductors L1, L2 and L3 during the ON-state
of the switch, the inductance of L1, L2, and L3 is derived as,
maximum value of the voltage and current stress which are
experienced by the component either during step-up or step-
down mode. The final design of the SSBDC converter is
given in Table III.
TABLE II VOLTAGE AND CURRENT STRESSES DURING STEP-DOWN MODE

VL DH VL DH VL DH Current stress
Components Voltage stress
=L1 = ; L2 = ; L3 (9) Average RMS
f s ∆I L1 f s (1 − DH )∆I L 2 f s (1 − DH )∆I L 3 VH DL
Diode D0 I L (1 − DL ) I L (1 − DL ) VD 0 =
2 − DL
The average inductor currents IL1, IL2 and IL3 are derived as,
Body- I L (2 + DL )(1 − DL ) I L (2 + DL ) 1 − DL VH
SD4 VSD 4 =
I H (1 + DH ) I H (1 + DH ) Diode 2 − DL 2 − DL 2 − DL
I L1 = 2
; I L2 = ; I L3 I H (10)
(1 − DH ) 1 − DH VH DL
S1 I L DL I L DL VS 1 =
2 − DL
The capacitors C1, C2, C3 and CH are derived as
I L DL 2 I L DL DL VH
Switch S2 VS 2 =
I H DH (1 + DH ) I H DH I H DH I H DH 2 − DL 2 − DL 2 − DL
=C1 = ; C2 = ; C3 = ; CH (11)
(1 − DH ) f s ∆VC1 f s ∆VC 2 f s ∆VC 3 f s ∆VCH I L DL 2 I L DL DL VH
S3 VS 3 =
2 − DL 2 − DL 2 − DL
where ∆VC is the voltage ripple across the capacitor. The
TABLE III SPECIFICATIONS OF SSBDC
appropriate switches and diodes are selected based on the
voltage and current stress of each component, and the Diodes D0 and D1 FFSH2065B
Switches S1, S2, S3 and S4 C3M0025065K
expression of those stresses is listed in Table I.
Inductors L1, L2 and L3 1 mH, 3 mH and 5 mH
TABLE I CURRENT AND VOLTAGE STRESSES DURING STEP-UP MODE C1 , C2 , C3 22 µF
Capacitors
CH ,CL 100 µF
Components Current stress Voltage stress Switching frequency fS 50 kHz
Average RMS Rated power 300 W
I H DH (1 + DH ) I H (1 + DH ) DH VL VL and VH 48 V and 650 V
Diode D1 VD1 =
(1 − DH )2 (1 − DH )
2
1 − DH
IV. DYNAMIC MODELING OF SSBDC
I H DH (3 − DH ) I H (3 − DH ) DH VL
Switch S4 VS 4 = To optimize the converter dynamics and to improve the
(1 − DH ) 2 (1 − DH ) 2 (1 − DH ) 2 converter stability analysis, a state-space model is derived. In
I H (1 + DH ) I H (1 + DH ) (1 − DH ) VL the step-up mode, VL(t) is the input variable, and VH(t) is the
SD1 VSD1 = output variable and dH(t) is the control variable. iL1(t), iL2(t),
1 − DH (1 − DH )
2
1 − DH
iL3(t), VC1(t), VC2(t), VC3(t) and VCH(t) are the state variables.
I H (1 − DH ) VL
Body-
SD2 IH VSD 2 = Fig. 3(b) shows that when the switch S4 is turned-OFF, the
Diode 1 − DH (1 − DH ) 2 capacitors C2, C3 and CH form a series path. So, the voltage
I H (1 − DH ) VL of those capacitors becomes zero, i.e., VC2+VC3-VCH = 0 [23],
SD3 IH VSD 3 = therefore it does not fit within the dynamic modeling
1 − DH (1 − DH )2
framework. To find the state trajectory, a loop resistance r
The design of various components of the SSBDC converter with a value of 0.1 is added to that loop. The state-space
for the step-down operation is described as follows. The final model of the system for step-up mode is represented as,
derived inductance values of L1, L2, and L3 are given as, x
= A1 x + B1u ; y = C1 x (15)
2
VH DL (1 − DL ) VH DL (1 − DL ) VH DL (1 − DL )
L1 = ; L2 = ; L3 (12) where x = [iL1 iL2 iL3 vC1 vC2 vC3 vCH]T; y = [vH]; vH = [0 0 0 0 0
(2 − DL ) f s ∆I L1 (2 − DL ) f s ∆I L 2 (2 − DL ) f s ∆I L 3
0 1]. The final state-space model of the converter for the step-
The average inductor currents IL1, IL2 and IL3 are written as, up mode of operation is given in (17). During step-down
mode, VH(t) is the source variable and VL(t) is the load
I L DL 2 variable. dL(t) is the control variable. iL1(t), iL2(t), iL3(t), VC1(t),
L ; IL2
I L1 I=
= L ; I L3
I L D= (13)
(2 − DL ) VC2(t), VC3(t) and VCL(t) are the state variables. For
simplification purposes, the value of capacitance of different
The capacitors C1, C2, C3, and CL are expressed as, capacitors is considered equally, i.e., C1 = C2 = C3 = CH = CL
= C. The state-space model of the system for step-down mode
I L DL ( DL − 1) I L DL 2 (1 − DL ) is represented as,
C1 = ; C2 ;
f s ∆VC1 (2 − DL ) f s ∆VC 2
(14)
I L DL 2 (1 − DL ) I L DL 2 (1 − DL )
x
= A2 x + B2u ; y = C2 x (16)
C3 = ; CL
(2 − DL ) f s ∆VC 3 (2 − DL ) f s ∆VCL where, x = [iL1 iL2 iL3 vC1 vC2 vC3 vCL]T; y = [vL]; vL = [0 0 0 0 0
0 1]. The final state-space model of the converter for step-
The voltage and current stress of the switches and the diodes
down mode of operation is given in (18). Using (17) and (18),
are listed in Table II. Though the design of the SSBDC
converter during the step-up and step-down modes is the small-signal transfer functions �𝑣𝑣𝐻𝐻 ⁄𝑑𝑑̂𝐻𝐻 , and 𝑣𝑣�𝐿𝐿 ⁄𝑑𝑑̂𝐿𝐿 during
discussed, the components are selected by considering the step-up and step-down modes are derived and given in (19)

© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY CALICUT. Downloaded on December 31,2022 at 08:52:38 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

 DH − 1   1 
 0 0 0
L1
0  0 0 0 0 L
0 0 0 0 
   1 
 1 DH − 1   1 
 iˆ   0 0 0 0 0  1  0 0 0 0 0 0 
 L1   L2 L2   iˆL1     L2   I L1 
 iˆ      L1  I 
DH −1 ˆ   1
 L2   0 0 0 0 0   iL 2   0  0 0 0 0 0 0   L2 
 iˆ   L3 L3  ˆ
 iL 3    L3   I L3  (17)
 L3      0   −1   ˆ
 vˆC1  = 1 − DH −1
0 0 0 0 0   vˆC1  +  0  vˆL +  0 0 0 0 0 0   VC1  d H
   C C 
 vˆ    C  VC 2 
 vˆC 2   1 − DH − DH DH − 1 DH − 1 DH − 1 DH − 1 1 − DH   C2 
 0  −1 −1 1 1 1 1 −1  
   0 0 + +   vˆC 3    0 0 + +  VC 3 
 vˆC 3   C C rC CR rC CR rC  vˆ   0   C C rC CR rC CR rC  V 
   1 DH − 1 DH − 1 DH − 1 DH − 1 1 − DH   CH 
 0   1 1 1 1 −1   CH 
vˆCH   0 0 0 + +  0 0 0 0 + + 
 C rC CR rC CR rC   rC CR rC CR rC 
 1 − DH 1 − DH − DH D − 1  −1 −1 −1 1
 0 0 0 0 + H  0 0 0 0 + 
 rC rC rC + CR rC   rC rC rC + CR rC 

 DL −1 
 0 0 0 0 0  1 
L1 L1   0 0 0 0 0 0
  L1
 −1 DL   0   
 iˆ   0 0 0 0 0   0   1 
 L1   L2 L2   iˆL1     0 0 0 0 0 0  I 
 L2   L1 
 iˆ   r ( DL − 1) −1 1 − DL   iˆ   DL 
 L2   0 0 0 0   L2     r −1   I L2 
 iˆ   L3 L3 L3 L
  iˆL 3   3   0 0
L3
0 0
L3
0  I  (18)
 L3   − D    0     L3 
 vˆC1  =  L 1
0 0 0 0 
0  C1vˆ  +   ˆ
v H +  −1  VC1  dˆL
   C C   vˆ   DL   0 0 0 0 0 0  V 

 vˆC 2     C 2   rC  C   C2 
− DL 1 − DL − DL   V 
   0 0 0   vˆC 3    −1 −1 −1
 vˆC 3   C C rC rC   vˆ   DL   0 0 0 0  C 3 
 ˆ     CL   rC   C rC rC  VCL 
DL − 1 − DL − DL
 vCL   0 0 0 0     1 −1 −1 
 C rC rC   0   0 0 0 0
 C rC rC 
 1 −1 
 0 0 0 0 0   0
 0 0 0 0 0 0
 C CR 

vˆH −1.32 ×104 s 6 − 1.32 ×108 s 5 + 2.67 ×1012 s 4 − 9.49 ×1014 s 3 + 9.14 ×1018 s 2 − 1.69 ×1021 s + 2.49 ×1024
= 7 (19)
dˆH s + 1.49 ×10 s + 5.40 ×10 s + 7.74 ×10 s + 7.29 ×10 s + 9.59 ×10 s + 5.54 ×10 s + 5.92 ×10
4 6 6 5 10 4 12 3 16 2 17 20

vˆL 2.74 ×108 s 5 + 1.92 ×1013 s 4 − 8.44 ×1014 s 3 + 1.31×1020 s 2 − 4.51×1021 s + 2.31×1026
= 7 (20)
dˆL s + 7.11×10 s + 9.92 ×10 s + 5.03 ×10 s + 4.83 ×10 s + 1.12 ×10 s + 5.74 ×10 s + 7.61×10
4 6 7 5 11 4 14 3 18 2 20 23

1000 80
DH changes from 65.1% to 67% DL changes from 34.9% to 37%
Output voltage (VL)

V. PERFORMANCE ANALYSIS OF SSBDC

Output voltage (VH)

60
800 60 Analytical 50
Analytical 40

600 40
5 5.05
A. Effect of parasitic elements on output voltage
Simulation
Simulation
400 DH changes from 67% to 63% 20 DL changes from 37% to 33% A detailed investigation has been conducted on how parasitic
2 4
Time (Sec)
6 8 2 4
Time (Sec)
6 8
elements affect the output voltage of SSBDC. RL1, RL2 and RL3
(a) (b) are considered as winding resistance of L1, L2 and L3,
Fig. 7 State space model validation (a) step-up mode (b) step-down mode respectively. RL is considered a low voltage source of
resistance. RC1, RC2, RC3 and RCH are the series equivalent
and (20), respectively. The dynamic response of the derived resistances of the capacitors C1, C2, C3 and CH, respectively.
transfer functions is validated by the simulation results, as VFD1 is the forward drop voltage of D1 and RD1 is the internal
shown in Fig. 7. Fig. 7(a) shows the dynamic results of the resistance of D1. RSD1, RSD2, RSD3, and RS4, are the internal
SSBDC for the step-up mode. At 3 sec, the duty ratio DH is resistances of SD1, SD2, SD3, and S4, respectively. The final
changed from 65.1% to 67%; and at 5 sec, it is again changed
from 67% to 63%. These changes in the duty ratio are VH =
[VL (1 + DH ) − DHVFD1 (1 + DH )] 

reflected in the output voltage, i.e., variation of output voltage  ( R + R ) R R R
(1 − DH ) 2 1 + SD 2 SD 3
+ L 3 + a SD1 + b S 4 +  
from 650 V to 736 V for a 65.1% to 67% change in duty ratio  R R R R  (21)
and from 736 V to 572 V for a 67% to 63% change in duty ( DH RD1 + RL1 + RL ) RL 2 RC1 RC 2 RC 3  
ratio. The output waveform confirms that the response of the c +d +e −f −g 
R R R R R  

analytically derived dynamic model closely matches with the
simulation response and the theoretical value. The response (1 + DH ) 2 (3 − 2 DH )(3DH − DH 2 ) 2 (1 + DH ) 2
of the analytically derived dynamic model has oscillations = a = , b = , c ,
because the effect of parasitic is not considered in the model (1 − DH )3 (1 − DH ) 4 (1 − DH ) 4
and the amplitude of voltage is more due to the small (1 + DH ) 1 + 3DH + DH 2 − DH 3 DH DH 2f
perturbation in the duty ratio during step-up operation of = the d = ,e =
32
,f = ,g
(1 − DH ) (1 − DH ) 1 − D D
SSBDC. Fig. 7(b) shows the response of the SSBDC during H H

step-down mode. Here also, the responses closely match. expression of the output voltage VH by considering the
parasitic elements is obtained as, Similarly, the final

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
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expression of the output voltage VL during the step-down

1.5 300
1.4 300

Ideal

Ideal
R=11.52
mode of operation by considering the parasitic elements is 1.2
R=450
250
280 R=7.68
R=5.76
DL 4
1 R=300 200

Output Voltage (kV)

260 R=4.6
obtained as given in (21), where a = ,

Output Voltage(V)
0.8 R=225 R=1.15
150
2
(2 − DL )
R=180 0.99 0.995 1
0.6
100
0.4

( D − DL 2 )
d = ( − DL5 + DL 4 + ( DL 2 + DL 4 − 2 DL3 )(2 − DL )2 ) L 0.2 50

(2 − DL )2 0.0
0 0.2 0.4 0.6 0.8 1
0
0 0.2 0.4 0.6 0.8 1

Duty Ratio DH Duty Ratio DL

DL 2 (4 DL − 2 DL 2 − 2) (a) (b)
b = ( DL − DL 2 )(1 + DL ), e = 2
and Fig. 8 Parasitic output voltage versus D (a) step-up mode (b) step-down mode
(2 − DL )
3 2 TABLE IV POWER LOSS OF THE SSBDC DURING STEP-UP MODE
2 DL − 2 DL
=c ( (− DL5 + 5DL 4 − 4 DL3 + DL 2 ) . Loss Expression
(2 − DL ) Ohmic loss of inductors I H2 ((2 + 2 DH − DH 2 + DH 4 ) + (1 − DH )4 )
RL
PL =(IL12+IL22+IL32) RL (1 − DH )4
VH DL 2 − VFD 0 (2 + DL 2 − 3DL )  
VL =  Ohmic loss of capacitors I H2 (5DH − DH 2 )
 ( RS 1 DL − RD 0 ( DL − 1) − RCO (1 − DL )) RC1 RC 2 RC 3  RC
(2 − DL ) 1 + +b +c + d  PC=(IC12+IC22+IC32+ICH2) RC (1 − DH )2
 R R R R 
 Ohmic power loss of switch I H2 (3 + 4 DH − DH 2 − 2 DH 3 )
RS
2 2
D (R D + D R + R − R ) ( R + ( RC 3 + RC 2 )(1 − DL )) RSD 4   and body diodes of switches
+ L S 2 L L C1 L 2 C1 + a L 3 +e  (1 − DH )4
R R R    PSW,C =(IS42+ISD12+ISD22+ISD32)RS
Switching loss of switch 1 VH2 DH (3 − DH )
(22) (ton + toff ) f s
PSW,S=0.5×fS×(ton+toff)VS4 ×IS4 2 R0 (1 + DH )(1 − DH ) 2
RH is considered as the high voltage source resistance and R is Ohmic power loss of diode I H2 DH (1 + DH ) 2
Rd
considered as the load resistance. Using (21), the parasitic PD,C=ID12RD (1 − DH ) 4
output voltage versus DH during step-up operation is plotted, Loss due to VFD of diode I H DH (1 + DH )
as shown Fig. 8(a). As shown in the plot, the voltage gain is VFD1
PD,VF= VFD1× ID1 (1 − DH ) 2
reduced significantly, as compared to the ideal voltage gain
when DH > 0.7. Fig. 8(b) shows the parasitic output voltage TABLE V POWER LOSS OF SSBDC DURING STEP-DOWN MODE
versus DL during step-down mode of operation. Loss Expression
Ohmic loss of inductors I L2 (4 − 4 DL + 5DL 2 − 4 DL 3 + 2 DL 4 )
RL
B. Efficiency Analysis PL =(IL12+IL22+IL32) RL (2 − DL ) 2
Ohmic loss of capacitors I L2 (4 + 2 DL − 5DL 2 − 6 D L 3 + 8D L 4 − 5D L 5 + D L 6 )
The efficiency analysis of the converter is carried out using RC
PC=(IC12+IC22+IC32+ICL2) RC (2 − DL ) 2
the standard power loss equations. The power loss of each
Ohmic power loss of switches
component of the SSBDC during step-up mode is calculated and body diode of switches
I L2 (4 − 4 DL + DL 2 − 2 DL 3 + DL 4 )
RS
as given in Table IV. The power loss during step-down mode PSW,C = (ISD42+IS12+IS22+IS32) RS
(2 − DL ) 2
is calculated as given in Table V. The total power loss as Switching loss of switches
1 VL2 (4 − DL )
(23) PSW,S=0.5×fS×(ton+toff)(VS1×IS1+ (ton + toff ) f s
Ploss = PL + PC + PSW ,C + PSW , S + PD ,C + PD ,VF 2 R0 DL (2 − DL )
VS2 IS2+VS3×IS3)
Fig. 9(a) shows the loss breakdown analysis of the SSBDC. Ohmic power loss of diode
I L2 (1 − DL ) Rd
PD,C=ID02RD
Compared to the other losses, the losses due to the switch S4
Loss due to VFD of diode
is more during the step-up mode. The efficiency of the I L (1 − DL )VFD 0
PD,VF= VFD0× ID0
SSBDC is computed using (23), as shown in Fig. 9(b). The
figure demonstrates that the SSBDC's analytical efficiency is Load power at 300 W 98
96.7% in step-up mode and 97.7% in step-down mode for 300 4 Step-up mode
3.5
W of output power. The experimental efficiency profiles of
Step-down mode 96
% Efficiency

3
Power loss (W)

2.82.8
the SSBDC for both the modes are also presented in Fig. 9(b). 2.5
94
2 1.6
VI. PERFORMANCE COMPARISON OF SSBDC 1
92 Analytical
Step-down mode
1 0.70.7 Experimental
0.40.4 90 Analytical
A detailed study has been conducted to assess the 0
0.1
0.03 Experimental Step-up mode
PD,VF PSW,C PSW,S
potential benefit of the SSBDC converter with some of the PL PC PD,C
50 100 150 200 250 300
components Load power (W)
similar converters in the literature. Fig. 9 shows the voltage (a) (b)
gain comparison of the SSBDC in step-up and step-down Fig. 9 SSBDC (a) Loss break-down study (b) Efficiency investigation
modes. Fig. 10 shows a comparison of the VTRstep-up and 60

VTRstep-down. The comparison confirms that the proposed 50

[22]
Proposed
[16]
[15]
0.8 [7]
[8-10]
[15]
[16]

SSBDC produces more VTR in both the modes compared to 40

[19-21] [11-14]
0.6
[19-21]
proposed
[17]
[22]
the other reported converters except [22]. However, the
[18] [8-10]
VTRStep-down

[11-14] [18]
VTRStep-up

[17] [7]

converter reported in [22] utilizes six switches, and it uses 30

0.4

three switches out off six switches during step-up operation. 20

Whereas, the SSBDC uses a single switch out of four 10

0.2

switches. The comparison of the SSBDC with other reported

converters in terms of the number of components and VTR in 0 0
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8

both the modes is given in Table VI. Duty ratio DH

(a)
Duty ratio DL
(b)
Fig. 10 VTR comparison (a) step-up mode (b) step-down mode

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

TABLE VI COMPARISON OF SSBDC WITH OTHER TOPOLOGIES

Topology [7] [8-10] [11][13] [12] [14] [15] [16] [17] [18] [19-20] [21] [22] Proposed
1 1 + DH 2 2 + DH 3 3 + DH 4 1 3 − DH 1 + DH
VTRstep-up
1 − DH 1 − DH 1 − DH 1 − DH 1 − DH 1 − DH 1 − DH (1 − DH ) 2 (1 − DH )2 (1 − DH )2

DL DL DL DL DL DL 2 DL 2
VTRstep-down DL 0.5 DL DL 2
2 − DL 3 − DL 3 4 − DL 4 2 + DL 2 − DL

S/L/C 4/1/2 3/2/3 4/2/3 5/2/3 4/1/3 5/2/5 8/3/5 5/2/3 6/2/4 4/2/2 4/2/2 6/2/5 4/3/4
Diodes - - - - - - - - - - 2 - 2
Total count 7 8 9 10 8 12 16 10 12 8 10 13 13
Max. VSW VH VC1 0.5VH 0.5VH VH VH − VC1 0.33VH 2VC1 0.5VH VH VH + VC1 VH − VC1 VH − VC1
TABLE VII COMPARISON OF EXTENDABLE SSBDC WITH OTHER N-STAGE TOPOLOGIES

Topology [20] [22] Proposed

1-stage 2-stage n-stage 1-stage 2-stage n-stage 1-stage 2-stage n-stage
1 1 1 3 − DH 5 − 2 DH 1 + n(2 − DH ) 1 + DH 1 + DH 1 + DH
VTRstep-up
(1 − DH )2 (1 − DH )3 (1 − DH ) n+1 (1 − DH )2 (1 − DH )2 (1 − DH ) 2 (1 − DH )2 (1 − DH )3 (1 − DH ) n+1
DL 2 DL 2 DL 2 DL 2 DL 3 DL n+1
VTRstep-down DL 2 DL 3 DL n+1
2 + DL 3 + 2 DL 1 + n(1 + DL ) 2 − DL 2 − DL 2 − DL

Switches (S) 4 4+2 2+2n 6 6+2 4+2n 4 4+1 3+n

Diodes - - - - - - 2 2+2 2n

Inductors (L) 2 2+1 1+n 2 2 2 3 3+1 2+n

Capacitors (C) 2 2+1 1+n 5 5+2 3+2n 4 4+1 3+n

Total count 8 8+4 4+4n 13 13+4 9+4n 13 13+5 8+5n

1 1 1 (2 − DH ) (4 − 2 DH ) n(2 − DH ) 1 1 1
Max.VSW/VL
(1 − DH ) 2 (1 − DH )3 (1 − DH ) n+1 (1 − DH ) 2 (1 − DH ) 2 (1 − DH ) 2 (1 − DH ) 2 (1 − DH )3 (1 − DH ) n+1
n
DH DH 1 + DH n + DH (3 − DH ) DH DH (2 + DH − DH 2 + ∑ (1 − DH )i+1
Max. ISW/IH i =1
(1 − DH ) 2 (1 − DH ) n+1 (1 − DH )2 (1 − DH )2 (1 − DH )2
(1 − DH )n+1
VL(V)/VH(V)/P0(W) 40/400/500 - - 80/800/1000 - - 48/650/300 48/1200/300 -
ⴄstep-up, 95.3%, 97.2%, 96.7%, 96.0%
- - - - -
ⴄstep-down 95.1% 97.6% 97.7% 96.8%
Common ground yes no yes

VII. ANALYSIS OF EXTENDABLE STRUCTURE

I H DH (1 + DH ) I H (1 + DH )
As shown in Fig. 1, the proposed BDC has an extendable I=
D1n n +1
; I=
S 1n = I L DL n ; I D=
0n I L (1 − DL ) n
(1 − DH ) (1 − DH ) n
feature to n-stage. The converter with an n-stage requires a n
total component count of 8+5n including 3+n MOSFETs, 2n n +1 I H DH (2 + DH − DH 2 + ∑ (1 − DH )i +1
diodes, 2+n inductors, and 3+n capacitors. The generalized I L DL
I S=
2 I S=
3 I=
H ; I S=
4
i =1

expressions of the voltage across the capacitors and current 2 − DL (1 − DH ) n +1

through the inductors of the extendable structure for both VL VH DL n
step-up and step-down operations are described as, V=
D1n V=
S 1n = = V=S 1n VD 0 n
(1 − DH ) n 2 − DL
(24)
VL VH DL n VL V D n −1
VC1n =
= V= V= V= = H L
I H (1 + DH ) (1 − DH ) n 2 − DL S2 S3 S4
(1 − DH ) n +1
2 − DL
=I L1 = IL
(1 − DH )n +1 VL VH DL n −1
= VC 2 = The comparison of the extendible SSBDC with other n-stage
I H (1 + DH ) n (1 − DH ) n +1
2 − DL topologies, which are reported in [20] and [22], is given in
=I L 2n = I L DL ; (23)
(1 − DH )n VL DH VH (1 − DL ) n Table VII. The main advantage of the extendible SSBDC is
= VC 3 = that the SSBDC with n = 2 requires only five switches,
I L DL n +1 (1 − DH ) n +1 2 − DL
I=L3 I=H
including a single additional switch and improved VTR, as
2 − DL VL (1 + DH ) VH DL n +1 shown in Fig. 11 and Fig. 12. Whereas [20][25] and [22]
= VH = ; V
(1 − DH ) n +1
L
2 − DL require 6 switches, including 2 additional switches, and 8
switches, including 2 additional switches, respectively. As
The voltage and current stress of switches and diodes of the shown in Fig. 11, the ideal voltage gain of the SSBDC during
extendable structure are described as given in (24). the step-up mode is 45:1 at 80% duty. Whereas [20][25] is
found as 25:1, and [22] is 55:1. For the proposed converter

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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

with n = 2, the gain is 225:1,[20][25] and [22] have a gain of capacitor count become 2n, 3 + n, 4 + n and 3 + n,
125:1 and 85:1, respectively. This comparison confirms that respectively. Hence the total component of the proposed
the proposed BDC produces a significantly large voltage gain BDC becomes 8 + 5n. Whereas in [22], they become 0, 2, 4
when n = 2 compared to [20][25] and [22]. The proposed + 2n and 3 + 2n, with a total component of 9 + 4n. Compared
BDC has reduced voltage stress on the switch compared to to [22], the proposed converter has more diodes and
[20][25][22] for n = 1. Whereas, it is slightly more in the inductors. However, the count of the switch and the capacitor
higher duty ratio region for the proposed BDC when n = 2 is lower. Reduction of switches to 4 + n in the proposed
compared to [22]. However, it achieves better VTR for n = 2. converter reduces the requirement of gate drives and also
The maximum current stress of the switch S4 during step- reduces the control complexity compared to the converters
up is slightly higher in the proposed converter compared to [20][25] and [22] which require 2+2n and 3 + 2n,
[20][22] because of the utilization of single switch in step-up respectively. The inclusion of the inductor on every extended
operation. But, [20][22] use two switches. The extendable stage of the proposed converter results to increase power of
structure of [22] has low voltage stress compared to the the denominator part of the voltage gain. Whereas, the
proposed converter, but it produces lower voltage gain and inclusion of the capacitor in [22] results to increase the
does not have a common ground. The efficiency comparison numerator part of the voltage gain. Hence, the proposed
of the proposed converter with [20] and [22] for n = 1 is given converter achieves more voltage gain from n = 2.
in Table VII. The converters [20] [22] were tested with the
gain of 10:1 for VH / VL of 400 V / 40 V and 800 V / 80 V, VIII. EXPERIMENTAL VALIDATION
respectively. Whereas, the proposed converter is tested with The proposed converter is experimentally validated by
a gain of 13.54:1 for 650 V/ 48 V. The efficiency comparison considering VH = 650 V, VL = 48 V, and P0 = 300 W for the
of the SSBDC shows the competences with [20][22] even switching frequency of 50 kHz. Based on the design, L1, L2
though it is tested at a higher gain. and L3 are considered as 1 mH, 3 mH and 4 mH, respectively.
The efficiency of the proposed converter with 2-stage for The capacitors are taken as 22 µF and 10 µF. To reduce the
VL(V)/VH(V)/P0(W) of 48 V /650 V /300 W is 96.4% for step losses of the semiconductor devices, C3M0025065K (SiC
up and 97.3% for step down. Compared to the proposed MOSFET) and FFSH2065B (SiC diode) are selected. Using
converter with 1-stage, the second stage converter does not the above-mentioned components, a prototype of the SSBDC
provide improvement in efficiency for 48 V /650 V /300 W. has been fabricated and assembled in the laboratory with a
programmable source, digital storage oscilloscope (DSO),
However, the proposed converter with stage 2 gives the
programmable load, etc. The control pulse of 65.1% duty ratio
efficiency of 96.01% for 48 V /1200 V /300 W (a higher VTR
with 50 kHz frequency is generated from TEKTRONIX
ratio) during step-up mode with the operating duty ratio of AFG1022 and given to the switch S4 to test the performance
0.6 and for stage 1 with a duty ratio of 0.737, the efficiency of the SSBDC during step up mode. In this mode, the source
is 95.5% during step-up mode. voltage is set at 48 V, and the converter produces 627 V.
250 Fig. 13 (a)-(d) shows the experimental results of the
SSBDC during step up mode. Fig. 13(a) shows the
200 n=2
n=1
Proposed experimental results of the voltage source, L1 and C1, which
Voltage transfer ratio

n=2 [20],[25] enclosed the path of VL-L1-C1 in state 2. The L1 is energized

150 n=1
n=2 [22]
with an input voltage of 48 V, and it discharges with a voltage
100
n=1
of 89 V, i.e., VC1-VL. The capacitor C1 holds a voltage of 137
V. Hence, the waveforms confirm the KVL in this closed path
50

Capacitor 1 Voltage (VC1)

0 Low Voltage (VL)
Inductor 1 Voltage (VL1) Inductor 2 Voltage (VL2)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Duty ratio DH
Fig. 11 2nd stage VTR comparison during step-up mode
0.8 Inductor 1 Current (IL1) Inductor 2 Current (IL2)
0.15
Capacitor 2 Voltage (VC2)
Capacitor 1 Voltage (VC1)
n=2 0.1
0.6 Proposed
n=1
Voltage transfer ratio

0.05
n=2 [20],[25]
n=1
n=2 [22]
0
0.2 0.3 0.4
(a) (b)
0.4 n=1
Capacitor 2 Voltage (VC2)

Inductor 3 Voltage (VL3)

0.2
Switch 4 Voltage (VS4)

0
Inductor 3 Current (IL3) Diode 1 Voltage (VD1)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Duty ratio DL High Voltage (VH)

Fig. 12 2nd stage VTR comparison during step-down mode Capacitor 3 Voltage (VC3)
Output Current (IH)

Although [20][25] has fewer components, including n-stage,

it has limited voltage gain and more voltage stress compared (c) (d)
to the proposed BDC. When the number of stages of the Fig. 13 Experiment results, step-up mode (a)VL, VL1, IL1 and VC1 (b)VC1, VL2,
proposed BDC increases, the diode, inductor, switch, and IL2 and VC2 (c)VC2, VL3, IL3 and VC3 (d) VS4, VD1, IH and VH

© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: NATIONAL INSTITUTE OF TECHNOLOGY CALICUT. Downloaded on December 31,2022 at 08:52:38 UTC from IEEE Xplore. Restrictions apply.
 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295

during states 1 and 2. Fig. 13(b) shows the experimental
waveforms of the C1, L2 and C2 which enclosed the path C1-
L2-C2 in state 2. Here, the L2 is charged with a voltage of 137
V (i.e., VC1) and discharged with a voltage of 257 V (i.e., VC2-
VC1). The capacitor C2 holds a voltage of 394 V. Fig. 13(c)
shows the waveforms of C2, L3 and C3 (path C2-L3-C3 in state
2). Fig. 13(d) shows the waveforms of the output voltage VH,
output current IH, and voltage stress across the S4 and the D1.
During step-down operation in the SSBDC, the VH side
voltage is set at 650 V using the programmable source on the
load side, and the programmable load is set on the VL side.
The pulse generator is set at 34.9% duty ratio. Fig. 14(a)
shows the waveforms of VH, L3, C2, and C3. The inductor L3 is
charged with a voltage of 257 V (i.e., VH-VC2 where VC2 = 394
V). It is discharged with a voltage of 137 V (i.e. VC2-VC3 where
VC3 = 257 V). The current of the L3 is shown in Fig. 14 (b).
Fig. 14(c) shows the waveforms of the L2 C2 and C1. The L2 is
charged from a voltage of 257 V (i.e. VC2-VC1) and is de-
energized from a voltage of C1, which has 137 V. Fig. 14(d)
shows the waveforms of C1, L1, and the load. Fig. 14(e) shows
the voltage of VL and VH, and their corresponding currents IL
and IH. Fig. 14(f) shows the voltage stresses of the switches S1,
S2, S3 and the diode D0. The magnitude of each output
waveform closely matches the analytical values. To improve
generated bin file is loaded into the Zynq 7000 FPGA
controller, and the necessary feedback signals to the
controllers are sensed from the proposed SSBDC. During the
step-up operation, the source is realized using GWINSTEK
PSW 250-13.5 multi range DC power supply, and it is set to
48 V. Fig. 15(a) shows the source side variation of VL from
48 V to 38 V during step-up mode. Fig. 15(b) shows the load
side variation of iH from 0.3 A to 0.55 A. The designed PI
controller (KP = 8.729×10-7 and Ki = 0.00053) regulates the
output voltage at 650 V successfully for the variations of the
source and load. During step-down operation, the source is
realized using KIKUSUI PAT850-9.4T regulated DC power
supply, and it is set to 650 V. Fig. 15(c)&(d) show the
effective regulation by the PI controller (KP = 0.00018 and Ki
= 0.598) at required VL of 48 V for the source side variation
(VH from 650 V to 540 V) and the load side variation (iL from
2A to 1A) during step-down mode. Fig. 15(c) indicates that
although, the source voltage is varied from 650 V to 540 V,
there is a sloppy response in the programmable source due to
its internal characteristics. The same delay is reflected in the
output waveform of the VL, and then the controller restores
the VL at 48 V.
50 700 1.5
800 48 V

Input voltage (VL)

the dynamic closed loop response, PI controllers are designed
Output voltage (VH)

Output current (IH)

Output voltage (VH)
650
by using the Ziegler-Nichols tuning method for both the 700 38 V
40 1

modes, and the results are shown in Fig. 15. The closed-loop 600 0.55 A
0.5
controllers are realized in MATLAB/XILINX® using the Xilinx 600 30 0.3 A
System Generator (XSG), and the bin file is generated. The 0 0.5 1
550
0 0.5 1

(a) (b)
700 2.5
50
High Voltage (VH)

Output voltage (VL)

High Voltage (VH) 50

Output current (IL)

2A

Output voltage (VL)

Input voltage (VH)

650 2
Capacitor 3 Voltage (VC3)
650 V
600 40 1.5
45
Inductor 3 Voltage (VL3)
Inductor 3 Current (IL3) 540 540 V 1A 1

Inductor 3 Voltage (VL3) 30 40 0.5

0 0.2 0.4 0.6 0.8 0 0.5 1
Capacitor 2 Voltage (VC2)
Capacitor 2 Voltage (VC2)
(c) (d)
Fig. 15 Dynamic results under closed loop, step-up mode (a) source change
(b) load change, Step-down mode (c) source change (d) load change
(a) (b)
IX. CONCLUSION
An extendable bidirectional DC-DC converter with
Capacitor 1 Voltage (VC1) Capacitor 1 Voltage (VC1)
Inductor 2 Voltage (VL2)

Inductor 1 Current (IL1) improved voltage gain was proposed in this paper. The step-
up and step-down modes of operation of the proposed
Inductor 2 Current (IL2)
converter with single-stage were discussed. The single-stage
Inductor 1 Voltage (VL1)
converter uses four MOSFETs and achieves the VTR of
Capacitor 2 Voltage (VC2)
(1+DH)/(1-DH)2 during step-up mode and DL2/(2-DL) during
Low Voltage (VL)
step-down mode. Compared to the similar BDCs, the
proposed single-stage converter using minimum switches,
(c) (d) and achieves improved VTR, lower voltage stress across the
VS1 switches, continuous source current and common ground.
High Voltage (VH)
Switch 3 Voltage (VS3)
When the single-stage structure is extended to the second-
High current (IH) Switch 2 Voltage (VS2)
VS2 stage, the proposed converter requires only a single additional
MOSFET along with the four existing MOSFETS. Moreover,
VS3
Low Voltage (VL) the VTR is significantly improved to (1+DH)/(1-DH)3 during
Switch 1 Voltage (VS1)
the step-up operation and DL3/(2-DL) during the step-down
Diode Voltage (VD0)
VD0 operation. The generalized small-signal model of the SSBDC
Low current (IL)
was derived and the obtained transfer functions are validated
using the circuit level simulation. Using the derived transfer
(e) (f) functions, the PI controllers were designed using Ziegler–
Fig. 14 Experiment results, step-down mode (a) VH, VL3, VC2 and VC3 (b) VH, Nichols method for both the modes. The analytical and
VL3, IL3 and VC2 (c) VC2, VL2, IL2 and VC1 (d) VC1, VL1, IL1 and VL (e) VH, IH, VL
and IL (f) VS1, VS2, VS3 and VD0
experimental performance of the proposed single-stage BDC

© 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.
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 This article has been accepted for publication in IEEE Journal of Emerging and Selected Topics in Industrial Electronics. This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/JESTIE.2022.3233295
is validated using the 300 W, 650 V, and 50 kHz converter
prototype. Using the XSG, the designed controllers were
implemented, and the experimental closed-loop results
proved the effective regulation of the voltages.
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