designideas

Edited By Martin Rowe

and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Digitally programmable-gain amplifier D Is Inside

50 Circuit indicates
uses divergent-exponential curve ac-mains-fuse failure
W Stephen Woodward, Chapel Hill, NC 52 Isolation MOSFET-driver IC


DPGAs (digitally programma-
ble-gain amplifiers) are handy
signal-processing components when-
ever ADCs must acquire signals with
a wide dynamic range. Without the
ability to accommodate input-signal
amplitude to match and efficiently use
ADC span, low-level inputs may not
be digitized with adequate resolution,
and high-level inputs may overrange
gets improved power efficiency
at lighter loads
54 Synthesize variable resistors
with hyperbolic taper
ETo see all of EDN's Design
Ideas, visit www.edn.com/design
ideas.

the ADC and be lost altogether.

Currently available DPGA designs
typically incorporate a multiplying
DAC into an op-amp-feedback loop,
so that the input code to the multi-
plying DAC sets the amplifier’s closed-
loop gain. Several available monolith-
ic DPGAs, such as Linear Technology’s
(www.linear.com) LTC6910 and Na-
tional Semiconductor’s (www.national.
Figure 1 The behavior of the RC topology is still simple when you replace R com) LMP8100, employ this topolo-
with an active circuit that synthesizes a negative resistance. gy. But the DPGA’s digital-gain-con-
trol bits are sometimes inconvenient
to provide, and these devices’ output
R1 span may be inadequate, for exam-
14.3k VOUT ple, to interface to 610V ADC-input
TO ADC spans. Also, the resolution of these de-
AMPLIFY/
TRACK vices’ available gain settings is usually
11 T=14.4 �SEC
13 X1 A coarse—for example, 2-to-1 per gain
R4
X
14 10 � step—and their power consumption is
2k
VIN 12
X0 ¼ LT1214
8 sometimes large. In contrast, this De-
1/ 9 � sign Idea describes a new DPGA that
3 MAX4053
C employs the concept of the divergent-
R2 R3
0.001 �F 28.7k 28.7k
exponential curve.
No waveform is simpler or more
familiar than the e2t/RC-convergent
exponential—the asymptotic dis-
Figure 2 The divergent-exponential and negative time constants are the core charge to zero of an elementary RC
concepts of the DENT (divergent-exponential-negative-time-constant) DPGA circuit initially charged to the input
topology. edn080821di42882 DIANE voltage, VIN, in which V5VIN/2 at
t5T5log e(2)RC, V IN/4 at t52T,

January 8, 2009 | EDN 49

designideas
VIN/8 at 3T, and so forth. Less famil-
iar, but just as simple, is the behavior
of the same RC topology when you
replace R with an active circuit that
synthesizes a negative resistance (Fig-
ure 1). Replacing R with 2R makes
the RC time constant negative: 2RC
and the waveform function yield the
divergent exponential, VIN3e1t/RC.
Then, instead of converging to zero,
the waveform diverges theoretically
to infinity, and V52VIN at t5T, 4VIN
at 2T, 8VIN at 3T, and so forth. There-
fore, no matter how small the input
voltage might be, you can amplify it
as much as you desire to any voltage
by simply waiting the right amount of
time5t5log2(V/VIN)T after starting
the negative discharge.
The divergent-exponential and
negative time constants are the core
concepts of the DENT (divergent-
exponential-negative-time-constant)
DPGA topology (Figure 2). When
the amplify/track-control bit goes to
logic one, the two-times-noninverting
gain of the op-amp follower creates a
negative time constant: 2(R11RON)
(C1CSTRAY)5214.4 msec, where RON
is the on-resistance of the CMOS
switch, and CSTRAY is the parasitic ca-
pacitance surrounding C (Figure 3).
It also creates a diverging exponen-
tial: VOUT(t)5VIN32(t/10 msec11). Thus,
gain52(t/10 msec11). The 1-msec timing
resolution in the amplify-control bit
provides 1.07-to-150.6 dB533 steps/
decade gain-programming resolution.
Figure 4 graphs the voltage gain ver-
sus the time elapsed since the track/
amplify-logic transition.
Unlike monolithic PGAs, DENT
uses discrete components, such as op
Circuit indicates ac-mains-fuse failure
By Vladimir Oleynik, Moscow, Russia

Fuses are essential parts of
power-distribution systems be-
cause they prevent fire or damage to
electronic equipment. Fuses have the
disadvantage of requiring replacement
after every burnout, but they have the
advantages of being inexpensive and
50 EDN | January 8, 2009
SAMPLE AND
CONVERT
SAMPLE AND
CONVERT
T=R4C T=�R1C
VOUT
2VIN
AMPLIFY/TRACK
TRACK AMPLIFY TRACK AMPLIFY
Figure 3 When the amplify/track-control bit goes to logic one, the two-times-
noninverting gain of the op-amp follower creates a negative time constant.
EDN080821DI4288FIG3 MIKE
Figure 4 This graph shows the voltage gain versus the time elapsed since the
track/amplify-logic transition.
amps and switches, so it can easily ac- 0.007% of gain-programming error.
commodate parameters such as I/O- Fortunately, the near ubiquity of pro-
voltage spans—negative inputs and grammable timer/counter hardware
10V amplitudes—by choosing appro- in popular microcontroller and data-
priate parts and power supplies. The acquisition peripherals usually makes
accuracy and repeatability of the tim- the digital generation of a precisely
ing of exponential generation, ADC repeatable amplify/track control an
sampling, and RC-time-constant sta- easy matter. On the analog side, pos-
bility limit the practical performance sibilities exist for self-calibration algo-
of the amplifier in gain-programming rithms that preserve gain-setting accu-
accuracy and jitter. In the sample cir- racy and relax RC-component-preci-
cuit, with T514.4 msec, 1 nsec of am- sion requirements, but they lie beyond
plify-timing error or jitter equates to the scope of this Design Idea.EDN
cases, audible indication is sufficient.
The circuit works with a range of loads,
and you can change its components to
widely available. It is difficult to de- adapt to particular ac mains and load
termine the failure time of fuses with specifications.
ceramic or sand-filled bodies to pre- When a fuse is in good order, the in-
vent arcing. This Design Idea presents dication circuit is off because the fuse
a simple circuit that solves this prob- shunts it. When a fuse burns out, the
lem (Figure 1). It visually and audibly indication circuit starts working. Ca-
indicates ac-mains-fuse failure; in most pacitor C1 reduces the ac-mains volt-
designideas
age, and bridge diode D1 rectifies the ac
voltage. Resistor R1 limits inrush cur-
FUSE
rent when capacitor C1 is discharged. LOAD 60W
Zener diode D2 and capacitor C2 form R2 C1
1M
a dc voltage to operate a buzzer- and 0.15 �F
¼W 400V
blinking-LED network. The blinking R1
LED flashes, and buzzer B1, which has 56
~
a built-in generator, sounds. ~220V
1W
B1
Like most other simple circuits, this 1206X
� �
circuit also has a disadvantage: It is in-
compatible with some load-power and D1
W04M D2 C2 �
ac-mains-voltage values. When a fuse ~10V 100 �F
D1
BLINKING
burns out, the load stays connected to 1W 16V
the ac mains, and the ac voltage di-
vides between the circuit and the load.
When the load is highly resistive or the
ac-mains voltage is 110V rather than
220V, the circuit’s operating voltage Figure 1 This circuit visually and audibly indicates ac-mains-fuse failure.
may be too low to drive the circuit. In
that case, decrease the value of capaci- ponent values in Figure 1, the tested the circuit operates well because, with
tor C1 to 47 or 68 nF, after which the edn080904di43341
circuit operated with resistive DIANE
loads of higher load-power values, the circuit’s
circuit’s resistance rises. With the com- 20 to 200W. With higher-power loads, load resistance is lower.EDN

a bipolar phototransistor, using it as

Isolation MOSFET-driver IC gets IC2 would be less suitable in this case.
improved power efficiency at lighter loads A bipolar phototransistor has a satu-
ration voltage of 0.4V, and, further,
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia the CTR (current-transfer ratio) of a
common optocoupler would decrease


Many modern power MOSFETs
reach low values of on-resistance
at 5V even when the gate-to-source
voltage is 5V. For heavy-duty power
MOSFETS and, especially, IGBTs (in-
sulated-gate bipolar transistors), how-
ever, engineers prefer gate-to-source
voltages of 12 to 15V because the on-
resistance of those power switches fur-
ther decreases at higher gate-to-source
voltages. The 17A-rated IRFR024
power MOSFET from International
Rectifier (www.irf.com), for example,
has an on-resistance of 0.075V (Refer-
ence 1). When the gate-to-source volt-
age is 12V, the device’s on-resistance
drops to 41% of its value compared to
a case of a gate-to-source voltage of 5V.
At a switching current of 10A, the de-
vice dissipates 6W less when the gate-
to-source voltage is 12V.
IC1, an Analog Devices (www.analog.
com) ADuM5230 IC isolation driver,
can boost a 5V input to a level that’s
high enough to drive a MOSFET’s on-
resistance to a low value, minimizing
power dissipation (Figure 1). At low
switching frequencies, however, the
IC’s high-side, internal 18V clamping
dissipates the energy that the IC draws
from the low-side 5V supply (Refer-
ence 2).
The ADuM5230’s output is, how-
ever, unregulated. Fortunately, this
IC has an adjustment pin that you can
use to control the duty cycle of the
device’s internal PWM (pulse-width
modulator) to reduce the duty cycle
from a value of 1 to approximately 0.1.
The default duty cycle has the value of
0.55 when the adjust pin is open. The
lowest value of duty cycle occurs when
connecting the adjust pin to the 5V
supply. IC2, an ASSR-1219 advanced
photo-MOSFET device from Avago
Technologies (www.avagotech.com),
controls the voltage at the adjust pin.
The photo-MOSFET has 0V satura-
tion voltage between its output ter-
minals. As a classical optocoupler has
significantly when operating close to
output saturation. Pulling the voltage
at the adjustment pin to the external
voltage-supply level comes into ac-
count when the high-side output of
IC1 has light or negligible loading.
At some point, V ISO, the high-
side output voltage of IC1, will ex-
ceed the value of approximately
VZ(IF)1VFLED~13.5V, where VZ(IF) is
the voltage of zener diode D1 at IF, the
forward current of D2, and VFLED is the
minimum forward voltage at D2, the
LED of IC2. IC1 exceeds this value, cur-
rent starts to flow through the D2, and
the MOSFET at the output of IC2 be-
comes conductive. The manufacturer
of IC2 designed it for on/off operation
and recommends a forward current of
at least 0.5 mA (Reference 3).
At signal-level loading of the MOS-
FET at the output of IC2, a few tens
of microamperes of forward current
through the LED cause the photo
MOSFET’s on-resistance to change

52 EDN | January 8, 2009

designideas
NC
0V
EXTERNAL
3.9 �F 100 nF
SUPPLY
5V
� GNDISO
IC3 RA
� 3
AD1580 10k
INPUT
5V LOGIC RF
CONTROL 100k
0V
Figure 1 Connecting optical feedback by opto-MOSFET IC2 in the power-MOSFET-driver IC1 stabilizes the high-side
output voltage to 13.5V at values of loading current down to 3.7 mA. The power efficiency of the circuit increases for
a loading current of less than 7 mA.
from an almost-infinite value to a
value of kilohms. The voltage level at
the adjust pin then increases, and the
duty factor of both the PWM in IC1 de-
creases. This action establishes an iso-
lated negative-voltage feedback. Thus,
the temperatures of both the MOSFET
and the LED in IC2 have little effect on
the properties of the circuit. At lighter
loads, the current drain of the 5V sup-
ply is much lower than that of IC1 with
its adjust pin open.
Under test, the default supply current
of the unloaded IC1 was approximately
94.6 mA. This value decreases to 31.7
mA with the feedback in the circuit.
Synthesize variable resistors
with hyperbolic taper
TL Flaig, Clinton, WA

In adjustable, frequency-selec-
tive RC networks, the recipro-
cal of an RC product, vC51/RC, de-
termines the corner frequencies of the
54 EDN | January 8, 2009
NC D S
4 IC2 3
ASSR-1219
TURN-
OFF G
5 CIRCUIT 2
D2
D1
BZM85C15
6 1
RD
820
GND1 VOA
1 16
� 13.5V INTERNAL
VISO
VDD1
2 15 FLOATING
100 nF 10 �F
SUPPLY
VADJ
14
GND1
IC1 NC
4 ADuM5230 13
VIA NC
5 12
VIB GNDB NC
6 11
VDD1 VDDB NC
7 10
VOB NC
8 GND1 9
INTERNAL DIELECTRIC BARRIER
FOR LONG-TERM USE AT �700V
At heavy loading, the high-side output R e fe r e nce s
current of IC1 rises to approximately 20 1 “IRFR/U024 HEXFET Power
mA, and the duty factor rises automati- MOSFET,” International Rectifier,
cally to a properedn080918di43471
value that’s higher than
DIANE www.irf.com/product-info/datasheets/
at the default supply current.
(PLACED IN 10-2 Thus, the
FOLDER) data/irfr024n.pdf.
output voltage is roughly 13.5V within 2 “ADuM5230, Isolated Half-Bridge
the range of approximately 3.7 to 22.6 Driver with Integrated High-Side Sup-
mA. The power efficiency of the circuit ply,” Analog Devices Inc, 2008, www.
is 20% or greater. At an output cur- analog.com/static/imported-files/
rent of 4.5 mA, the power efficiency is data_sheets/ADuM5230.pdf.
20.5%, and the power efficiency for IC1 3 “ASSR-1218, ASSR-1219 and
is approximately 15%. At a current of ASSR-1228, Form A, Solid State
3.7 mA, the circuit reaches 20% effi- Relay (Photo MOSFET) (60V/0.2A/
ciency, a value that’s considerably high- 10V),” Avago Technologies, July 18,
er than the 13% in IC1 with its adjust 2007, www.avagotech.com/docs/
pin open.EDN AV02-0173EN.
wiper position, 0<a<1, and RP is the
potentiometer’s end-to-end resistance,
then the corner frequencies are recip-
rocal functions of the potentiometer’s
wiper position, and the frequency scale
network. If the adjustable elements compresses at the high end of the ad-
are potentiometers with a linear-con- justment range. This situation is usu-
trol characteristic—that is, taper— ally undesirable because it complicates
R(a)5aRP, where a is the normalized adjustment of the network at the high
designideas
I1 R
R1 ear taper potentiometer and a few 4
7.15k
V1
other components.
Figure 1 shows a simple cir- �
CCW
R1-0(�)
�RP
�
cuit for producing a ground-refer- R18
LT1007

R2 RP
�
enced variable resistance having 500k � R8
10k
(1-�)RP the desired hyperbolic-control CW
characteristic. Analysis of this R9
R6 � 10k
circuit yields the following rela- 93.1k LT1007
Figure 1 This simple circuit synthesizes tionship between the control set- �
R7
a grounded variable resistance with a ting and the resistance from Node 93.1k R5
hyperbolic-control characteristic. 1 to ground: R1-0(a)5R1R2RP/ 7.15k

(R 1R 21R 1R P1aR 2R P)0<a<1.

I1
R1 If you use this resistance in se- �
V1 C1 C2
ries or in parallel with a capaci- 0.1 �F 0.1 �F LT1007 VOUT
edn081002di43231 DIANE tor, the resulting corner frequen- VIN �
R2
(PLACED IN 10-2� FOLDER) cy will be a linear function of 392
�RP
RP
�
a: v C5(R 1R 21R 1R P1aR 2R P)/
(1-�)RP R3 R 1R 2R PC. The minimum and CCW �

R1-2(�) maximum values for R 1-0

are R3 R1A
LT1007
7.68k 500k
R 1-0MIN5R 1R 2R P/(R 1R 21R 1R P1 �
CW
R3 R2RP) and R1-0MAX5R2RP/(R21
R2
� RP).
To design this circuit for spe- Figure 3 The basic circuits of figures 1 and 2
�
R2 cific values of R1-0MIN and R1-0MAX, have been used in the design of a bridged-T
R1 choose RP.R1-0MAX and then com- notch filter with a variable notch center fre-
V2
pute R15R1-0MAX R1-0MIN/(R1-0MAX2 quency and a linear frequency scale.
I2 R 1-0MIN ) and R 2 5R P R 1-0MAX /
Figure 2 You can realize a floating (RP2R1-0MAX). R1-2MIN and R1-2MAX, choose
edn081002di43233 DIANE RP.R1-2MAX
variable resistance, with hyperbolic You can extend the basic cir- and then compute R1
5R R
1-2MAX 1-2MIN
/
taper, with this circuit. Note that fixed cuit of Figure 1 to produce a float- (R1-2MAX2R1-2MIN) and R25½RPR1-2MAX/
resistors with the same number are ing variable resistance with hyper- (RP2R1-2MAX). Note that the value of
matchededn081002di43232
pairs. bolic taper (Figure 2). The value the R3 resistors does not directly affect
DIANE
(PLACED IN 10-2 FOLDER) of the floating resistance between the value of R1-2(a). You should choose
end. To make the frequency scale lin- nodes 1 and 2 is R 1-2(a)52R1R2RP/ resistors that are large enough to not
ear requires a control element with a (2R 1 R 2 1R 1 R P 12aR 2 R P )0<a<1, excessively load the op-amp outputs.
hyperbolic taper—that is, something and the minimum and maximum val­ Figure 3 illustrates the application
in the form R(a)5RP/(A1aB). Such ues for R 1-2 are R 1-2MIN52R1R2RP/ of the circuits in figures 1 and 2 to
variable resistances are not general- (2R1R21R1RP12R2RP) and R1-2MAX5 the design of an adjustable bridged-
ly available from manufacturers, but 2R2RP/(2R21RP). To design the cir- T notch filter with a linear frequen-
you can synthesize them using a lin- cuit of Figure 2 for specific values of cy scale. The filter has a notch cen-
ter frequency that is adjustable from
1100
50 to 1000 Hz and a notch depth of
1000
220 dB. These requirements and the
900
choice of 0.1-mF capacitors for C1 and
800
C2 dictate that R1-0 varies from 375 to
700
7503V and that R1-2 varies from 6752
f N 600
(Hz) to 135,047V. (A side benefit of using
500
this technique is that it frees the de-
400
signer from the restrictions of the lim-
300 ited number of standard end-to-end
200 resistance values that potentiometer
100 manufacturers offer.)
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Figure 4 plots the Spice-simulated
a notch center frequency for the cir-
Figure 4 The Spice-simulated notch center frequency for the circuit of Figure 3
cuit of Figure 3 against the normalized
versus the normalized wiper position shows that the notch center frequency is
wiper position. The notch center fre-
a linear function of the control position.
quency is a linear function of the con-
trol position.EDN

edn081002di43234 mike
56 EDN | January 8, 2009
designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Increase the range of memorized

voltage for a sample-and-hold device D Is Inside
Yakov Velikson, Lexington, MA 48 Inexpensive self-resetting cir-
cuit breaker requires few parts


Sample-and-hold devices find to handle greater voltage can signifi-
54 Sinusoid generator uses
use in front of ADCs. The basic cantly improve the resolution of an
dual-output current-controlled
sample-and-hold circuit comprises two ADC.
conveyors
op amps, A1 and A2; a switch, S1; and You can increase the memorized
a capacitor, C1 (Figure 1). For many voltage that amplifiers A1 and A2 can 56 Perform timing for micro­
low-power op amps, the values of the reach by using a variable power supply controllers without using timers
input and output voltages can be only (references 1 and 2). This approach
610 to 614V using a standard 615V places additional voltage require- ETo see all of EDN's Design
power supply. Enabling these devices ments on S1, however. To continue Ideas, visit www.edn.com/design
using switches ideas.
15V with the same
15V
range as the
original, you
�
must add two two parts of the circuit may have in-
� S1 A2 VOUT
A1
switches and dependent power supplies. You apply
�
VIN independent the same variable voltages to ampli-
�
C1 control-logic fiers A1 and A2 as you do to control-
�15V
blocks, CL 1 logic blocks CL1 and CL2, respective-
�15V and CL 2 , for ly. When S1 and S3 are closed, S2 is
Figure 1 A basic sample-and-hold circuit comprises two op
switches S1, S2, open, and vice versa.
amps, a switch, and a capacitor.
and S 3 (Fig- The resulting circuit keeps the volt-
ure 2). The ages connected to the gate and sub-
strate for the MOS transistors of each
VCONTROL
switch within the desired 30V range
edn081002di43321 DIANE
(Figure 3). (You derive this value from
V1 CONTROL CONTROL V3 the sum of absolute-voltage values:
V2
LOGIC
CL1
LOGIC
CL2 V4
|V1|1|V2| and |V3|5|V4|.) Volt-
V3 ages V1 and 2V2 connect to amplifier
V1 A1, control-logic block CL1, and the
substrates of the transistors of switches
� S1 and S2. Voltages V3 and 2V4 con-
�
S1 S3
A2 VOUT nect to amplifier A2, control-logic
A1
VIN
� block CL2, and the substrates of the
�
C1 transistors of switch S3.
V4 You create the changing voltages
S2
V2 of V1 and V2 using resistor dividers
R5 and R6 and R7 and R8, which con-
nect to the 30 and the 230V power
supplies and the output of amplifier
Figure 2 To continue using switches with the same voltage range as that
follower A1 (Figure 3). Transistors
of Figure 1, you must add two switches and two independent control-logic
Q1 and Q2 create the change to the
blocks.
power supply of amplifier A1. Volt-
edn081002di43322 DIANE

january 22, 2009 | EDN 47

designideas
ages V1 and V2 also supply power to
control-logic block CL1 and the sub-
strates of the transistors of switches S1
and S2. CL1 comprises transistors Q11,
Q12, Q15, and Q16. It creates a control
signal for gates Q5 and Q6 of switch S1
and the inverse signal for gates Q8 and
Q9 of S2.
Resistor dividers R9 and R10 and R11
and R12 connect to the 30 and the
230V power supplies, and the output
of amplifier follower A2 creates the
30V
R5
V1
Q1
R6
� �
A1 Q5
VIN � �
R7 Q8
V2
Q2
R8
�30V
Figure 3 You can create the changing voltages of V1 and V2 using resistor dividers R5 and R6 and R7 and R8.
Inexpensive self-resetting circuit
breaker requires few parts
Anthony H Smith, Scitech, Bedfordshire, England

Most readers are familiar with
the current-limiting circuit in
Figure 1, in which the load current,
IL, is limited to a value of ILPVBE/RS,
where VBE is the base-to-emitter volt-
age and RS is the sense resistance. Un-
der normal conditions, in which the
base-to-emitter voltage is too small to
bias Q1 on, P-channel MOSFET Q2’s
gate resistor, RG, biases Q2 fully on, and
48 EDN | january 22, 2009
changing voltages V3 and V4. Tran-
sistors Q3 and Q4 create the change
to the power supply of amplifier A2.
Voltages V3 and V4 also supply pow-
er to control-logic block CL2 and the
substrates of the transistors of switch
S3. CL2 is made up of transistors Q13,
Q14, Q17, and Q18. It creates a control
signal for gates Q7 and Q10 of switch
S3. Transistors Q5 through Q10 and
Q11 through Q18 of CL1 and CL2, re-
spectively, are complementary pairs of
VCONTROL
Q11 Q12 Q13
R1 R2
R3 Q16 Q17
Q15
R4
Q6
Q9
edn081002di43323 DIANE
only the load resistance, RL, and the
load voltage, VL, determine the load
current. However, if the load current
increases to a point at which the base-
to-emitter voltage is approximately
0.7V, Q1 starts to conduct and reduces
Q2’s gate-to-source voltage, VGS, to a
level that holds the load current rough-
ly constant at a value you derive from
ILMAXIMUMP0.7V/RS.
MOS logic transistors.EDN
R e fe r e nce s
1 Velikson, Yakov, “Controlled power
supply increases op amp’s output-
voltage range,” EDN, March 15,
2007, pg 72, www.edn.com/article/
CA6421438.
2 Velikson, Yakov, and Igor Ribkin,
“Analog switch, 1385288,” Bulletin of
Izobreteny (Copyrights and Patents),
No. 12, 1988.
Q14
30V
R9
V3
Q3
Q18
R10
Q7 A2 VOUT
Q10
R11
V4
C1 Q4
R12
�30V
This linear current limiter is effec-
tive for applications in which the max-
imum load current, the supply voltage,
or both are relatively small. However,
the power that the circuit’s pass tran-
sistor, Q2, dissipates limits the circuit’s
applicability. For example, if the maxi-
mum load current is 200 mA and the
supply voltage, VS, is 24V, a short cir-
cuit across the load would dissipate al-
most 5W into Q2. Q2 must handle this
power with adequate margin, and ad-
ditional heat-sinking may be neces-
sary to keep its junction temperature
at a safe level. Using larger values of
designideas
maximum load current, supply RS
If a fault now causes the load
Q2
voltage, or both exacerbates this current to increase to a level at
problem. In many applications, IL which the base-to-emitter voltage
the cost, size, and weight of the VBE is approximately 0.7V, Q1 turns
components necessary to handle VL
on and its collector current rap-
SUPPLY
the short-circuit power dissipa- VOLTAGE �
� Q1 idly charges C1. The input volt-
tion may be prohibitive. VS RL age now quickly rises toward the
However, by adding a few RG Schmitt inverter’s upper thresh-
inexpensive components, you old voltage, VTU, at which point
can adapt the circuit to pro- IC1’s output goes low, turning off
vide effective current limiting Q3 and Q2. The load current now
with none of the power-dis- Figure 1 A conventional two-transistor current falls to 0A and the base-to-emit-
sipation headaches. The re- limiter prevents excessive current from reaching ter voltage falls to 0V, thereby
sulting circuit functions as a the load. causing Q1 to turn off. C1 now
self-resetting circuit breaker begins to discharge through R1
(Figure 2a). Again, Q1 and RS pro- assume that the load current is initial- and R2, and the input voltage slow-
vide a current-monitoring function ly low and the base-to-emitter voltage ly falls toward the Schmitt inverter’s
in which the sense voltage VSENSE5 is less than 0.7V. Under these condi- lower threshold voltage, VTL. At this
IL3RS. In this circuit, however, Q2 is tions, Q1 is off and timing capacitor C1 point, IC1’s output again goes high, Q3
either fully on or fully off and never remains uncharged such that VIN, the and Q2 turn on, the circuit breaker re-
biases into its linear region. Because voltage at the input of Schmitt inverter sets itself, and the process repeats un-
Q1’s base current is normally small, the IC1, is 0V. Thus, IC1’s output
edn081016di43391 is approxi- til you remove the fault.
DIANE
voltage drop across base resistor RB is mately 5V, biasing Q3 on, which in turn The circuit’s waveforms show the
also small, such that the base-to-emit- provides gate bias for Q2 through R4, al- relationship between the input volt-
ter voltage is approximately equal to lowing current to flow from the supply age and the load voltage (Figure 2b).
the sense voltage. voltage into the load through the sense Because load current flows into Q 2
To understand how the circuit works, resistor and Q2’s on-resistance. only during the on-time, the average
power it dissipates is directly propor-
tional to the duty cycle: PAVG∝tON/
RS Q2 (tON1tOFF), where PAVG is the aver-
VSENSE age power in watts, tON is the on-time,
RB
R3 IL and tOFF is the off-time. Provided that
VBE 10k
1k C1, R1, and R2 set a large enough time
Q1 constant, the off-time will normally
RX R4 be much greater than the on-time,
SUPPLY � 5V 10k VL
VOLTAGE � R IC
RL and the resulting power that Q2 dis-
D X C1 1 1
VS sipates will be low. Like the linear-
Q3
current limiter, the sense resistor sets
CX the circuit breaker’s current limit:
R2 VIN C2
2N7002
0V 100 nF ILMAXIMUMP0.7V/RS (A).
R1 and R2 form a potential divider
(a)
that ensures that the input voltage
VTU can never exceed IC1’s maximum in-
VIN put voltage. Select values such that
the input voltage is 5V or less when
VTL Q1 is fully on, where the voltage of
�VS C1 is roughly equal to the supply volt-
VL
tON age. Also, choose values that are large
enough to provide a large time con-
tOFF stant without requiring an excessively
large value of C1. The selection of tran-
(b) 0V sistor Q1 isn’t critical, but you should
select a device with good current gain
Figure 2 Adding a few components turns the current-limiting circuit into a and make sure that its maximum col-
pulser that reduces heat in the pass transistor, Q2 (a). The circuit’s waveforms lector-to-emitter voltage is greater
show the relationship between the input voltage and the load voltage (b). than the supply voltage. When choos-
ing a P-channel MOSFET for Q2, re-

52 EDN | january 22, 2009 edn081016di43392 DIANE

designideas
member that it must withstand the full
supply voltage when you bias it off, so
make sure that the maximum drain-to-
source voltage is greater than the sup-
ply voltage. When choosing a value for
the sense resistor, ensure that the base-
to-emitter voltage is less than 0.5V at
the maximum normal value of the load
current.
Loads such as filament bulbs, ca-
Sinusoid generator uses dual-output
current-controlled conveyors
Abhirup Lahiri, Netaji Subhas Institute of Technology, New Delhi, India

Second-generation current con-
veyors feature wide signal band-
width, linearity, wide dynamic range,
simple circuitry, and low power con-
sumption. Hence, designers employ
several implementations of current
mode in these devices for realizing var-
ious functions. A previous Design Idea
introduced a second-generation dual-
output current-controlled conveyor to
create oscillators (Reference 1). Un-
fortunately, these circuits aren’t avail-
able as ICs, but you build them from
discrete components. Figure 1 illus-
trates an active building block of such a
circuit, which the following equations
characterize: I Y50, V X5V Y1I XR X,
Q7
Y X
IB
Q9
Q8
Figure 2 A current-controlled circuit uses no internal resistors or capacitors.
54 EDN | january 22, 2009
pacitive loads, and motors that ex-
hibit a large inrush current can cause
the circuit breaker to trip on power-
up. You can avoid these problems by
adding capacitor CX, diode DX, and
resistor RX. On power-up, CX is ini-
tially uncharged and pulls the input
voltage toward 0V through DX. This
action prevents the circuit breaker
from tripping until the inrush current
IZ15IX, and IZ252IX. You can express
the parasitic resistance at terminal X
as RX5VT/2IB, where VT is the thermal
voltage and IB is the bias current of the
conveyor that is tunable over several
decades. Figure 2 shows the bipolar
implementation of the circuit.
The circuit provides an extra degree
of freedom in the sense that the con-
trol over the frequency of oscillation
can be through both current and volt-
age. The circuit in the previous De-
sign Idea provides various advantages,
it this new circuit not only retains all
those essential advantages, it also pro-
vides an extra feature of voltage con-
trollability of frequency of oscillation.
�V
Q13
Q5 Q6
Q3 Q1
�Z
Q2 Q4
Q12
Q11 Q10
�V
edn081018di43502 DIANE
subsides. CX and RX determine a delay,
after which the voltage on CX even-
tually rises to the supply voltage, DX
becomes reverse biased, and the cir-
cuit breaker is then free to respond
to overcurrent faults. Be prepared to
experiment with the values of CX and
RX to get the right delay time. Values
of 10 mF and 1 MV, respectively, are
good starting points.EDN
IY
IB
VY Y Z� IZ�
IX
VX X Z� IZ�
Figure 1 Second-generation cur-
rent conveyors feature wide signal
bandwidth, linearity, wide dynamic
range, simple circuitry, and low
power consumption.
edn081018di43501 DIANE
(PLACED IN THE 10-16 FOLDER)
Additionally, you can control the con-
dition of oscillation using the convey-
ors’ bias currents.
Figure 3 shows the proposed si-
nusoid-oscillator circuit. You can
obtain the characteristic equation
for the circuits as follows: S 2C1C2
R X1 R X2 1 SC 2 R X2 2 SC 2 R X1 1 K5 0,
Q18 Q16 Q15
�Z
Q14 Q17 Q19
designideas
where K is the voltage multiplier. Satis­
fying Barkhausen’s criteria—that the
loop gain is unity or greater and that
the feedback signal arriving back at
the input is phase-shifted 3608—the
required condition for oscillation is
RX15RX2, and the frequency of oscilla-
tion is f51/2p=k/(C1C2RX1RX2).
Clearly, you can use the gain buffer
to vary the frequency of oscillation,
which is the area in which this circuit
differs from the earlier Design Idea. You
can use both current and voltage to
control the voltage multiplier. The cir-
cuit lets you vary the voltage multiplier
by adjusting bias currents IB3 or IB4 (Fig-
ure 4). For voltage control over K, you
can use another circuit simply by using
a noninverting op amp and replacing
the resistors with MOSFETs working in
that triode region. That approach sim-
ulates voltage-controlled resistors.
The circuit in Figure 2 underwent
testing with a PR100N PNP transistor
and an NPN NP100N transistor of the
bipolar arrays ALA400 and a dc supply
of 63V (Reference 2).
The circuit requires only two cur-
rent-controlled conveyors, two ground-
ed capacitors, and a voltage multiplier;
it requires no floating capacitors and
no external resistors, which makes
the circuit’s power consumption lower
than that of RC oscillators. For a con-
ventional bipolar-transconductance
operational amplifier, the transcon-
ductance, gm, is IB/2VT. Comparing
Perform timing for microcontrollers
without using timers
Ganeshkumar Krishnamoorthy, NTERA Ltd, Dublin, Ireland

Microcontrollers now
find use in every walk I/O2 INTERRUPT ON CHANGE
of life. Their peripherals vary
from the general-purpose I/Os MICROCONTROLLER
to the USB interface, mak-
ing them versatile for a range
of products. Timing is one key
part of a typical microcon- Figure 1 The RC filter along with I/O2’s interrupt-on-
troller application. Low-cost change feature provides a simple and cost-effective
microcontrollers have one or approach for a variety of time-scale measurements
two built-in timers and often from microseconds to minutes.
also have a watchdog timer.
56 EDN | january 22, 2009
IB1 IB3
Y Z� VIN Y Z� VOUT
C1
1 3
X Z� X Z�
Y X
IB2
4
Y Z� K Z� Z�
IB4
2
X Z�
C2
Figure 4 This circuit lets you vary the volt-
Figure 3 This configuration creates age multiplier by adjusting bias currents I B3
an oscillator from two current-con- or I B4.
trolled conveyor circuits. edn081018di435014 DIANE
condition (PLACED IN THE 10-16
for oscillation. FOLDER)
Oscillator
this figure with the equivalent
edn081018di43503 DIANE value circuits may latch up and never oscil-
of I(PLACED
B
, the transconductance
IN THE 10-16 FOLDER) of the bi- late even if you satisfy the Barkhausen
polar-transconductance op amp is four criteria.EDN
times less than that of a dual-output
current-controlled conveyor. Thus, R e fe r e nce s
the power consumption of the cur- 1 Lahiri, Abhirup, “Oscillator uses
rent-controlled-conveyor-based cir- dual-output current-controlled con-
cuit is about four times less per active veyors,” EDN, Nov 13, 2008, pg 62,
device than that of the op-amp-based www.edn.com/article/CA6611645.
circuit. The sensitivity study shows 2 Frey, DR, “Log-domain filtering: an
that SωCK;RX1;RX2;C1;C252½; ωc sensitiv- approach to current-mode filtering,”
ities are hence less than unity, which is Circuits, Devices and Systems, IEE
an attractive feature of this circuit. Re- Proceedings G, 1993, Volume 140,
member that creating an accurate os- pg 406, http://ieeexplore.ieee.org/
cillator model requires modeling equa- Xplore/login.jsp?url5/iel1/2211/
tions to be nonlinear, and meeting 6397/00250002.pdf?arnumber5
the Barkhausen criteria is a necessary 250002.
Sometimes, the design requires more
timers without a significant cost in-
crease. Software timers are not suitable
for time-critical application because
the controller is fully occupied. The
circuit in this Design Idea uses
the I/O “interrupt-on-change”
R1 feature that is common in most
1M 1
I/O1 2 microcontrollers to implement
C1 +
IC
a medium-precision, long-pe-
10 �F 1A
GND LM7414 riod timer with low additional
cost.
The circuit in Figure 1 uses
I/O1, a typical I/O pin, to drive
an RC filter. The circuit feeds
the output of the RC filter to a
edn081002di43071 DIANE
Schmitt-trigger inverter whose
(PLACED IN THE 10-2 FOLDER)
output goes back to I/O2, trigger-edge interrupt in this
which has the interrupt- case changes from falling-ris-
on-change feature. After ing-falling edge in a cycle.
power-up, I/O1 is low and Most microcontrollers don’t
the output of the Schmitt- require this feature because
trigger inverter is high. any logic change will trigger
After initialization, I/O1 an interrupt. Figure 2 shows
goes high. Capacitor C1 the timing waveform of the
charges up with the time circuit with the ATMEGA64
constant R 1C1. Once it and the 74HC14.
reaches logic-high voltage, The circuit’s advantages
the output of the Schmitt- are its low cost, a microcon-
trigger inverter goes low troller-clock-independent
and triggers an interrupt time period, and the ability
on I/O2. In the ISR (in- to achieve time periods of
terrupt-service routine), a minutes to hours by tuning
counter increments, driv- Figure 2 Channel 1 shows I/O1’s waveform, and Channel 2 resistance and capacitance.
ing I/O1 low. Now, C1 dis- shows the capacitor’s charging/discharging waveform. The For example, with a resis-
charges through R1. The time period of the waveform is 10.4 sec. tance of 10 MV, a capaci-
voltage reaches logic low, tance of 10 mF, and a 16-bit
again triggering an interrupt. As the www.edn.com/090122dia, includes the register as a counter, you can achieve
cycle repeats, the value in the counter software routine for the ATMEGA64 a maximum count of 75.85 days.EDN
indicates time5counter3R1C1. The microcontroller from Atmel (www.
Schmitt-trigger inverter serves as a atmel.com). In the listing, Port D, A c k n o w l e d g m e n t
debouncer. Pin 5 plays the role of I/O1 and Pin This work is part of a system design in a
Listing 1, which is available in the 3, whose alternate function is INT3, project funded by the European Union
Web version of this Design Idea at plays the role of I/O2 in Figure 1. The under the Marie Curie Project.

january 22, 2009 | EDN 57

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Convert signals to proper logic levels D Is Inside

Abel Raynus, Armatron International Inc, Malden, MA 44 DDR-differential-clock source


When designing a test station output to the microcontroller level. on SOC drives two DDR-memory
chips
incorporating a microcontroller, Moreover, the output will follow the
you often face voltages in the test that measured input-signal variations, so it 48 Flying capacitor and negative
exceed the maximum input level per- needs analog-to-digital conversion in time constant make digitally pro-
mitted for the microcontroller. For the microcontroller. grammable-gain instrumentation
example, if a microcontroller uses a A better approach is to use a small- amplifier
5V power supply, then the maximum signal MOSFET in the voltage-re- 50 MOSFET prevents battery
input signal should also be 5V. When peater configuration (Figure 1). You damage
a test voltage exceeds 5V, you might can use the BS107A from On Semi-
think to reduce the voltage with a conductor (www.onsemi.com) for this 51 Voltage doubler improves
voltage divider. A voltage divider can task. You can consider the gate-to- accuracy
influence the DUT (device under source area of the MOSFET as a ca- ETo see all of EDN's Design
test), however. So, a signal condition- pacitor with a value of approximately Ideas, visit www.edn.com/design
er needs high input impedance. Also, 60 pF. To discharge it in the absence ideas.
the signal conditioner’s output signals of the DUT, connect a resistor of ap-
should match the logic levels of the
microcontroller despite some fluctua-
tion of the measured signal. It allows 5V
you to use the regular microcontroller-
input pins instead of ADC ones.
Engineers often use a noninvert- R1
VTHR 10k
ing op amp to bring signal voltages in 5V 3 8 VOUT
�
line. However, most op amps have dif- FROM DUT
LM393
1 0V MICROCONTROLLER
ferential-input-voltage ranges match- VIN 2 �
12V 4
ing their power-supply voltages. Thus,
you need one more power-supply volt- (a)
age with a higher voltage and several
VIN 12V
extra resistors to lower the op amp’s
12V
VTHR
5V 5V

BS107A D
1 VOUT
FROM DUT
VIN 2
12V 3 VOUT
G 5V
R1 S 5V
MICROCONTROLLER
1M
R2
10k 0V
(b)

Figure 2 Another approach to signal conditioning is to use dual- or quad-

voltage comparators (a). The 5V power-supply voltage acts as the positive-
threshold voltage. The output is 5V for input signals lower than this level. If
Figure 1 You can use a small-signal MOSFET
the input signal exceeds 5V, the output voltage drops to 0V (b).
to provide overvoltage-signal conditioning.

edn081016di43542 DIANE
edn081016di43541 DIANE
february 5, 2009 | EDN 43
designideas
proximately 1 MV between the gate
and ground. Also, the input voltage
should be more than the MOSFET’s
gate-threshold voltage, VTHR, of 3V dc
but less than the maximum rated gate-
to-source voltage, VGS, of 20V dc. In
this figure, the output voltage never
exceeds the power-supply voltage, and
variations of the input voltage have no
effect on output as long as they happen
in the saturation region. A drawback
of this approach is that you must use as
many transistors as the number of test-
points in the DUT.
Another good option is to use any
dual- or quad-voltage comparator.
You can use an LM393 from National
Semiconductor (www.national.com)
because it’s inexpensive and widely
available. Figure 2 shows a simple con-
figuration with few components. The
5V power-supply voltage acts as the
positive-threshold voltage. The out-
put is 5V for input signals lower than
this level. If the input signal exceeds
5V, the output voltage drops to 0V. Re-
sistor R1 connects an open collector of
the LM393 to the supply voltage.
Sometimes, a zero-output signal is
undesirable. A missing power-supply
voltage, a bad solder joint, or a bro-
ken wire in the test fixture could cause
this zero-output signal. Use a logic
high level when the signal under test
is present and logic low when it’s ab-
sent. At first glance, it seems that just
DDR-differential-clock source on
SOC drives two DDR-memory chips
Goh Ban Hok, Infineon Technologies, Singapore

Many system engineers as-
sume that a differential-clock
source should drive just one chip. If
a system design requires driving two
DDR-memory chips, however, the de-
sign would inevitably need a differen-
tial-clock buffer. This Design Idea de-
scribes a circuit that drives two DDR
chips without a clock-source buffer
yet does not sacrifice much of the sig-
nal integrity.
The cost-saving nature of an SOC
44 EDN | february 5, 2009
R2 R3
5V
200k 200k
R1
VTHR 10k
2.5V 2 8 VOUT
�
FROM DUT 1 5V
LM393 MICROCONTROLLER
VIN 3
12V �
4
(a)
VIN 12V
12V
VTHR
2.5V
VOUT
5V
5V
(b)
Figure 3 Use the voltage divider comprising R2 and R3 for the threshold
voltage.
switching the comparator pins of the common-mode range. The upper limit
input and the threshold voltages pro- of common-mode
edn081016di43543 DIANE input voltage for the
vides an acceptable approach. Howev- LM393 is 1.5V less than the power-
er, that assumption is invalid because supply voltage, or 3.5V. Thus, you
the positive input voltage may exceed should use the voltage divider compris-
the power-supply level only as long as ing R2 and R3 for the threshold voltage
the other voltage remains within the (Figure 3).EDN
signals CLK and CLK2 from SOC
chip IC1 connect to series resistors R1
and R2, respectively. The differential
traces then connect to DDR-memory
chips IC2 and IC3 with a 120V termi-
(system-on-chip) design dictates the nation resistor near IC2.
need for fewer pins. Such designs typi- Figure 2 shows the equivalent PCB
cally have only one pair of differential (printed-circuit-board) layout. The
signals available for external-memory- PCB comprises a four-layer FR4 ma-
chip connection. When the system terial with a ground plane under dif-
design requires more than one DDR ferential lines CLK and CLK2. The
chip, designers typically use a clock CLK and CLK2 signals are routed
buffer. close to each other and pass through
Figure 1 shows an SOC with an em- series resistors R1 and R2, which are
bedded DDR controller, which con- also placed close to each other, to pro-
nects the SOC’s differential clock to vide proper termination. The closely
two DDR-memory chips. Differential spaced differential signals connect to
designideas

R1 CLK
IC1 CLK
R3 IC2
SOC R2 DDR CHIP
CLK� CLK�

CLK
IC3
CLK� DDR CHIP

Figure 1 This circuit for an SOC-differential-clock source Figure 2 The bare PCB shows the differential-signal
drives two DDR chips. traces from the SOC to IC1 and IC2.

IC2 with the 120V termination resis- in. DIANE

edn081030di43641 from the SOC chip to the DDR and R2 are 0V and R3 is unconnected.
tor, R3. The bottom-layer traces are chips. Figures 3 through 7, which are available
necessary to connect the differential The SOC provides DDR differential with the Web version of this Design
signals to IC3. The total length of the clocking. With various values for R1, R2, Idea at www.edn.com/090205dia, show
differential pair is approximately 2.5 and R3, the best results occur when R1 various waveforms for the signals.EDN

Flying capacitor and negative time C to the positive and negative differ-
ential-input terminals, which acquire
constant make digitally programmable- the input voltage, VIN. The transition

gain instrumentation amplifier to the amplify mode isolates C from

the input and initiates regenerative
negative-time-constant exponential
W Stephen Woodward, Chapel Hill, NC amplification of the input voltage.


Numerous and evil are the forc- You control DDENT operation From that point (Reference 1) until
es of darkness that conspire to with the amplify / track-bit mode. the moment when a connected ADC
frustrate accurate analog-to-digital Track mode connects flying-capacitor ultimately samples and converts the
conversion of wide-dynamic-range
analog signals. Among these grem- R1
lins lurk common-mode-voltage noise 14.3k
and signal amplitudes too variable to VOUT
fully use ADC-input span and conver- AMPLIFY/
sion resolution. Proven charms against T=14.4 �SEC TRACK
common-mode noise are differential 11
inputs, and you can exorcise variable 13 X1 A
R4 14 10 �
signal amplitudes by implementing 2k
X
8
VIN 12 LT1214
digitally programmable gain. DPGIAs X0
9 �
(digitally programmable-gain instru- MAX4053
mentation amplifiers) combine both C
0.001 �F
useful features (Figure 1). R4
R3
28.7k
Microcircuit—even monolithic— 2k 2
MAX4053
�VIN
DPGIAs, such as the Linear Tech- X0
15 R2
nology (www.linear.com) LTC6915, 1
X 28.7k
are available. But this Design Idea de- X1 A

scribes a DDENT (differential-diver- 10

gent-exponential-negative-time-con-
stant) DPGIA employing the concepts
of the “flying”-capacitor differential
input and the DDENT curve, which
provide an interesting alternative.
Figure 1 The behavior of the RC topology is still simple when you replace the
resistors with an active circuit that synthesizes a negative resistance.
edn080821di42961 DIANE

48 EDN | february 5, 2009

designideas
output voltage, VOUT/VIN is a diver-
gent exponential function of time:
gain52(t/10 msec11).
Building on the assets of that earlier
design, this new circuit features CMR
(common-mode rejection) that nei-
ther resistor-network matching nor
the CMR of the op amp limits. Stray-
capacitance issues impose the only lim-
its, but you can minimize these issues
with careful circuit layout. The circuit
has rail-to-rail inputs, virtually unlim-
ited programmable gain, and gain-set
resolution that only the resolution
of the amplify-interval timing lim-
its. The circuit also has settling time
10 to 100 times faster than that of the
curacy of the op amp you choose, the
this new circuit accuracy and repeatability of the tim-
ing of exponential generation, ADC
features CMR sampling, and RC-time-constant sta-
that neither bility are the only limits on the am-
plifier’s signal-processing performance
resistor-network and precision. In the sample circuit, in
matching nor which T514.4 msec, 1 nsec of amplify-
timing error or jitter equates to 0.007%
the CMR of the of gain-programming error.EDN
op amp limits.
R e fe r e nce
1 Woodward, W Stephen, “Digitally
exemplary LTC6915 and 610V out- programmable-gain amplifier uses
put-amplitude capability—two to four divergent-exponential curve,” EDN,
times greater than that of monolithic Jan 8, 2009, pg 49, www.edn.com/
DPGIAs. Besides the inherent dc ac- article/CA6625454.

MOSFET prevents battery damage (Figure 2). The MOSFET conducts

only when the battery is correctly con-
Santosh Bhandarkar, Wep Peripherals, Mysore, India nected, which lets the battery charge
or discharge. In this condition, the


Sealed-lead-acid batteries,
which find wide use in power-
electronics products, such as UPS
(uninterruptible-power supplies), in-
verters, and emergency lamps, supply
power to the load whenever utility
power is unavailable. When you re-
store utility power, a charger supplies
the power to the load and charges the
batteries (Figure 1).
You can add a diode to protect a load
from current resulting from a reverse-
connected battery. The diode, howev-
er, won’t protect a reverse-connected
battery from the charger circuit. If the
charger is on, a potentially dangerous
current can flow into a reverse-con-
nected battery. The battery voltage,
which normally opposes the charging
voltage, now aids it, which lets a high-
er current flow into the battery.
If you add an N-channel MOSFET
to the circuit, you can protect the bat-
tery from this damaging condition
transistor gets forward-biased, which
switches on the MOSFET. If the bat-
tery is reverse-connected, the transistor
and MOSFET turn off, thus prevent-
ing current flow. This simple circuit
provides reverse-battery protection in
both charger and battery paths, there-
by protecting the battery, the charger,
and the load. You can use a microcon-
troller to measure battery current and
make a decision on appropriate action,
as well.EDN

FROM V1 TO
CHARGER LOAD
BATTERY R2 �
LOAD 1k
CHARGER 13V BATTERY
�
R1
10k
CURRENT
Q1
2N2907A SENSE

CHARGING LOAD
PATH PATH Q2
R3
BATTERY 10k IRF150

Figure 1 Batteries provide power to a load when utility Figure 2 MOSFET Q2 protects the battery from exces-
power is off. sive current.
edn081113di4371 DIANE

50 EDN | february 5, 2009 edn081113di43712 DIANE

Voltage doubler improves accuracy verse beta of the bipolar transistors is
small; consequently, the operation of
S Chekcheyev, Tiraspol, Moldova the reversed transistors in Figure 1 is
similar to the operation of the reverse-


The voltage doubler in Figure 1 of the forward-biased diodes in Figure biased diodes in Figure 2. Both cir-
provides more accurate voltage 2. The collector-emitter voltage of the cuits underwent tests with a resistive
doubling than does the conventional saturated bipolar transistors, however, load of 10 kV and a 50-Hz, 2V-ampli-
voltage doubler in Figure 2 because it is substantially smaller than the voltage tude sinusoidal signal applied to the
uses transistors instead of diodes. You can across the forward-biased diodes. Thus, input. The measured output voltage of
express the output voltage of the con- the error of doubling decreases. the conventional voltage doubler was
ventional doubler as VOUTDC52VINAC Transistors Q1 and Q2 are reverse-bi- 2.8V, and the error of doubling was
22VD, where VOUTDC is the output dc ased during the negative and the posi- 232V22.8V51.2V. The measured
voltage, VINAC is the amplitude of the tive half-cycles, respectively. The re- output voltage of the proposed voltage
input ac voltage, and VD is doubler was 3.8V, and the error of dou-
the voltage across the for- bling was 232V23.8V50.2V.EDN
Q2
ward-biased diodes. The C1
error of the conventional 470 �F 470 �F
BC547C 1N4005
voltage doubler is 2VD. R1
VINAC C2 VOUTDC
Transistors Q1 and Q2 in 47k
R2 470 �F
Q1
Figure 1 are saturated 47k VINAC
1N4005 470 �F VOUTDC
during the positive and BC547C
the negative half-cycles,
respectively, of the input
ac voltage. The operation Figure 2 A conventional voltage doubler
Figure 1 An improved voltage doubler uses tran-
of the saturated transistors uses diodes.
sistors for better accuracy.
is similar to the operation

edn081205di43851 DIANE
edn081205di43852 DIANE

february 5, 2009 | EDN 51

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Digital controller compensates

analog controller D Is Inside
David Caldwell, Flextek Electronics, Carlsbad, CA 51 Circuit provides constant-cur-


Emerging digital ICs for power
control lack basic features, such
as the built-in gate drive and current
limiting, that you would normally find
in analog ICs. Digital-power control-
lers generally have only PWM (pulse-
width-modulated)-logic output, and
discrete gate drivers rarely include cur-
rent limiting. In addition, most pro-
tected FETs work only in low-frequen-
cy, low-side applications.
The LM3485 IC from National
Semiconductor (www.national.com)
rent load for testing batteries
includes high-side gate drive with cur-
rent limiting (Reference 1). However, 52 MOSFET-based, analog circuit
the hysteretic-control scheme of this calculates square root
analog IC is likely to yield questionable
54 “Hippasian” nonlinear VFC
performance in some applications due
stretches dynamic range
to variable switching frequency and
overshoot, as well as an inability to reg- 57 Decoder lights the way
ulate feedback below the 1.24V refer-
ETo see all of EDN's Design
ence. A traditional PID (proportional-
Ideas, visit www.edn.com/design
integral-differential)-control scheme
ideas.
can get around these limitations but
adds considerable complexity.
The CLZD010 CLOZD (Caldwell-
12V
INPUT-VOLTAGE RANGE: 6 TO 28V

CURRENT LIMIT: 5 �A�48.7k�/0.12=2A

NONDISSIPATION
CURRENT SENSE ANALOG LM3485 48.7k 0.001 �F
1 8
ISNS VIN
2 1.24V 7
GND � GATE
FDC5614P
3 6
NC GND
4 � 5
FBK IADJ
SWITCHED
PWM PULSE POWER
TRAIN TEMPERATURE FEEDBACK

5V 5V CONTROL POWER
LP2950 LM34
PRECISION DIGITAL CLZD010 TEMPERATURE HEATER
LINEAR SENSOR LOAD
REGULATOR 1 HEN 18
FBK A
2 D LEN 17
2.2 �F REF
3 16 100 �F
5k SPT C STA
TEMPERATURE- 4 15
BIP TIM
SETPOINT 5 C 14
GND � � VDD MBRS-
ADJUSTMENT 6 13
PS0 DSP O CS3 140T3
P
7 CS2 12
PS1 W M
8 11
PS2 P CS1
9 M 10
PWM CS0

PWM SETTING: COMPENSATION

31.2 kHz SETTING: 134 SEC

Figure 1 Combine the simple and robust closed-loop control of the digital CLZD010 with the current-limited high-side
gate drive of the analog LM3485 for the best of both worlds.

48 EDN | february 19, 2009

edn080918di43441 DIANE
(PLACED IN 10-2 FOLDER)
designideas
loop-optimization-in-Z-domain) con- rameters, eliminating complex stabil- closed-loop control of the digital
troller-chip IC from Flextek Electron- ity analysis. The circuit requires no PC CLZD010 with the current-limit-
ics (www.flex-tek.com) both broadens interface because you inspect the open- ed high-side gate drive of the analog
and simplifies control applications loop response and then use pin settings LM3485 for the best of both worlds
though the embedded intelligence of to configure the closed-loop compen- (Figure 1). The PWM-logic level of
a digital device (Reference 2). A sin- sation. However, the PWM output is the digital IC overrides the hysteretic
gle time-domain compensator replaces only a logic-level driver. comparator of the analog IC to switch
the three frequency-domain PID pa- Combine the simple and robust the FET. A second comparator at
ISNS, Pin 1 in the LM3485, turns off
250
the FET if the voltage across it exceeds
200 a predetermined value during conduc-
tion to limit current.
150
TEMPERATURE In the thermal-response example
(�F) 100 (Figure 2a), the circuit takes about
OPEN LOOP three minutes for the open-loop tem-
50
CLOZD* perature to reach roughly two-thirds of
0 its final value, so closed-loop compen-
0 1 2 3 4 5 6 7 8 9 10 sation, at 134 seconds, is slightly fast-
TIME (MINUTES)
er in Figure 1. The resultant closed-
* CALDWELL-LOOP OPTIMIZATION IN Z DOMAIN
(a) loop temperature quickly nears its final
14 value due to maximum drive; voltage
12 then decreases to allow the tempera-
10 ture to settle at the setpoint without
8 overshoot (Figure 2b). You can use
VOLTAGE (V) 6 this basic circuit combination to satis-
4 edn080918di43442a DIANE OPEN LOOP fy a broad range of applications in mul-
2
CLOZD*
tiple industries.EDN
0
0 1 2 3 4 5 6 7 8 9 10 R e fe r e nce s
TIME (MINUTES)
1 “LM3485 Hysteretic PFET Buck
(b) * CALDWELL-LOOP OPTIMIZATION IN Z DOMAIN Controller,” National Semiconductor,
September 2004, www.national.com/
Figure 2 In the thermal-response example (a), the circuit takes about three
ds/LM/LM3485.pdf.
minutes for the open-loop temperature to reach roughly two-thirds of its final
2 “CLOZD Loop Controller Chip,
value. The resultant closed-loop temperature quickly nears its final value due
Part CLZD010,” Flextek Electronics,
to maximum drive; voltage then decreases to allow the temperature to settle at
2004, http://flex-tek.com/CLZD010.
the setpoint without overshoot (b).edn080918di43442b DIANE
pdf.

Circuit provides constant-current the battery’s output voltage, using IC1,

IC2, and Q3. Your choice of current
load for testing batteries depends on battery size. You calculate
the sink current of this circuit as ITEST5
Vladimir Rentyuk, Modul-98 Ltd, Zaporozhye, Ukraine 1/R 193[V CC3R 18/(R 41R 18)], where


Suppose that you need to test a
1.5V, AA-size alkaline battery.
You can apply a short circuit and mea-
sure current, or you can measure open-
circuit voltage, but neither method
properly tests the battery. A suitable
test current of approximately 250 mA
gives you a more reasonable test. You
can use a 6V resistive load at 1.5V,
which produces an output voltage of
1.46V at an ambient temperature of
258C if the battery is in excellent con-
dition. A poor battery might produce
less than 1.2V. Given the load, the
output current at 1.2V will be 200 mA
instead of 250 mA. The battery will
have just 80% of a full load current. In-
stead, you can use the circuit in Figure
1 to produce a constant-current load.
The circuit uses a 9V battery and a
voltage regulator to produce a steady
power-supply voltage of 5V. From that
voltage, the circuit produces a constant
sink current, which is independent of
ITEST is the current you are testing and
VCC is the voltage of resistive divider R4
and R18.The voltage across R19 should
range from 0.3 to 0.85V for AAA and
AA batteries. Transistor Q3 should be
in its active region. Resistor R14 limits
Q3’s base current to a safe level.
A suitable choice for the operation-
al amplifier, IC2, is also important. You
should use a single-supply op amp with
a rail-to-rail input and a rail-to-rail
output, such as Analog Devices’ (www.

february 19, 2009 | EDN 51

designideas
IC1 3
5V 1
VOUT L78L05BUTR VIN
R1 D1 GND
C2
1k 330 nF BAS32L 2 C1 � Q1
R2 100 �F IRLML5103
D2 R3
1.5k 16V
R4 BAS32L 20k
6.8k
1% D3
R5
GREEN
6.8k
TEST
4 D4
� 2
R6 GREEN
OPTIONAL 6.2k IC2A 1 EXCELLENT R7
MULTIMETER BH1 1.46V 3 10k
B1
� R10 9V
ITEST=250 mA R8
510 680k R9 6F22
1.5k �
� 1%
R11
2k BCW33
BATTERY Q2
UNDER TEST
R15 R12
2k 100k
� 9 D5
5 R14 BC817-40
IC2C 8 YELLOW
7 1k
IC2B Q3 1.33V 10 GOOD
6 R16
R21 1.5k
VREF OP484ES
680k
0.825V
R17
R13 OPTIONAL 510
1.6k SELF-TESTING 1% 13 D6
R18 R19 1% 14
IC2D RED
1.2k 3 1.2V 12 POOR
1% 1% 4
0.25W R20
R22
330
4.7k R23
1%
1% 680k

Figure 1 A tester of AA- or AAA-sized batteries uses constant-current load.

test has enough volt- When you connect a battery to test,

tABLE 1 VOLTAGE RANGES FOR LEDs age to be tested. LEDs you should test it for at least 5 seconds.
Battery D4, D5, and D6 indicate LED D3 shines if the battery is in rela-
Condition voltage1 (V) D2 D4 D5 D6 D3 the battery’s condition. tively normal condition. In this case,
Excellent >1.46 Yes Yes No No Yes Table 1 shows the volt- switch Q1 applies power to the bat-
Good >1.33 Yes No Yes No Yes
age ranges necessary for tery tester. The sink-current generator
these LEDs to light. comprising IC2A and Q3 loads the bat-
Poor >1.2 Yes No No Yes Yes Op amps IC2A, IC2C, tery under test, and the resistor-divider
Bad >12 Yes No No No Yes and IC2D work as com- network sets the comparator voltages.
Unable to >12 No No No No No parators with
edn081113di43771 DIANEsome hys-
(SAVED IN THE 12-5 FOLDER)
You can add an optional self-testing
test teresis for operational button for checking the 9V battery to
stability. The resistive ensure that it has enough voltage to
1
Ambient temperature is 258C.
2
This estimated value can be less. divider comprising R5, drive the circuit. You can also connect
R6, R8, R17, and R22 sets a digital multimeter to the multimeter
analog.com) OP484ES or OP496GS. the voltage levels. Diodes D1 and D2 terminals if you need a more accurate
When you connect the battery under are optional but are useful when you measurement. You can use a suitable
test, Q2 turns on, which then turns on need to operate the circuit outdoors, rotary switch or a variable resistor and
Q1, applying voltage from the 9V bat- where temperatures vary widely. Re- change the value of the test current by
tery to the regulator. That action lights sistor R15 protects the inputs of IC2A, changing the value of R4 to test anoth-
D3, indicating that the battery under IC2C, and IC2D. er type or size of battery.EDN

MOSFET-based, analog circuit mean-square) value of an arbitrary

waveform, for example. Hence, design-
calculates square root ers need an effective analog square-
root calculator. Because manufacturers
Abhirup Lahiri, Netaji Subhas Institute of Technology, New Delhi, India do much of the IC fabrication in MOS


Square-root-calculating circuits tion and measurement systems for technology, a MOSFET-based, analog
find wide use in instrumenta- such tasks as calculating the rms (root- square-root calculator seems appropri-

52 EDN | february 19, 2009

designideas Equation for 081002di 4330
Equation 1

ate. This Design Idea describes such a the identical transistors forming the root of the difference of input voltag-
circuit, which uses onlyEquation
MOSFETs 1 to MOS-resistive  1  V and V
1 and
VO =  circuit,
  I O1A, B
es V1 and V2. If you ground V2, then
provide the square-root function (Fig- are control voltages  K1  to the gate the output voltage is proportional to
K 2 applied
ure 1). The design is simple and ver- of the MOSFETs that are working in the square root of input voltage V1.
satile and can provide the output 1 as1  the triode. This approach provides the As noted, control voltages VA and VB
O = 
the square root of theVdifference I O1 ,
two  advantage
of of voltage controllability of can vary the proportionality constant.
 K 2 K1 
voltages. the output; hence, the square-rooting Hence, you have devised a new all-
The circuit uses the nested con- function is voltage-controllable. MOSFET-based, voltage-controllable
Equation 2
nection of MOSFETs Q1 and Q2. Q2 The following equation gives the analog square-root calculator.
works in the saturation region as it is output voltage: You can test the circuit using a va-
diode-connected, forcing Q1 to work riety of commercially available MOS-
in the triode for
region. Equa tion 2MOS-
Alldiother  1 1 1  FETs, such as the 2SK1228, which is
Equation 081002 4330 VO = 2  +   × K(VAVB )(V1V2).
FETs work in the triode region. The  K K K available from many sources; the buf-
 1 2 2 
first part of the circuit, comprising Q3, fer can be a MOSFET-based op-amp
Q4, Q5, and Q6, creating the  current
1 1 1  buffer, such as the BUF04701 from
VO = 2 
IO1, is basically a MOS-resistive +cir-   × K(VAVB )(V1V2). Texas Instruments (www.ti.com). For
Equation 1  K1 K 2 K2 
cuit. The essential equation  govern- the operation of the circuit to be in
ing the circuit operation is: It is evident from this equation that accordance with the output-voltage
the output voltage, VO, is the square equation, the four MOSFETs you use
 1 1  to create the MOS-resistive
VO =    I O1 ,
 K K circuit should be identical
 2 1 
Q3 and should work in the tri-
where K 1 and K 2 represent ode region, for which inputs
the aspect ratios of transis- V1 VA IO1 V1 and V2 should be less than
tors Q1 and Q2, respective- VA2VTH and VB2VTH, re-
ly: KI5(mCOXW)/2LI, where Q4 spectively. The MOSFETs in
I5KEqua
1
5K tion 2
2
. The MOSFETs cre- Q1
the current mirror, Q7 and Q8,
VB
ating the MOS-resistive circuit should be identical, and the
and hence responsible for the 1 V0 diode-connected MOSFETs,
 1 are1identical,
current creation 1  Q5 Q Q1 and Q2, should be differ-
VO = 2  +   × K(VAVB )(V1V2). 2
having the same aspect ratio ent and have different aspect
 K1 K 2 K2  Q 7 Q8
VB
and threshold voltage. The V2 ratios. You can test the circuit
current relates to inputs V 1 onboard using commercially
and V2, as the following equa- Q6 available ICs, or you can sim-
VSS
tion shows: IO15G(V12V2), VA
ulate it on a computer using
where G52K(VA2V B) and any standard version of Spice.
represents the conductance The supply voltage must be in
of the MOS-resistive cir- Figure 1 This circuit uses only MOSFETs to provide accordance with the selected
cuit—k5(mC OX W)/2L—of the square-rooting function. components.EDN

“Hippasian” nonlinear VFC of linear VFC conversion is equal to

stretches dynamic range the full-scale voltage reference, VREF,

divided by full-scale frequency, fFS,
multiplied by the counting interval,
W Stephen Woodward, Chapel Hill, NC edn081002di43301 DIANE
large dynamic range is inevitably as-


Hippasus of Metapontum was
a Greek philosopher who lived
approximately 500 BC. A disciple
of Pythagoras, Hippasus discovered
some interesting properties of square
roots. This Design Idea describes a
VFC (voltage-to-frequency convert-
er) that also uses an interesting prop-
erty of square roots: their ability to
extend VFC dynamic range by orders
of magnitude (Figure 1).
Linear VFCs are one of the old-
est types of ADCs, and their simplic-
ity and noise rejection preserve their
popularity. However, their Achilles’
heel is the direct proportionality be-
tween dynamic range and conversion
time. Because the voltage resolution
sociated with long counting intervals
and slow conversion, even when clever
VFC design provides for fast full-scale
frequency.
For example: If you use a 3-MHz
VFC-based ADC, such as Analog De-
vices’ (www.analog.com) AD7742 with
a 2.5V reference voltage in a design
that requires 1-mV resolution, then

54 EDN | february 19, 2009

designideas
VDD UNI/BIP PD

GAIN
AD7742
POWER-DOWN
VIN1 LOGIC

VIN2 VOLTAGE-TO- fOUT

INPUT X1/X2 FREQUENCY
MULTIPLEXER MODULATOR FOUT=FFS VIN .
VIN3 � VREF

VIN4

A1
CLOCK 2.5V
A0 GENERATION REFERENCE

5V
RC�VFC COUNTING INTERVAL.
GND CLKIN CLKOUT REFIN REFOUT 4
2 SD1 6 R R
5V 2.5V D1 Q1 �
� 5V A2
10 14
A1 VDD �
SD2 � C
D2 0.1 �F 74AC74 C
2k
12 Q2 9 2FFS 3 CP 5
1 Q1
C
CLOCK 74AC74
11 2k VSS CD1
SOURCE CP2 8
Q2 F 7 1
�12 MHz=4FFS
CD2 VREF=2.5V OUT
FFS 5V
13
5V

0 TO 100% FULL-SCALE 0 TO 4% FULL-SCALE 0 TO 0.04% FULL-SCALE

1 0.1 0.01

0.9 0.09 0.009

0.8 0.08 0.008

LINEAR
0.7 0.07 0.007
HIPPASIAN HIPPASIAN
0.6 0.06 0.006
RESOLUTION
0.5 0.05 0.005

0.4 0.04 0.004

HIPPASIAN
0.3 0.03 0.003

0.2 0.02 0.002

edn090219di4318fig1top mike LINEAR
0.1 0.01 0.001 LINEAR
0 0 0
0 0.20 0.40 0.60 0.80 1 0 0.01 0.01 0.02 0.02 0.03 0.03 0.04 0.04 0 0.0001 0.0002 0.0003 0.0004
VIN/VFS VIN/VFS VIN/VFS

Figure 1 This nonlinear, wide-dynamic-range voltage-to-frequency converter exhibits 25-times improvement in counting time over
other approaches.

you would need a minimum counting
interval of 2.5/1 mV/3 MHz52500/3
MHz5833 msec. That counting inter-
val yields only 1200 conversions per
second, which for many applications is
inconveniently slow.
The “Hippasian” VFC avoids this
problem with a semiparabolic-trans-
fer function instead of a linear one.
It works by substituting VREF2, which,
instead of the constant VREF of a lin-
ear VFC, is proportional to the output
frequency. Then, VREF25VREF3fOUT/fFS,
f OUT5V IN3f FS/V REF25V IN3f FS/(V REF
3fOUT/fFS), (fOUT/fFS)25VIN/VREF, and
fOUT5fFS3(VIN/VREF)1/2.
Generating the dynamic, output-fre-
quency-proportional reference voltage
is the job of op amps A1, which boosts
the VFC’s internal 2.5V reference to
power flip-flop Q1, and Q1 and A2,
which compose a high-performance
frequency-to-voltage converter. The
accuracy of the reference voltage de-
pends on precise 50-to-50 symmetry of
the VFC’s input-clock reference. Flip-
flop Q2 guarantees this symmetry.
The effect on conversion resolu-
tion of low-level signals is dramatic.
To return to the example of a 2.5V
full-scale, 1‑mV-conversion resolu-
tion, which requires a 2500-count,
833-msec conversion interval with
a linear 3‑MHz VFC, the Hippasian
version needs only 100 counts and 33
msec—a 25-fold improvement. Soft-
ware linearization of the Hippasian
VFC conversion is easy, requiring only
one multiplication.EDN

56 EDN | february 19, 2009

Decoder lights the way �

R6
Jean-Bernard Guiot, Mulhouse, France R1 6.8k
D1


10k
To display the status of two digi-
that resolves this problem by display- Q1
tal outputs, you can simply con-
ing four states on four LEDs (Figure
nect an LED and its resistor on each
1). The operator need not understand R3
R2
220
output. You must, however, interpret,
binary coding, and, if no or more than D2 220
B A
or “decode,” the displayed binary code.
one LED lights, it can mean only “no
R4
In addition, when no LED lights, users
power” or “default.” 220
have no way of knowing whether it
The circuit works in the following D3

means that both outputs are off, that

way: If both inputs A and B are low, Q2
R5
the power is off, or that a malfunction
Q1 allows current to pass through D1 10k R7
has occurred. In some applications,
and resistor R2 to A; only D1 will light. 6.8k D4

including industrial and medical set-

Symmetrically, if both inputs A and
tings, an indicator sending an ambigu-
B are high, Q2 passes, and the current Figure 1 This simple circuit dis-
ous signal would be unacceptable. This
can pass from A through R4, Q2, and plays four states on four LEDs.
Design Idea describes a simple circuit
D4; only D4 will light. If both inputs
are on different levels, the current for one LED must drive
edn080918di43511 the
DIANE
Table 1 LED-lighting possibilities only D2 or D3 will light. A and B inputs. Resistors R2, R3, and
IN LED Table 1 shows the possi- R4 are for applying a 12-mA LED cur-
A B 1 2 3 4 bilities; all other displays rent if the power supply is 5V. No com-
point to a default, such ponent is critical. For example, you
0 0 1 0 0 0
as a bad connection, a can use generic transistors, such as the
0 1 0 1 0 0 no-power condition, or a NPN 2N3904 and the PNP 2N3906.
1 0 0 0 1 0 malfunction. You can even use transistors with inte-
1 1 0 0 0 1
A totem-pole output grated base resistors, further reducing
that can sink and source the component count.EDN

february 19, 2009 | EDN 57

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Microcontroller converts digital- D Is Inside

temperature-sensor readings 44 Discrete-component buck

without floating-point arithmetic converter drives HB LEDs

47 Drive a single-coil latching relay
Jordan Dimitrov, Toronto, ON, Canada without an H-bridge circuit


Digital temperature sensors a high-level language and a compiler. EDNswitches
081016di 4256 equations
48 Limit control
combine a sensor, an ADC, Development time is short, and per-
dc-motor H bridge
and a serial interface in a single chip. forming even complex calculations is
They feature wide enough measure- EDN
not a problem. However, compilers 081016 di 4256 equations
50 Implement a clip-detection
ment range, good accuracy and resolu- produce machine code that occupies circuit for BTL Class D amplifiers
Equation 1
tion, no need of external parts, easy in- more memory and runs at lower speed
ETo see all of EDN's Design
terface to microcontrollers, small size, than code from an assembler. Also,
Ideas, visit www.edn.com/design
and low price. In a review of 10 digital compiler IDEs (integrated develop-
Equation 1
ideas. 5 N N  1
sensors from seven companies, all parts ment environments) cost hundreds tC = × NS =  S + S  × .
deliver signed-number data in two’s- of dollars, whereas many companies 80  2 8  10
complement format. They feature tem- offer free assembly-language IDEs. 5 If To get
 NS NS  1readings in degrees Fahrenheit,
perature ranges of 225 to 185 or 240 you work on a tight budget t C =or memo-
× NS =  use +the following
× . equation, which
80  2 8  10
to 11258C, accuracy of 0.5 to 2 or 2 ry-space allotment, assembly language converts degrees 2Celsius into degrees
Equation
to 48C, and output data of 9 to 13 bits is the better option. The problem is Fahrenheit: tF5[(9/5)3tC132]. Re-
with 0.5 to 0.03128C resolution. The to find a simple way to avoid the nec- placing tC from the above equations
devices’ conversion time is 26 to 750 Equation 2 to yields:
essary floating-point calculations
msec, and they use an SPI (serial-pe- convert sensor data into human-un- N
9 5   1
ripheral interface), an I2C (inter-inte- derstandable format, both in Celsius t F = × × NS + 32 =  NS + S + 320  × .
grated-circuit), or a 1-Wire interface. and Fahrenheit. This Design Idea 5 80  (2) 8  10
Power supplies are 1.5 to 3.6 or 3 to presents an effective approach. 9 5  N  1
t = × × NS + 32 =  NS + S + 320  × .
5.5V, and prices range from 80 cents to Consider the TMP121Fsensor 5 80from  8  10
$2.10 (1000). Texas Instruments (www.ti.com).
These sensors connect to microcon- It provides 13-bit data in a 16-bit The benefit of equations 1 and 2 is
trollers; hence, size, speed, and time frame with resolution of 0.06258C/ that you can perform the calculations
to develop firmware are also impor- bit. Hence, the transfer function is with integer arithmetic only. They
tant. The standard approach is to use tC50.06253NS, where tC is the tem- require divisions by powers of two,
perature in degrees which you can replace with shifts,
Celsius and N S is and division by 10, which you per-
VCC
TMP121 68HC11 LCD
the
EDNsensor
081016didata form by introducing a decimal point
4256 equations
after you remove in the display.
SCK SCLK the three meaning- The circuit underwent testing with
SO MISO EDN21.6�C
081016di 4256 equations
CE less least-significant the popular 68HC11 microcontroller
�C OC2 VCC bits. You can
Equation 1 easily from Motorola (www.motorola.com,
PA7 SS rearrange the above Figure 1). Besides a sensor and a
�F equation to: controller, it includes a unit-selec-
Equation 1 tion switch and a dot-matrix LCD.
5 N NS  1
tC = × NS =  S +The display
× . resolution is 0.18. The
80 2
(1) core 8 of 1the0 supporting firmware is an
Figure 1 A small system uses a 68HC11 microcon-
5 N N  1 endless loop in which the 68HC11
t C =data,× NS =  S + S  × .
troller to read a switch and a sensor, to convert
and to display temperature. 80  2 8  10 uses an output-compare function to
Equation 2 generate a square-wave signal with a

Equation 2

9 5  N march  15, 2009 | EDN 43

tF = × × NS + 32 =  NS + S + 320  × .
edn081016di43561 DIANE 5 80  8  10
designideas
period of 1 sec and a duty cycle of
50%. The OC2 signal connects to
the CE input of the sensor and con-
trols its operation: When CE is high,
the sensor measures temperature. The
HC11 does nothing except display
M on the LCD. When CE becomes
low, the last measurement latches in
a shift register inside the sensor. The
HC11 deletes M from the display,
reads the switch and the sensor, ma-
nipulates the data, and displays the
temperature.
Equations 1 and 2 provide the
basis for two source codes. Listing 1,
available at www.edn.com/090305dia,
generates machine code of 981 bytes.
Listing 2, also available at www.edn.
com/090305dia, generates machine
code of 392 bytes. Despite the C-lan-
guage approach with integer arithme-
tic, it needs 2.5 times more memory to
do the job. The ratio is well above 10
if the C code goes with equations that
need floating-point arithmetic. The
benefit is clear: Modified equations
1 and 2 and assembly-language pro-
gramming let you select a microcon-
troller with less memory and reduce
the price of your design.EDN

Discrete-component buck converter using only discrete components. It re-

quires two bipolar transistors, a P-chan-
drives HB LEDs nel MOSFET, an inductor, a Schottky
diode, and a few resistors (Figure 1).
Dhananjay V Gadre, Netaji Subhas Institute of Technology, New Delhi, India
When you switch on the battery


HB (high-brightness) voltage, the voltage across
S1
LEDs require a large R1, the resistor in series with
amount of current to operate. the HB LED, is 0V. Thus,
R2
When driving HB LEDs from a 3.9k
transistor Q2 is off, and Q1 is
IRF9540
voltage source, you can set the in saturation. The saturated
R3
required current with a suit- 3.9k
state of Q1 switches on the
able series resistor. If the volt- � BATTERY MOSFET, thereby applying
age source is a battery, then, as � Q1 the battery voltage to the
L1
the battery drains, the LED’s 130 �H LED through the inductor.
BC547 D2
intensity decreases. Also, a se- Q2
1N5819 As the current through resis-
ries resistance has the disadvan- BC547
tor R1 increases, it turns on
tage of power loss through the Q2, which turns off Q1 and
D1
resistor. A better option is to thus turns off the MOSFET.
use a suitable dc/dc converter. During the MOSFET’s off
If the LED’s turn-on voltage is R4 R1 � C1 state, the inductor contin-
470 3.6 10 �F
lower than the battery voltage, 25V
ues to supply current to the
as would be the case with a 6V LED through Schottky diode
sealed-lead-acid battery, then D2. The HB LED is a 1W,
you can use a buck converter white Lumiled (www.philips
Figure 1 A buck converter provides current sufficient
(references 1 and 2). You can lumileds.com) LED. Resistor
to drive a high-brightness LED.
build a simple buck converter R1 helps control the LED’s

edn080918di43581 DIANE

Figure 2 In a SwitchCAD simulation, the upper trace is

the MOSFET-drain voltage, and the lower trace is the Figure 3 In an oscilloscope screenshot, the upper trace is the
base voltage of Q1. MOSFET-drain voltage; the lower trace is Q1’s base voltage.

44 EDN | march 5, 2009

designideas
intensity. Using a larger value for R1
reduces the intensity.
The SwitchCAD-III software,
which is available as a free download
from Linear Technology (www.linear.
com), simulated the circuit; the simu-
lated MOSFET was an International
the MOSFET-drain waveform and
the voltage at Q1’s base. The circuit
was wired on a prototyping board and
tested for various supply voltages. Fig-
ure 3 shows oscilloscope screenshots
for the MOSFET-drain voltage and
the voltage at the base of Q1. They
R e fe r e nce s
1 Saab, Alfredo H, and Steve Logan,
“High-power LED drivers require
no external switches,” EDN, July 19,
2007, pg 78, www.edn.com/article/
CA6459061.
2 Gadre, Dhananjay V, “Buck

Rectifier (www.irf.com) IRF9Z24S fairly well match the simulated wave- regulator controls white LED with
instead of an IRF9540 because the form. Conversion efficiencies were optical feedback,” EDN, Oct 25,
model for IRF9540 is not available 60 to 95% for supply voltages of 6 to 2007, pg 72, www.edn.com/article/
in SwitchCAD-III. Figure 2 plots 10V.EDN CA6491146.

Drive a single-coil latching relay the relay in its set position. The relay

without an H-bridge circuit maintains its position even when you

remove the coil current, which saves
power after the relay latches.
Carlos Cossio, Santander, Spain
Latching relays have advantages


Single-coil latching relays find directions. Current flowing from the over classic relays because, as soon as
use in signal-routing, audio, and latching relay’s positive pin to the neg- the relay switches, it remains in that
automotive systems. To maximize their ative pin causes it to latch in its reset position without consuming energy.
usefulness and cut power consumption, position. Current flowing from the Thus, no current consumption means
these coil currents must flow in both negative pin to the positive pin latches less heat, smaller heat sinks, and a dra-
matic increase in battery life for porta-
3.3V 5V 5V ble devices. In some cases, the use of a
40.61.6.005 latching relay lets your greatly simplify
a circuit.
3.3V 3.3V
QE128 4.7k 47 Although latching relays boast sig-
4.7
31 nificant advantages over classic relays,
3
RESET their use appears limited to niche ap-
VDD
100 nF plications because they require more
4
VREFH
attention to design details. In general,
a latching relay’s drive circuit is slight-
�
100 nF 100 nF ly more complex than that of a clas-
10 �F ULN2003
5
VREFL sic relay. The traditional approach to
18 1 16
PTB0 driving a latching relay is to use an H-
2 15 bridge circuit, which can be costly and
6
VSS difficult to handle. In addition, you
3 14 must design a demagnetization circuit
using a special resistor to limit the cur-
PTB1 17 4 13 rent in compliance with the manufac-
turer’s specifications.
MC9S08QE128 5 12
Figure 1 shows a simple circuit using
6 11 the MC9S08QE128 microcontroller
from Freescale (www.freescale.com)
7 10 5V to drive a Finder (www.findernet.
com) 40.61.6.005 single-coil latching
8 9 relay with a standard ULN2003 Dar-
lington driver with open-drain outputs
and inductive-kickback protection.
Clamping diodes on each ULN2003
Figure 1 You can drive a single-coil latching relay without an H-bridge circuit, output pin catch high-voltage tran-
greatly simplifying hardware design and making the most of the low-power-con- sients that occur when you interrupt
sumption features inherent to latching relays in portable-system applications. the coil current. Because demagne-
tization uses low-value resistors, you

edn081113di43811 DIANE

march 5, 2009 | EDN 47

designideas
must wire at least two open-drain buf-
fers of the ULN2003 to both endings
of the relay coil to ensure enough cur-
rent when the microcontroller pulls
down.
Listing 1, which is available in the
Web version of this Design Idea at
www.edn.com/090305dib, shows the
software procedure to latch the relay
to its set or reset position by turning
on the corresponding microcontroller
output for at least 50 msec. The cur-
rent flows into the ULN2003 open-
drain output and latches the relay to
its set or reset position, according to
the direction of the coil current. As
soon as the relay latches, drive the
corresponding microcontroller output
low to turn off the ULN2003 open-
drain buffer to ensure the lowest
power consumption. You must, how-
ever, take into account the set/reset
timing. Pull the microcontroller out-
put low only after the required time
has elapsed. Waiting ensures that the
relay will properly latch to its intend-
ed position.EDN

Limit switches control


You use limit switches to
dc-motor H bridge switch off a motor if it reach-
es one of its two end positions. Even
Andreas Grün, Wedemark, Germany if you build a microprocessor-based
motor controller, you should switch
off a motor with hardware by build-
ing a safety interlock. Such a circuit
M �V works by inhibiting movement in one
�V �
NC NC direction but allowing movement in
the other direction when the motor
retracts from its end position. Figure
Figure 1 This circuit works by inhibiting movement in one direction but allow- 1 shows the circuit with mechanical
ing movement in the other direction when the motor retracts from its end switches. However, this ancient me-
position. chanical approach may be unsuitable
in some cases because the motor cur-
edn080809di43351 DIANE

M
NC NC
NO NO

Figure 2 This circuit shortens one input of the H bridge Figure 3 This circuit interrupts the connection to the driving
to ground so that movement is possible only in the other circuit of one input and sets the input to low using a pull-
direction by turning on the other input. down resistor.

edn080809di43352 DIANE
edn080809di43353 DIANE
M

Figure 4 This circuit is the same as that in Figure 3, and

it works with phototransistors without modification. Figure 5 This circuit is the same as that in Figure 4; the
value of the resistors depends on the parts you use.

edn080809di43354 DIANE
edn080809di43355 DIANE

48 EDN | march 5, 2009

designideas
rent may be too high, or the switch-
es may be closing switches or light
barriers.
If you use an H bridge to drive the
motor, you can achieve the same op-
eration in a more versatile way. The
circuit in Figure 2 shortens one
input of the H bridge to ground so
that movement is possible only in
the other direction by turning on the
other input. If the switches are open-
ing at the end positions, the circuit in
Figure 3 interrupts the connection to
the driving circuit of one input and
sets the input to low using a pulldown
resistor. The same circuit works with
phototransistors without modifica-
tion (figures 4 and 5). The value of
the resistors depends on the parts you
use; a value of 10 kV should work in
most designs.EDN

Implement a clip-detection circuit TAS5414/5424, have on-chip clip-

detection circuits, but these ICs use a

for BTL Class D amplifiers common clip-detection pin, compris-

ing hardware ORed inside the IC, for
Dimitri Danyuk and Rich Lenser, Niles Audio, Miami, FL all four channels. Other Class D am-
plifiers lack the clip-detection feature


Clip detection is a convenient
feature in Class AB amplifiers.
It produces a signal from a clip-detec-
tion pin that drives an automatic vol-
ume control, which reduces gain com-
pression and distortion when the am-
plifier is overdriven. Class AB ampli-
fiers, such as the STMicroelectronics
(www.st.com) TDA7293, TDA7396,
STA7360, and STA540 and the
Toshiba (www.toshiba.com) TA8275
and TB29xx, have on-chip clip-detec-
tion circuits. Newer Class D automo-
tive amplifiers, such as the four-chan-
nel STMicroelectronics TDA7454 and
the Texas Instruments (www.ti.com)
VCC
altogether, but you can implement it
with external components.
An analog-input Class D amplifier
comprises PWM (pulse-width-modu-
lation) logic, gate-drive circuits, and
a power stage. The PWM logic trans-
forms the analog-input signal into a
PWM signal. The power stage with

Q3

GATE OUT�
DRIVE Q4

PWM
LOGIC
Q5

OUT� VCC 3.3V

GATE
DRIVE Q6 D1
MMBD4448
R1
D2 100k R4
MMBD4448 10k

BTL-CLASS D-AMPLIFIER IC D3 TO MICRO-

MMBD4448 Q2 CONTROLLER
PGND
R2
10k MMBT2222
D4
MMBD4448
Q1
R5 C2
MMBT2222 100k 10 �F
C1 R3
4.7 nF 10k
TO SECOND
CHANNEL

Figure 1 Adding several components to the BTL-Class D-amplifier IC provides a clip-detection function. A peak detector,
comprising Q2, R5, and C2, is optional.

50 EDN | march 5, 2009

edn081018di43451 DIANE
designideas
the gate drivers transforms the low- R2, and R3 and the voltage drop across the existence of clipping (Figure 2).
power PWM signal into a high-volt- diodes D1 through D4 set this thresh- Capacitor C1 filters the residual of the
age, high-current PWM sequence. A old, which is 0.5V with respect to pow- switching- and high-frequency content
BTL (bridge-tied-load) amplifier ba- er ground, PGND, for the given compo- of the audio signal.
sically comprises two gate-drive cir- nent values. A positive-going pulse ap- A simple application involves fil-
cuits and two power stages, which the pears on the collector of Q1 whenever tering and integrating the pulses with
same PWM signal drives. The signal the output voltage is below the thresh- further automatic reduction and resto-
directly drives one gate-drive circuit old with respect to power ground. This ration of the volume setting using the
and phase-inverts the other. In theo- pulse alerts the host microcontroller to microcontroller’s driven-volume con-
ry, a BTL amplifier can produce trol to counteract the clipping dis-
four times more power into the tortion. You can also implement
same load than a single-ended more sophisticated algorithms
amplifier. (Reference 1). A suitable peak
Figure 1 illustrates the imple- detector comprising Q2, R5, and
mentation of an external clip- C2 allows the circuit to hold the
detection circuit to a BTL-Class short clipping pulses for a longer
D-amplifier IC. The voltage time. You can add LED circuitry
swing on each output is sym- to provide a visual clipping indi-
metrical and is within the range cation.EDN
of voltage drop on the on-re-
sistance of MOSFET Q6 to the R e fe r e nce
common-collector voltage, VCC, 1 Person, Andrew P, and James

minus the voltage drop on the P Muccioli, “Adjustable Clip

Figure 2 A positive-going pulse appears on the
on-resistance of MOSFET Q3. Detec­tion System,” US Patent,
collector of Q1 whenever the output voltage
When the output voltage reach- 5,453,716, Sept 26, 1995, US
is below the threshold with respect to power
es a certain threshold, Q1 turns Patent Office, http://patft.uspto.
ground.
off. The component values of R1, gov.

52 EDN | march 5, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Buck converter uses low-side PWM IC

D Is Inside
L Haachitaba Mweene, PhD, National Semiconductor Corp, Richardson, TX


The most common switching-
power topology is a buck con-
verter, which efficiently transforms
high voltages to low voltages. Figure
1 shows a typical buck converter in
which the N-channel MOSFET, Q1,
needs a floating-gate drive signal. The not have to tolerate high voltages, you
floating-gate drive is part of the PWM
(pulse-width-modulation) controller
IC. Q1 can be either N or P channel,
depending on the controller’s design.
Unfortunately, the IC’s voltage rating
must be as high as the input voltage,
which places a limit on the maximum
voltage it can process.
Q1
�
L1
VIN VGATE
D1
PWM CONTROLLER
� �
Figure 1 A basic buck converter uses a PWM con-
troller and a MOSFET.
� �
edn081113di43821 DIANE
VCC
PWM CONTROLLER
VIN
VGATE
� �
Figure 2 A level-shifting circuit provides low-side control of a buck converter’s high-
side FET.
The circuit in Figure 2 uses a simple
voltage-level shifter that lets a buck
converter control a pass transistor with
a low-side IC that has a ground-refer-
enced gate drive. Because the level-
shifting circuit in the PWM IC does
can implement a converter with an
arbitrarily high input voltage.
PWM ICs with low-side gate drivers
can power N-channel MOSFETs that
are on when they have a positive gate-
to-source voltage. The circuit in Figure
2 uses a P-channel device as the high-
side MOSFET; it’s on when its gate-to-
source voltage is nega-
tive. Therefore, you
� must invert the control
signal from the PWM
controller. A MOSFET
VOUT
C1 totem-pole configura-
tion comprising Q2 and
Q3 will work, although
you can also use an in-
verting-gate driver.
Capacitor C 2 per-
forms the level-shift-
Q1
L1
D2 R1
12V 5.11k
Q3
C2 D1 C1
PFET
Q2
NFET
53 Isolated clock source acts as
test generator
54 Class AB inverting amp uses
two floating-amplifier cells
56 DPGA conditions signals with
negative time constant
58 Instrumentation amplifier
compensates system offset
from single supply
ETo see all of EDN's Design
Ideas, visit www.edn.com/design
ideas.
ing. It must have a value large enough
to maintain its charge at the switch-
ing frequency but small enough for
its voltage to follow variations in the
input voltage. Resistor R1 and P-chan-
nel MOSFET Q3 charge C2 to a volt-
age of VC5VIN2VCC, where VC is C2’s
voltage, VIN is the input voltage, and
VCC is the supply voltage of the Q2 and
Q3 totem-pole configuration and the
PWM IC. The supply voltage must be
less than zener diode D2’s break-
down voltage. Otherwise, cur-
rent will flow through D2 and C2
whenever Q2 is on, which lowers
efficiency. D2 limits C2’s voltage
to the value in the above equa-
VOUT tion. When Q3 is on, D2 becomes
forward-biased if the voltage at-
tempts to increase. This circuit
applies a 0V voltage between
Q1’s gate and source when Q3 is
on, and it applies 1VCC when
Q2 is on.
Resistor R1 also ensures that
Q 1
’s gate-to-source capacitance
discharges, which keeps Q1 off
when the totem pole’s output

edn081113di43822 DIANE

march 19, 2009 | EDN 51

designideas
voltage is high. Diode D2 tor R4 and an internal 2-kV
limits Q1’s gate-to-source resistor to generate a ramp
voltage to 12V regard- with a peak-to-peak voltage
less of the circuit’s input of 50 mA3(2 kV15.11
voltage. Capacitor C2 is kV)Q300 mV at the CS
transparent to Q1’s gate- pin, Pin 8. The COMP pin,
drive pulse, so the circuit’s Pin 3, compares this saw-
gate-driving capability is tooth to the output error
just as good as that of the voltage at the COMP pin,
totem-pole circuit itself. which generates the right
The level shifting, there- duty-ratio signal for Q1.
fore, imposes no limita- Figure 4 shows the cir-
tion on the size of the cuit’s switching waveforms.
MOSFET that the circuit Oscilloscope channel 1
can drive. (bottom trace) shows the
Figure 3 shows a prac- gate-drive signal that the
tical buck converter em- LM5020-1 generates. Chan-
ploying this scheme. The Figure 4 Voltage waveforms in the buck-converter circuit of nel 2 (middle trace) shows
converter’s input voltage Figure 3 show clean voltages with short rise and fall times. the corresponding totem-
is 18 to 45V, and its output pole output voltage. Chan-
voltage is 12V at a 1.5A output current. ability in 12.7-kV R3 for 500 kHz; feed- nel 3 (top trace) shows the level-shift-
The converter uses National Semicon- back compensation in C7, C8, and R6; ed totem-pole output voltage between
ductor’s (www.national.com) LM5020- and output-voltage setting in R9 and the source and the gate of Q1. The
1 flyback/boost/forward/SEPIC (single- R10. peak value of Q1’s gate-to-source volt-
ended-primary-inductance-converter) The LM5020-1 provides current- age equals the input voltage, and its
PWM-controller IC. mode control, but, in this circuit, it amplitude is about 8V, the value of the
The figure retains the component implements voltage-mode control. supply signal that the LM5020-1 inter-
designators from the previous figures An internal sawtooth-current source nally generates. All the waveforms are
but adds functions such as input-volt- with a peak value of 50 mA, which clean and have short rise and fall times.
age filtering in C9; input-undervoltage adds slope compensation to a current The full-load efficiency of the circuit is
lockout in R2 and R7; soft-start capabil- signal, serves as a voltage ramp. This 86 and 83% at input voltages of 18 and
ity in C3; switching-frequency-setting current flows through 5.11-kV resis- 45V, respectively.EDN

IRFR9014
P2 Q1 P3
L1
VIN R5 12V AT 1.5A
D2 R1 15 �H
18 TO 45V 10k 12V 5.11k
C9 � R9
470 �F R7 13.3k
C5
63V 133k 0.1 �F
C7
10 OPEN
SS IC1 VIN 1
LM5020-1 2 C8
9 R6
RT VFB 47 nF
10k
8 3
CS COMP
7 VCC 4
UVLO
C6 C2
6 5
GND OUT 1 �F 0.1 �F

Q3 � C1
D1 330 �F
MBRS3100 16V
MMBF2202

R10
R2 C3 R3 C4 R4
Q2 1k
11.8k 100 pF 12.7k 1 nF 5.11k

MMBF2201
P4 P5

GND fS=500 kHz. GND

Figure 3 An alternative buck converter uses a low-side PWM IC to control MOSFET Q1.

52 EDN | march 19, 2009

edn081113di43823 DIANE
 HCLP-7101 type that operates at fre-
Isolated clock source quencies as high as 40 MHz, but new

acts as test generator devices, such as the HCPL-77xx in

SMD packages, are fully compatible.
Daniele Danieli, Eurocom-Pro, Venice, Italy These optocouplers have input-to-out-
put capacitance of less than 1 pF, and


Circuits such as PLL synthe-
sizers, high-dynamic-range
ADCs, and timing-sensitive digital
networks require stable and spurious-
free clocks. Testing these circuits is a
difficult task when you use a master
oscillator, even if the signal theoreti-
cally matches the application’s phase
noise and spurious responses. Variable
clock-line loads, typical conditions in
circuits under functional evaluation,
and power-supply-line interferences,
again typical in open-board environ-
ments on lab desktops, can degrade
signal purity with jitter or unpredict-
able phase steps.
You can insulate an oscillator from
a load requiring a special high reverse-
attenuation-buffer stage, but it is more
difficult to implement this insulation
at frequencies of 10 MHz and more.
This Design Idea describes a cost-effec-
tive approach to implementing an iso-
lated clock source using a high-speed
optocoupler with low input-to-output
capacitance.
The circuit uses a quartz-oscillator
stage with two NPN transistors in a
conventional scheme (Figure 1). You
select components C3 and C4 relative
to the frequency; for 15- to 30-MHz
frequencies, the corresponding values
are 220 and 100 pF, respectively. You
can scale up these values for lower fre-
quencies. You can also substitute this
stage with other equivalent circuits.
A level-shift follower uses PNP tran-
sistor Q3; a TTL-compatible signal at
the output is available. You select re-
sistor R7 for the best pulse response; a
value of 22V is adequate for most ap-
plications; however, you can omit the
resistor if necessary.
You now apply a logic-level signal to
the input pin of a high-speed CMOS
optocoupler, IC2. This design uses an
they have separate supply pins. If you
do not use common grounds, as in the
figure, you establish an optimized ul-
tralow-power coupling, which provides
effective isolation from load conditions
and EMI (electromagnetic interfer-
ence) that otherwise might modulate
the incoming signal.
Note that the left side of the cir-
cuit, comprising an oscillator and the
input half of the optocoupler, uses a
dedicated battery to obtain the 5V
supply voltage. On the right side,
comprising the output half of the op-
tocoupler, all lines directly connect
to the board under test with relative-
ly long cables; thus, they cause no
disadvantages in the oscillator stage.
You can use any optocoupler of ad-
equate bandwidth as long as you pay
attention to the correct power-supply
voltage and the logic-level compat-
ibility of IC2.EDN

IC1
E 78L05 U
M � C7
�
9V C6 100 �F
100 nF

C8 R8
C2 C5 100 nF 4.7
R1
100 nF 100 nF
56k R5
220
2N2369
Q1
Q3 1 IC2
2N2369 8 VCC
C3 R7 5V
C1 Q2 2N4423 2 7
C10
33 pF
22 nF
R2 C9 6
R3 CLOCK
100k 22 nF 4
2200 5
R6
3- TO 30-MHz
100
CRYSTAL HIGH-SPEED
OSCILLATOR C4 R4 OPTOCOUPLER
560

TTL-LEVEL SHIFT BOARD UNDER TEST

Figure 1 This circuit provides a cost-effective approach to implementing an isolated clock source using a high-speed opto-
coupler with low input-to-output capacitance.

march 19, 2009 | EDN 53

edn081113di43721 DIANE
designideas

Class AB
600V
POSITIVE AMPLIFIER CELL

inverting amp R6
100k
2W

uses two floating-

Q1

R7 R10 STW8N80

amplifier cells 15V

2 8
100k
2W
100
1W

Joseph Wee Ting, Institute of D1

6.2V
Atomic and Molecular Sciences,
NC
Sinica Academy, Taipei, Taiwan 7
Q2


6
STW8N80
Transistors often find use as C1
4.7 pF
R11
3
three-pin amplifier devices, in 100
1W
which the input and the output share IC2
5
R2 R4 6N136
one pin. Thus, the input and the out- 600k 2k VOUT
put must have the same voltage at this 1W

pin. On the other hand, a four-pin am- R3 C2

plifier could isolate the circuit’s input 330k 2000 pF

and output. Using optoisolators, you

can design a four-pin Class AB ampli- R1 15V R8
100k
VIN
fier. Although the output voltage of an 10k
1
�
7 2W Q3
optoisolator curtails its usefulness, you 3
IC1 6
�
can add discrete transistors to form an 4
LM7171
R5
R9 R12 STW8N80
100k
isolated amplifier. �15V
2k 2W
100
1W
Figure 1 shows an example of a 2 8

simple, 1-kV-p-p Class AB inverting D2

6.2V
amplifier that uses two identical float- NC
ing-amplifier cells. The frequency re- 7
Q4

sponse is dc to 20 kHz at full gain. You 6

STW8N80
R13
can achieve higher frequencies but at 3 100
lower gains. The ratio of resistors R2 �15V
IC3
1W

and R1 sets the gain. This circuit elimi- 6N136 5

nates the need for many voltage-shift-
ing components, which are typical of
a standard circuit design. The positive
and the negative cells are driven out
of phase. The 15V and 215V and re-
NEGATIVE AMPLIFIER CELL
�600V
Figure 1 Transistors boost the output voltage and current of optoisolators, mak-
ing an isolated amplifier output.

edn081030di43601 DIANE

Figure 2 The amplifier’s square-wave response at 10 Figure 3 The amplifier’s sine-wave response at 20 kHz
kHz shows some high-frequency cutoff. shows a clean output signal.

54 EDN | march 19, 2009

designideas
sistors R4 and R5 provide the neces-
sary bias to guarantee that the out-
put transistors are always on. Careful
trimming of R4 and R5 can remove the
output crossover distortion. Zener di-
odes D1 and D2 keep the optoisola-
tor photodiodes back-biased at 6.2V.
Resistors R10, R11, R12, and R13 supply
some negative feedback to the output
transistors. You must mount the four
STW8N80 N-channel MOSFETs on
suitable heat sinks to keep them cool.
The circuit requires no active short-
circuit protection. One pair of 125-
mA currents across the high-voltage
supply lines is sufficient to safeguard
the circuit from destruction.
Figure 2 shows the square response
at 10 kHz. There are no overshoots or
undershoots, and the rising edge is al-
most antisymmetric with respect to the
trailing edge. Figure 3 shows the sine-
wave response at 20 kHz. Both outputs
are 1 kV p-p.EDN

DPGA conditions signals 

DPGAs (digitally programmable-
gain amplifiers) amplify or atten-
with negative time constant uate analog signals, which maximizes
an ADC’s dynamic range. Most mono-
W Stephen Woodward, Chapel Hill, NC lithic DPGAs, such as the Linear Tech-
nology (www.linear.com) LTC6910 and
the National Semiconductor (www.
national.com) LPM8100, use a multi-
plying DAC in an op amp’s feedback
loop so that the DAC’s input code sets
the amplifier’s closed-loop gain. In-
stead of using a monolithic DPGA, you
can use two op amps and three analog
switches to build a DPGA employing
negative time constants.
You’re no doubt familiar with the e2t/RC
convergent exponential in which a
capacitor in an RC circuit asymptoti-
cally discharges to zero. For input volt-
Figure 1 A negative time constant causes voltage to increase exponentially age, V5VIN/2 at t5T5loge(2)RC,
over time. V5VIN/4 at t52T, V5VIN/8 at t53T,
and so forth. Less fa-
R1 miliar, but just as sim-
7.21k
ple, is the behavior of
GAIN-PROGRAMMING PWM MICRO-
I1 CONTROLLER the same RC topol-
S1 11
3 A T=7.21 �SEC ogy when you replace
69 �SEC=1/14.5 kHz
X1
4 3
R with an active cir-
5 �
VIN
X0
X A1 1
PWM
cuit that synthesizes
R4 AD8606
200 1/3 MAX4053
I1 2 � VO=�2VIN a negative resistance
�5 �SEC
C1
�4 �SEC t (Figure 1). If you re-
0.001 �F 1 MAX4053
R2
17.4k
R3
7.21k 2
/3 AMPLIFY place resistor R with
X0
15 13
9 S3 SAMPLE 2R, you create a posi-
X X1 A
I3 1
X1 A tive RC time constant.
I3 I2
X 14 Thus, you create a di-
S2 12 X0
10 I2
NOTE: 1 MAX4053
vergent exponential,
/3
I1=I2=I3. THEREFORE, IF THE ON-RESISTANCES
C2
750 pF
VINe1t/RC.
5
OF R1, R2, AND R3 ARE EQUAL, THEN
ON-RESISTANCE ERRORS CANCEL.
� A
2 7
Instead of converg-
C3
750 pF 6 �
AD8606 ing to zero, the wave-
form theoretically di-
C1 VOUT verges to infinity, and
C3=C2�
�2 V52VIN when t5T,
V54V IN at t52T,
V58VIN at t53T, and
Figure 2 Positive feedback from amplifier A1 causes C1 to increase in voltage, which exponen-
so forth. Therefore,
tially amplifies the input voltage.
you can amplify the in-

edn081030di43682 DIANE

56 EDN | march 19, 2009

designideas
put voltage by simply waiting the right
amount of time (t5log2(V/VIN)T) after
starting the negative discharge. The di-
vergent exponential and the negative
time constant are the core concepts of
the circuit in Figure 2.
You can program the amplifier’s gain
with a PWM (pulse-width-modula-
tion) signal from a microcontroller or
another circuit. When the PWM sig-
nal goes to logic zero, sample-and-hold
capacitor C1 charges to VIN. When the
PWM signal cycles to logic one, op
amp A1 drives the R1C1 positive-feed-
back loop, creating a negative time
constant. The resulting divergent ex-
ponential rise of C1’s charge continues
as long as the PWM signal remains at
logic one. That situation creates a net
voltage gain of:
VOUT(t)5VIN2(t/10 msec10.5).
Instrumentation amplifier
compensates system offset
from single supply
Luca Bruno, ITIS Hensemberger Monza, Lissone, Italy

Many integrated instrumenta-
tion amplifiers have architec-
tures that permit offset compensation.
The reference terminal’s voltage, VREF,
RG
0.1%
R2
46.4k
0.1%
R1
23.2k
R3
0.1% 2
� 46.4k
IC1A 1
0.1%
OPA2333
VA 3 � R5
46.4k
0.1%
VREF
VB
Figure 1 You can build an instrumentation amp operating from a single supply
that permits you to reset the system offset by applying a positive-correction
voltage to the VREF input.
58 EDN | march 19, 2009
lent gain resolution even when a PWM
the near-ubiquity signal has just 8 bits of resolution and
its programmable gain has a range
of programmable- greater than 0.2 dB/LSB step. (To view
timer/counter the log and linear plots of gain versus
hardware makes time using the amplify phase, go to
the Web version of this Design Idea at
it easy to digitally www.edn.com/090319dia.)
generate a HIGHLY The accuracy and repeatability of
the timing of the exponential signal,
repeatable PWM- the ADC sampling, the jitter, and the
control signal. RC-time-constant stability all limit the
amplifier’s gain-programming accuracy.
In Figure 2, 1 nsec of timing error, or
Thus, gain52(t/10 msec10.5) and log(gain)5 jitter, produces 0.007% of gain-pro-
310.6 dB/msec. At the end of the am- gramming error. Fortunately, the near-
plification cycle, when PWM returns ubiquity of programmable-timer/coun-
to logic zero, amplifier A2 captures and ter hardware in microcontrollers and
holds the amplified input voltage. data-acquisition systems usually makes
The logarithmic relationship be- it easy to digitally generate a highly re-
tween gain and timing provides excel- peatable PWM-control signal.EDN
of equal value but of opposite polar-
ity. If the instrumentation amp oper-
ates from a dual-supply voltage, you
can easily provide both positive- and
negative-correction voltage. Howev-
er, some instrumentation amps oper-
ate from a single supply—for example,
in a battery-powered application—to
adds in phase to the output to yield a amplify a signal source or a sensor that
gain of one. As a result, you can reset introduces a positive offset voltage. A
the output offset voltage by applying sensor such as the AD590 from An-
to the VREF input a correction voltage alog Devices (www.analog.com), for
example, produces an output current
R4 proportional to absolute temperature,
46.4k
0.1%
and you should calibrate it at the
lower reference temperature. In this
case, the output swing of the instru-
C1 5V mentation amp decreases, especially
100 nF with high gain. To prevent this effect,
you must apply a negative-correction
voltage, which you generate from the
6 8 positive power supply. In precision
�
IC1B applications, the application of such a
7
OPA2333 VOUT voltage may cause a problem.
5
� This Design Idea shows you how to
4 build an instrumentation amp operat-
GND
ing from a single supply that permits
you to reset the system offset by ap-
plying a positive-correction voltage
to the VREF input. The circuit in Fig-
ure 1 employs the dual high-precision
OPA2333 op amp from Texas Instru-
ments (www.ti.com). This op amp can
 VO =  3 +  ( VB1VA )1VREF .
 RG 
designideas
Equation 2 Equation 3

operate from a 1.8 to 5.5V supply and

uses a proprietary autocalibration tech- V =  3 + 92.8 kΩ  ( V 1V )1V . 2R
3+
O B A REF
nique to simultaneously provide a max-  RG  RG
CMRR = ,
imum offset voltage of 10 mV and near-  ∆R 
6 
zero drift over time and temperature. It The amplifier’s differential gain is  R 
also Equations forEquations
offers high-impedance DI4412 (inputs for− DI
12 5 −that
08 issue
4412 (12 )− 5 − 08 kV/R
31(92.8
Equation issue
3 ) G), and the reference
have a common-mode range 100 mV voltage is added, inverted together where DR/R is the resistor’s tolerance.
beyond the supply rails and rail-to-rail with the output signal. Resistor RG sets If the tolerance is 0.1% and with the
or DI4412 for
Equations (12 −DI − 08 issue
54412
output (12 −)swings
that 5 − 08within
issue) 50 mV of the the gain, and, if you do not connect R , minimum differential gain, which is
2R G
rails.Equation
Applying1theEquation superposition 1 of the the gain assumes 3+ the minimum value, three, you obtain a CMRR of at least
RG
effects to the circuit in Figure 1 yields which CMRRis=three; decreasing , the value of 54 dB. With a differential gain of 100,
the following equation: RG to 93V6increases  ∆R  the gain to 1000. you obtain a CMRR of at least 84 dB.
 R 
Equation 1  The V  input  requires a low-im- The VREF input can reduce the sys-
R 4    RR44  R 2   R 4REF   R2 
VO = VB  1 +VO = VB  1 + +  pedance
   +  1 connection
  1 to preserve a tem offset to the lower output-swing
 R 3 R 5 RG  R3 RR35 RR
 good R3   RG
GG  CMRR  
(common-mode-rejec- limit but does not reset it completely
R            
 R   R  R 4   R 2 4 R 2 4  R 4   R 4 4
R R    tion  R ratio);
  otherwise,
 R 4  you can use because, in that case, the output volt-
1V+O = VB4 1 +  +  V4A 1 +2+12V A  1 + 1 +    1VREF +  op-amp
an 1 . Vbuffer
REF  for . better CMRR, age would be unable to reach the sin-

R 3 R 5R G R 3 R R53 RGRG R  
 1RR3 G RGR 3R 1 RRGG  R 3  which
 RR 
G5depends  R 5  on resistor-ratio
mainly gle-supply ground. If you want instead
R 2   R 4 R 2 R4 R4   R4R4  R  matching. In this implementation, to to reset the output offset, you can sub-
VA 1 +  +     1V+REF
     1  .VREF  4  . preserve an acceptable CMRR, you tract this value using an ADC with dif-
R G  R 3R1 RGRG R3   RGR5   R5 
  must use precision film resistors. An- ferential inputs (Reference 1).EDN
ToEquation
achieve 2equal gain for
Equation 2 both the alyzing the circuit, you can calculate
VB and the VA inputs, resistors R2, R3, the worst-case CMRR at low frequen- R e fe r e nce
R4, and R5 must have equal values that cy. With R2, R3, R4, and R5 all of equal 1 Bruno, Luca, “Circuit compensates
Equation 2 are double the9value 2.8 kΩof R1. 9Using the value and double that of R1 and with
2.8 kΩ 
system offset of a load-cell-based
resistor =  3 + in V
VO values O =  (31,
Figure V+Byou 1VA )1V (REF
obtain VB1 A )1
.allVthe VREF . having equal tolerance,
resistors balance,” EDN, Aug 16, 2007, pg 71,
 simplifiedR G  RG 
the following equation: you obtain: www.edn.com/article/CA6466208.
2.8 kΩ  92.8 kΩ 
VO =  3(+VB1VA )1V
( VREF
B1 . VA )1VREF .
RG   R G Equation 3
Equation 3

Equation 3 2R 2R
3+ 3+
RG RG
CMRR = CMRR , = ,
 ∆R   ∆R 
2R 2R 6  6 
+ 3+  R   R 
RG RG
CMRR , = ,
 ∆R   ∆R 
 R  6 
   R 

60 EDN | march 19, 2009

 designideas
Twin-T power oscillators work
as dc-biased ac sources
Tiger Zhou and Robert Dobkin, Linear Technology, Milpitas, CA

AC test equipment often needs
a low-distortion signal source to
excite the device under test. The com-
mon practice is to use a signal genera-
tor to produce a low-distortion refer-
ence, which you feed to a power ampli-
fier to drive the device under test. This
Design Idea suggests a less cumbersome
alternative.
Figure 1 shows an oscillator that
generates a low-distortion sinusoidal
signal with power-driving capability.
The power oscillator consists of two
major parts: a twin-T network and a
high-power low-dropout regulator. The
twin-T network has two T-type filters
in parallel: one lowpass filter and one
highpass filter. The twin-T network is
IN
LT3080
VCONTROL
OUT
SET
1 �F C
R
RSET R/K
K�C
R C
Figure 1 This oscillator generates a low-distortion sinu-
soidal signal with power-driving ability.
edn081127di43891 DIANE
(in 12-15 folder)
54 EDN | april 9, 2009
readerS SOLVE DESIGN PROBLEMS
highly frequency-selective as a notch
filter. The low-dropout regulator am-
plifies the signal and drives the load.
The regulator in this circuit incorpo-
rates a current-reference voltage-fol-
lower architecture. It is unity gain from
the Set to the Out pins, and the cur-
rent reference is a precision 10-mA cur-
rent source. The RSET resistor on the
Set pin programs the output-dc level.
By connecting a twin-T network be-
tween the Out and the Set pins, the
resulting notch filter attenuates both
high- and low-frequency content, al-
lowing the center frequency to freely
pass through. The resistors and capaci-
tors program the center frequency, f0:
f051/(2pRC).
VOUT
200 4.7 �F 10
2k
Figure 2 The twin-T network’s gain changes with the value
of K from Figure 1.
Edited By Martin Rowe
and Fran Granville
D Is Inside
56 Diagnose LEDs by monitor-
ing the switch-mode duty cycle
60 Single pin controls relay,
intermittent buzzer, and
status LED
62 Simple two-transistor circuit
lights LEDs
ETo see all of EDN's Design
Ideas, visit www.edn.com/
designideas.
Small-signal analysis of the twin-
T network indicates that the gain is
maximum at the center frequency. The
twin-T oscillator’s maximum gain in-
creases from one to 1.1 when the K
factor increases from two to five (Fig-
 ure 2). The maximum gain decreases
IN when the K factor is larger than five.
LT3080 Therefore, select a K factor of three
VCONTROL
to five for a gain larger than unity
gain. The loop gain must be unity to
maintain a steady oscillation. Thus,
you need a potentiometer to tune the
� loop gain to control the oscillation
amplitude.
�
The twin-T oscillator can drive in-
VOUT
OUT ductive, capacitive, or resistive loads.
SET
The low-dropout regulator’s current
6.3V, limit, which is 1.1A for the Linear
150-mA
10 �F 47 nF
LIGHT BULB
Technology (www.linear.com) LT3080,
8.45k 10 is the only limit on the oscillator’s drive
4.7 �F
2.21k capability. The load characteristics limit
499k
the maximum programmable frequency.
For example, a 10V resistive load with
220 nF
121 a 4.7-mF output capacitor causes a 7%
8.45k
47 nF THD (total harmonic distortion) at a
frequency higher than 8 kHz, although
THD is 0.1% at 400 Hz in the circuit
of Figure 3. The twin-T oscillator has
the same performance in line and load
regulation as the LT3080. It also works
Figure 3 To automatically control the gain, you can replace the potentiometer
in a wide temperature range.
with a light bulb.
To automatically tune the gain, you
edn081127di43893 DIANE can replace the potentiometer with a
(in 12-15 folder) light bulb (Figure 3) or a voltage-mod-
ulated resistive MOSFET (Figure 4).
IN
LT3080
The light bulb’s resistance increases
VCONTROL with the oscillation amplitude due to a
self-heating effect, so it servos the loop
gain to maintain the oscillation. In
Figure 4, by detecting the peak voltage
� using a zener diode, the MOSFET re-
sistance decreases when the oscillation
� amplitude is high. The loop gain also
VOUT decreases to maintain the oscillation.
OUT
SET Figure 5 shows the test waveform of
100 the twin-T oscillator using a light bulb.
100k The output is tuned to a 4V-p-p volt-
age with 5V-dc bias voltage (Figure 6).
1 �F 47 nF 3.1V The twin-T oscillator has a 400-Hz fre-
10 �F quency and 0.1% THD. The most sig-
8.45k 4.7 �F
2.21k 20k
10 nificant harmonic contribution is from
499k the second harmonic at less than 4
VN2222LL mV p-p. Figure 6 shows the test wave-
220 nF form of the twin-T oscillator using the
8.45k 200 MOSFET. The THD is 1% with a 40-
47 nF
10 �F 20k mV-p-p second harmonic.
Start-up is another important as-
pect of the oscillator. Both circuits ex-
hibit no low-frequency swing, which
is common to other types of oscilla-
Figure 4 You can automatically control the gain by replacing the potentiometer
tors. The waveforms in figures 7 and
with a variable-resistance MOSFET.
8 exhibit little overshoot. The oscilla-
edn081127di43894 DIANE
(in 12-15 folder)

april 9, 2009 | EDN 55

designideas

Figure 5 The test waveform for the oscillator in Figure 3 Figure 6 The test waveform for the oscillator in Figure 4
shows low distortion at a THD of 0.1%. shows low distortion with a THD of 1%.

Figure 7 The waveform for the circuit in Figure 3 shows a Figure 8 The waveform for the circuit in Figure 4 shows a
slow start-up of the light-bulb oscillator. quick start-up of the MOSFET oscillator.

tor using the MOSFET stabilizes faster can use the simple circuit as a dc-bi- Ack n owle d g m e nt
than the one using the light bulb be- ased ac source in applications requir- The authors wish to thank Tony Bonte,
cause the light bulb has a long thermal ing low distortion and power-driving Mitchell Lee, Jim Williams, and Todd
constant due to the heating effect. You capability.EDN Owen for fruitful discussions.

Diagnose LEDs by monitoring the switch-mode duty cycle

Fons Janssen, Maxim Integrated Products Inc, Bilthoven, the Netherlands


Engineers often monitor the forward voltage, VF,
of HB LEDs (high-brightness light-emitting di- LEDs
odes) to assess the LEDs’ health. Big changes in forward RSENSE L
voltage can indicate deterioration or even a complete VIN
failure of one or more LEDs connected in series. For
CIN
several LEDs in series, the sum of their forward voltages
D1
can reach 40V or more, and, if you do not reference
that voltage to ground, it requires a differential mea- 1 6
VIN VCC
surement. In addition to the challenges of high volt-
MAX16820
age and differential measurement, HB LEDs are often
dimmed using PWM (pulse-width modulation). If so, 2
CS� DRV
5
you can’t measure forward voltage during the low por- PWM
DIMMING
tion of the PWM duty cycle when the LEDs are unlit 3 4
DIM GND
and the forward voltage is not present. For a hysteretic
buck-LED driver driving three LEDs in series (Figure
1), you must measure the anode and cathode voltages
of the string when the Dim pin is high.
To avoid the need for a differential high-voltage mea- Figure 1 For a hysteretic buck-LED driver driving three LEDs
surement, you can take the indirect approach of mea- in series, you must measure the anode and cathode voltages
suring the duty cycle at the driver pin, DRV. For this of the string when the Dim pin is high.
LED driver, a first-order estimate of forward voltage for

edn081127di44031 DIANE
(IN 12-15 FOLDER)

56 EDN | april 9, 2009

designideas
LEDs
the LED string is VF5D3VIN, where RSENSE L
D is an internal duty cycle that the VIN
IC’s switch-mode section produces; do CIN
not confuse this duty cycle with that D1
at the Dim pin. You reference the driv- 1 6
VIN VCC
er signal to ground and limit it to the
MAX16820
power-supply voltage, VCC, at 5V. That
2 5
condition allows the use of low-voltage PWM
CS� DRV

ADCs or comparators, which the LED DIMMING

3 4
driver’s VCC output, a maximum of 10 DIM GND

mA, can power. R1 VD

�
Figure 2 shows how to detect a MAX9141 LED SHORT
short-circuited LED with the aid of a C1
REF �
LE
comparator. Filter R1C1 converts the ac D2
PWM signal at the driver to a dc volt-
age, VD, proportional to D3VCC. You
should sample VD when its value is R2 C2

greater than perhaps 90% of its steady-

state value; this sampling requires a
period of at least 2.3R1C1. Because the Figure 2 Adding this comparator circuit to the Figure 1 circuit provides detec-
comparator’s LE (latch enable) latches tion of shorted LEDs.
the output when LE is low, LE should
assert not earlier than 2.3R1C1 after shorted, its forward voltage drops and
edn081127di44032 DIANE
(IN 12-15 FOLDER)
per LED (Figure 3a), the filtered driv-
the Dim pin goes high. R2, C2, and D2 causes the duty cycle at the driver to er signal (green) stabilizes at approxi-
ensure that LE deasserts immediately drop. VD then drops below the refer- mately D3VCC5(9V/12V)5V53.75V.
after the Dim pin goes low. The value ence, causing the comparator’s output The comparator latches when the fil-
of R2C2 is higher than that of R1C1, to go high, indicating a shorted LED. tered Dim signal (yellow) goes lower
so the comparator enables when the Because the output latches when the than 2.5V, so the comparator begins
input signal reaches at least 90% of its Dim pin goes low, the error signal re- interpreting the filtered driver signal
steady-state value. D2 immediately dis- mains asserted even when the LEDs are after approximately 100 msec. Clearly,
charges C2 after the Dim pin goes low, off. Figure 3 shows the filtered Dim pin VD is higher than the threshold-refer-
which latches the output as soon as the and driver signals for normal operation ence voltage (red) when the compar-
LEDs turn off. versus a shorted-LED condition. ator is active. After one of the LEDs
Because the reference voltage is For a system with an input voltage of shorts out (Figure 3b), VD stabilizes at
lower than D3VIN, the comparator 12V and three LEDs in series, in which approximately (6V/12V)5V52.5V and
output is normally low. If an LED fails the forward voltage is approximately 3V no longer exceeds the threshold. That
condition causes the comparator’s out-
put to go high, indicating that one of
the LEDs has become a short circuit.
The choice of filter constants R1C1
and R2C2 depends on several param-
eters. The cutoff frequency should be
low enough to properly filter the driver
signal yet small enough to allow the fil-
tered signal to stabilize near the steady-
state value achievable within the
(a) (b)
shortest dimming pulse. You can easily
Figure 3 For a system with an input voltage of 12V and three LEDs in series, adjust this circuit to detect open-cir-
in which the forward voltage is approximately 3V per LED (a), the filtered driver cuit LEDs. When an LED breaks and
signal (green) stabilizes at approximately D3VCC5(9V/12V)5V53.75V. The com- stops conducting current, the driver’s
parator latches when the filtered Dim signal (yellow) goes lower than 2.5V, so the duty cycle goes to 100% when the Dim
comparator begins interpreting the filtered driver signal after approximately 100 pin is high. If you then swap the com-
msec. Clearly, VD is higher than the threshold reference voltage (red) when the parator-input connections and put the
comparator is active. After one of the LEDs shorts out (b), VD stabilizes at approxi- reference voltage slightly below VCC,
mately (6V/12V)5V52.5V and no longer exceeds the threshold. the comparator output goes high in re-
sponse to an open LED.EDN

april 9, 2009 | EDN 59

designideas
Single pin controls relay, sign Idea discusses a circuit that con-
trols a device through a relay and an
intermittent buzzer, and status LED intermittent buzzer with only one digi-
tal-I/O pin.
Kartik Joshi and Manik Chugh, Pin PA1 of the digital device controls
Netaji Subhas Institute of Technology, Delhi, India a relay, which switches an appliance on


Switching applications involv- could be in the form of a buzzer that and off (Figure 1). NPN transistor Q3
ing controlling devices or appli- turns on for a few seconds every time activates the relay coil when the I/O
ances using digital-I/O lines through a the line changes state. Designers gen- line is in the high state. Status LED D1
relay often need to indicate the change erally employ an additional I/O pin to connects in parallel to the relay coil
of state of the I/O line and, hence, the trigger the buzzer whenever the state of and turns on when the I/O line is high
connected device. This indication the primary I/O line changes. This De- and off when the line is low.
The buzzer remains on for a small
12V amount of time when the relay chang-
es state. You accomplish this task by
employing a push-pull-inverter topolo-
D1
K1 gy using complementary BJTs (bipolar-
D2 junction transistors) NPN Q1 and PNP
IN4001
R9 Q2. The output of this stage connects
1.5k to a bridge rectifier with a buzzer as a
R7 load because buzzers usually are unidi-
1.5k rectional. The bridge rectifier connects
PA1 Q3
in series both with resistor R12 to regu-
2N2222
R10
MVCC late the maximum current through the
1.5k buzzer and with capacitor C1 to ensure
that the buzzer “fades off.” When the
Q2
BC558A
line is low, transistor Q2 is on, the ca-
BUZZER pacitor charges to a positive voltage,
R11 B1
1.5k and the buzzer operates until the cur-
rent through it is sufficient. When the
Q1 line goes high, transistor Q1 switches
BC547A on, the capacitor discharges to ap-
R12
47 proximately 0V, and the buzzer oper-
�
C6 ates again for a short duration. The
1000 �F on-time of the buzzer depends on the
values of REQ, the series combination
Figure 1 This circuit controls a device through a relay and an intermittent buzzer of R12 and the buzzer resistance, and
with only one digital-I/O pin. C6. To change the time constant and
hence the on-time of the buzzer, you
should change the value of the capaci-
tor rather than that of the resistor. You
can also design this circuit using only
one BJT instead of two, but the tran-
sistor would always draw some current
edn081030di43371 DIANE at steady state.
This topology is useful when no
separate I/O lines are available for
controlling the buzzer. You can also
employ this topology to indicate the
change of state of any input stage di-
rectly by connecting it to the given
circuit or through a buffer. Figure 2
shows a Spice simulation of the buzzer
circuit. This simulation replaces the
Figure 2 A Spice simulation of the buzzer circuit replaces the buzzer with 50V buzzer with 50V resistance and plots
resistance and plots the current through the buzzer and the status of the I/O the current through the buzzer along
line. with the status of the I/O line.EDN

60 EDN | APRIL 9, 2009

designideas
Simple two-transistor circuit
lights LEDs
Barry A Tigner, Michigan State University, East Lansing, MI

A previous Design Idea de-
scribes a circuit that uses an
astable multivibrator to drive an
LED (Reference 1). The circuit in
Figure 1 uses a simpler alternative
approach. The circuit uses a 2N3904
NPN transistor and a 2N3906 PNP
transistor, which operate as a high-
gain amplifier.
The 1-MV resistor supplies bias
current. The 1-kV resistor helps
linearize the oscillator waveform
into one that is close to a square
wave with about a 50-to-50 duty
cycle. The capacitor supplies posi-
tive feedback from the output of the
amplifier to the noninverting input.
The frequency of oscillation de-
pends mostly on the RC constant of
62 EDN | APRIL 9, 2009
the feedback capacitor and the input-
stage impedance. The circuit oscillates
at 91 kHz with a 48% duty cycle. You
can use almost any common NPN or
PNP transistors, as long as they have
moderate forward-current gain of 50 or
more and can handle 100-mA col-
lector currents.
The LED connects across the out-
R2
1k
put transistor because this approach
lets the inductive kickback voltage
2N3906 L1 add to the battery-supply voltage
180 �H
Q1
and makes the LED brighter. This
C1 circuit operates well from approxi-
47 pF
B1 � mately 0.8 to 1.6V, which is the use-
1.5V AA ful range of an alkaline battery. The
�
LED-light output decreases as the
R1 Q2
1M
LED1 supply voltage decreases from 1.6 to
2N3904 0.8V.EDN
R e fe r e nce
1 Bruno, Luca, “Astable multivibra-
Figure 1 This two-transistor circuit oper- tor lights LED from a single cell,”
ates as a high-gain amplifier to light LEDs. EDN, Aug 21, 2008, pg 53, www.
edn.com/article/CA6586223.
edn081215di44101 DIANE
PLACED IN THE 2-1 FOLDER
designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Simple method uses PSpice

for Thevenin-equivalent circuits D Is Inside
David Karpaty, Analog Devices Inc, Wilmington, MA 48 DAC and flip-flops form


Thevenin- and Norton-equiv-
alent circuits, among the most
fundamental circuit-analysis theorems,
can be useful for determining a load re-
sistance for maximum power transfer,
simplifying circuit models, and a variety
of other analysis techniques. Unfortu-
nately, calculating the Thevenin volt-
age and resistance can become difficult
as circuit complexity increases. Figures
1, 2, and 3 illustrate a simple method
for obtaining the Thevenin voltage
and resistance—and, subsequently, the
Norton equivalence—with the aid of
simulation. First, you choose an arbi-
trary load resistance, RLOAD—2 kV in
this example—and run the simulation
to get the current through the load re-
sistance. Next, you remove the load re-
sistance and simulate the open-circuit
voltage across nodes A and B to obtain
the Thevenin voltage. You obtain the
Thevenin resistance from those two
values.
The Thevenin-equivalent circuit
R1 R3 R8
2k 3.5k 8k
constant-current source
must produce the same current through
the load. The total resistance in the 52 Convert negative inputs
Thevenin circuit is RTOTAL5(V TH/ to positive outputs
ILOAD)5(374.095 mV/60.301 mA)Q ETo see all of EDN's Design
6.203 kV, where RTOTAL is the total re- Ideas, visit www.edn.com/design
sistance. Therefore, the Thevenin resis- ideas.
tance is simply [(VTH/ILOAD)2RLOAD]5
(RTOTAL2RLOAD)56.203 kV22 kVQ
4.203 kV, where VTH is the Thevenin
voltage and ILOAD is the load current. Without the aid of simulation, you
Figure 4 shows
Equation the Thevenin-
for di4349 (12-5-08 issue)can calculate VTHEVENIN and RTHEVENIN
equivalent circuit, and Figure 5 shows as follows. The array for the loop cur-
the Norton-equivalent circuit. Note rents in Figure 2, assuming a clock-
that, because the net current through wise current flow in each loop, gives
Equation 1
the load flows to the left, the posi- the current through the load resis-
tive Thevenin terminal is grounded. tance (Equation 1).
+(6k)I1 (2k)I2 (0)I 3 (2k)I 4 (0)I 5 (0)I6   1V 
(2k)I +(9.5k)I (2k)I
 1 2 3 (0)I 4 (2k)I 5 (0)I6   0 V 
 (0)I1 (2k)I2 +(15k)I 3 (0)I 4 (0)I 5 (3)I6   0 V  (1)
  .
  (2k ) I1  (0)I 2  (0)I 3 +(4k)I 4 (2k)I 5 (0)I6   5V 
 (0)I (2k)I2 (0)I 3 (2k)I 4 +(14k)I 5 (2k)I6  2V 
 1  
 (0)I1 (0)I2 (3k)I 3 (0)I 4 (2k)I 5 +(17k)I6   2V 
R1 R3 R8
2k 3.5k 8k

V1 R2 R5 Equation 2
R12 V1 R2 R5
1V 2k 2k 1V LOOP 1 LOOP 2 LOOP 3 R12
2k 2k 2k
2k
R6 RLOAD R11
R6 RLOAD R11
2k 2k 3k
2k A 2k B 3k
V2 +(6k)I1 (2k)I2 (2k)I 3 PROBE (0)I 4
1
(0)I 5   1V 
(2k)I +(4k)I (0)I 52V2  5V 
V
2V
R14  1 2  (2 k)I 3 (0)I 4
(2k)I1 (2k)I2 LOOP R14
4 5(2k)IR5   2V  .6
2k +(19.5k)I
R7 R10 4 3 R(2k)I
LOOP LOOP
2k
2k 2k  7 10  
V4 R9 R13  (0 )I1 (0)I 2  (2k)I 3 +(15k)I
2k 4  (3k)I 5 
2k 0V 
5V V4
8k 10k  (0)I (0)I2 5V(2k)I 3
 (3k)I8k49 +(14k)I 5   10k
R R
2V13 
 1 
Figure 1 To calculate Thevenin-equivalent
circuits, you first choose a load resistance— Figure 2 The simulation for current through the load resistance yields
2 kV in this circuit. 260.3 mA.

edn081205di43491 DIANE
edn081205di43492 DIANE
APRIL 23, 2009 | EDN 47
designideas
XMM1 RTHEVENIN
4.203k
� � PROBE 1

VTHEVENIN RLOAD
R1 R3 R8 0.374095V 2k
2k 3.5k 8k

Equation for di4349 (12-5-08 issue)

V1 R2 R5
1V LOOP 1 2k 2k LOOP 4 R12
LOOP 3 2k
Equation 1 R6 R11 Figure 4 In the Thevenin-equivalent
2k A B 3k circuit, current flows to the left, so
the VTHEVENIN terminal is grounded.
V2 edn081205di43494 DIANE
+(6k)I1 (2k)I2 (0)I 3 (2k)I 4 2V (0)I 5 (0)I6   1V 
(2k)I +(9.5k)I R14
 1
LOOP 2
2  R7(2k)I 3 (0)I 4 R(2k)I
10 5 (0)I62k  0 V 
LOOP 5

 (0)I1 (2k)I 2k
V4 2 +(15k)I 3  (0)I 4 2k(0)I 5 (3)I6   0 V  PROBE 1
 5V
R9 R13  .
(2k)I1 (0)I2 (0)I 3 +(4k)I
8k 4 (2k)I10k5 (0)I6   5V  INORTON RNORTON RLOAD
 (0)I (2k)I2 (0)I 3 (2k)I 4 +(14k)I 5 (2k)I6  2V  8.9�005A 4.203k 2k
 1  
(0)Isimulation
Figure 3The 1 (0)Ifor
2 the (3k)I 3 (0)I
open-circuit voltage (2k)I
4 yields 5 +(17k)I6   2V 
approximately
2374 mV.

From Equation 1, you can calcu- currents in Figure 3 without the

late I2 and I5: I2Q217.77 mA, and load resistance,
edn081205di43493 as Equation 2 shows.
DIANE
Figure 5 In the Norton-equivalent
I5Q157.47 mA. Thus, I 2I Q60.3 mA, From Equation 2, you can calculate circuit, R NORTON is 4.203 kV.
Equation 2 2 5
assuming a leftward flow through the the following currents: I 1Q807.92
load resistor. mA, I2Q1.744 mA, I3Q179.87 mA, Thus, VA 52V 4 1[(I 2 2I 3 )3R 7 ]Q
edn081205di43495 DIANE
You calculate the array for the loop I 4Q53.64 mA, and I 5Q148.27 µA. 21.8719V, where the net current flows
downward. Further, V B5 [(2V 41
+(6k)I1 (2k)I2 (2k)I 3 (0)I 4 (0)I 5   1V  (I 3 3R 9 ))1((I 3 2I 5 )3R 10 )1V 2 ]Q
(2k)I +(4k)I
 1 2 (2k)I 3 (0)I 4 (0)I 5   5V  21.498V, where the net current in R10
(2) flows downward. Thus, VTHEVENIN5
(2k)I1 (2k)I2 +(19.5k)I 3 (2k)I 4 (2k)I 5  2V  .
   VA2VBQ2374 mV, and you can cal-
 (0)I1 (0)I2 (2k)I 3 +(15k)I 4 (3k)I 5   0V 
culate RTHEVENIN according to the pre-
 (0)I (0)I2 (2k)I 3 (3k)I 4 +(14k)I 5   2V 
 1 vious description.EDN

DAC and flip-flops form rent pin (Pin 19). The AD5422’s in-
ternal shift-register data moves into
constant-current source the data register at every low-to-high
transition of the latch signal (Pin 7).
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia
The device interprets this alternating


The Analog Devices (www.
analog.com) AD5422 16-bit
serial-input DAC lets you program
for a voltage output or a current out-
put. To communicate with the DAC
and produce a variable output, you
need a data SERDES (serializer/dese-
rializer). If your design needs a con-
stant 4-mA output, however, you can
program the device with two flip-
flops and test it with S1, a mechani-
cal pushbutton switch (Figure 1).
The AD5422’s programming uses a
24-bit word in which the upper eight
bits form an address for a control regis-
ter and the lower 16 bits set the DAC’s
output range, slew-rate step, and slew-
rate clock (Table 1, pg 52). Program-
ming a 24-bit 0101 ... 01 pattern into
the AD5422 sets it to the bottom of
the simultaneously selected current
range, 4 to 20 mA at the output-cur-
bit sequence as a control command
during the 23rd time you press and re-
lease the switch after IC1’s power-up.
After that sequence, the SCLK signal
can remain idle (Figure 2).
Flip-flop FF1, configured as a familiar
divide-by-two counter, produces the
desired alternating sequence. Manually
pressing and releasing the pushbutton
switch, you cause the generation of an
SCLK signal. You must use a debounc-

48 EDN | APRIL 23, 2009

designideas
er because the circuit requires a clean
logic signal for SCLK with level tran-
sitions that do not exceed a few 10s of
nanoseconds. FF2 acts as an asynchro-
nous set/reset flip-flop that debounces
the signal from the button.
For the circuit to work properly,
the active low-to-high transition of
the latch signal must occur at least 13
nsec after the low-to-high transition of
SCLK. You can fulfill this requirement
by using the SN74HC74-class flip-flop.
The Q output of FF1 in IC2 connects to
the SDIN input of IC1. The level tran-
sitions at the SDIN input must have
preset and hold times of at least 5 nsec
with respect to low-to-high transitions
of the SCLK signal. You can derive the
supply voltage of 5V for the pull-up re-
sistor at the FAULT output of IC1 (Pin
3) for IC2 from the AD5422’s precision
5V reference. The tiny current surges
due to loads appear at the initializing
state, at clocking in the control word
to IC1, or in a faulty state when the
open-drain FAULT output of IC1 is ac-
tive. Fortunately, either the output cur-
rent (Pin 19) is not yet flowing, or an
overtemperature condition or an ex-
cessive value of the load resistor causes
external damage to the precision of
this current. In either case, the exter-
nal loading of the internal reference

FAULT LOGIC OUTPUT 15V

MSB LSB
D23 D15 D11 D7 D4 D2 D0 100 nF

0 1010 101 0 10 1 0 101 010 10 10 1

IC1
1 AD5422 24
ADDRESS SLEW- SLEW- OUTPUT- AVSS AVDD
RATE RATE RANGE 2 23
NC DVCC �VSENSE NC
CLOCK STEP SELECT
10k
3 22
FAULT �VSENSE NC
NOTE:
LSB ENTERS THE INTERNAL SHIFT REGISTER AS A LAST BIT. 4 21
GND VOUT NC
5 20
Figure 2 Although the control-command sequence CLEAR SELECT BOOST NC
is at least 23 clock pulses wide, you can easily IOUT
6 19
CLEAR IOUT
generate the alternating bit pattern. 18
7 RL
LATCH NC NC
�1200
8 17
SCLK CCOMP NC
9 16
SDIN DVCC SELECT NC
10 15
SDO REFIN
11 14
AGND REFOUT
12 13
GND RSET NC
edn081127di43932 DIANE
(PLACED IN THE 12-15 FOLDER)
5V

14 13 12 11 10 9 8
VDD

D S Q

CLK
Q
IC2 R
SN74HC74 FF1
D S Q 47 nF
470k 470k
S1 CLK
Q
R
FF2
GND

1 2 3 4 5 6 7

0V

Figure 1 After you press and release S1 23 times, the DAC produces a constant-4-mA-current output.

APRIL 23, 2009 | EDN 51

edn081127di43931 DIANE
(PLACED IN THE 12-15 FOLDER)
designideas
source, which is no more than a few you can measure a voltage of 0.400xV tivity to temperature, immunity to sup-
10s of microamperes, is harmless to the on this resistor, where xm4, confirming ply-voltage variations, and high initial
precision of the reference source. the high-precision, constantly flow- accuracy. Current-output DACs also
By connecting a high-precision, ing current of 4 mA. The actual full- exhibit output resistance in the 10s of
100V resistor between the IOUT pin and scale-range error of IC1 is far below its megohms.
ground and generating 23 clock pulses, guaranteed worst-case value of 60.3% This circuit uses S1 to generate
full-scale-range error (Ref- the SCLK signal for testing purposes
TABLE 1 Effects of the single erence 1). Hence, you must only. For power-on-the-go applica-
bits of the control command divide the observed relative tions, you can use a free-running clock
D2D1D0=101 Selects 4- to 20-mA current range error of the 4-mA current, with a frequency as high as 200 kHz.
D3=0 Disables daisy-chain operation with a value not exceeding You can supply the pull-up resistor at
0.1%, by four because the the FAULT output and IC2 from the
D4=1 Enables slew-rate control current scale is 20 mA24 AD5422’s DVCC pin.EDN
D7 to D5=101 Selects slew-rate size of 4 LSB mA516 mA. The total
D11 to Selects slew-rate update-clock full-scale-range error of the R e fe r e nce
D8=0101 frequency of 69.444 kHz DAC in this case is thus less 1 “Single Channel, 12/16-Bit, Serial
D12=1 Enables outputs
than 0.1%/4, or 0. 025%. By Input, Current Source and Voltage
using the constant-current Output DACs, AD5412/AD5422,”
D13=0 Deactivates external-resistor pin source employing a mono- Analog Devices, 2008, www.analog.
D14=1 Increases output voltage by 10% lithic DAC, you get high com/static/imported_files/data_
D =0 Concerns only the voltage output resolution, negligible sensi- sheets/AD5412_AD5422.pdf.
15

Convert negative inputs Current through R1 and R2 should be

to positive outputs at least 2 mA. The IC1 output, which is

IC2’s input, is 10.5V higher than 25V,
Shane Chang and Budge Ing, Maxim Integrated Products, Sunnyvale, CA which is 5.5V with respect to common
ground.


You can obtain a precise, posi-
tive-output voltage from a nega-
tive-voltage supply with a boost con-
verter and a linear regulator. The input
and output capabilities of the circuit in
Figure 1 depend on the allowable I/O
voltages of IC1 and IC2. In this case,
IC1 and IC2 convert a 25V input volt-
age to a 3.3V output voltage.
IC1 is a boost converter that accepts
25V when its VCC pin connects to
common ground—that is, the ground
of the negative-power-supply input.
Voltage divider R1/R2 at IC1’s output
provides feedback that sets the output
voltage 10.5V above IC1’s ground pin.
With the feedback-threshold voltage
factory-set to 1.226V, you can choose
values for R1 and R2 using this equa-
tion: (1.226V/R2)3(R11R2)510.5V.
IC2, a linear regulator whose ground
pin connects to the common ground,
accepts input voltages as high as 6.5V.
Its output is factory-set at 3.3V. Figure
2 shows the output voltage versus the
output current for the circuit in Figure
1 with input voltages of 24.5, 25, and
25.5V.EDN

22 �H 3.3V
OUT
IC2
D1 MAX8875EUK33
CMDSH2-3
100k
SW LX IN
IC1 R1
4.7 �F 10 pF
MAX8574EUT 2.1M POK
SHDN
VCC FB 1 �F
R2
GND
287k
1 �F
SHDN GND
POWER OK
1 �F

Figure 2 The circuit’s output volt-

�5V COMMON age drops as current increases.
Plots indicate source voltages of
Figure 1 A two-IC circuit converts a 25V input to a 3.3V output. 24.5, 25, and 25.5V.

52 EDN | APRIL 23, 2009

edn081205di43911 DIANE
(PLACED IN THE 12-15 FOLDER)
 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

CMOS-NAND gates control D Is Inside

sump pump 32 Use an LED to sense and emit
light
V Gopalakrishnan, Indira Gandhi Center for Atomic Research,
Kalpakkam, India 34 Two instrumentation amps


With just a few NAND gates,
you can control sump pumps
and other pumps that keep your base-
ment from flooding and maintain
water levels in tanks. The circuit in
Figure 1 receives 12V signals from
L1, the lower water level, and L2, the
upper level, of an underground tank.
You adjust the gap between these two
levels to avoid short cycling of the
pump. When the water level touches
the maximum level of L2, the pump
switches on to fill up the overhead
tank. When the water level falls
below the low level of L1, the pump
switches off.
NAND GATES HCF4093B
L2 1 14
3 13
2 11
R1
560 A
12V
When the tank is empty, sensors L1
and L2 and Gate D are at low levels
because the outputs of gates B and A
are high. When the water level rises
and shorts 12V through L1, the gate
outputs remain the same. When the
water level further rises and shorts
12V with L2, then the output of Gate
A becomes low, which forces Gate D
to a high level. That action, in turn,
latches Gate B’s output low. A low
output on Gate B pulls down the SSR
(solid-state relay), which turns on the
sump pump (Reference 1). Simul-
taneously, the high output of Gate
D turns on the gated oscillator and
12V
R2
10k
�
12
480V-AC, 16A
D SOLID-STATE
RELAY
�
make accurate voltage-to-current
source
36 Simple circuit indicates health
of lithium-ion batteries
ETo see all of EDN's Design
Ideas, visit www.edn.com/design
ideas.
sounds the piezoelectric buzzer.
When the water level lowers below
level L2, the pump remains on because
of the latched B and D gates. If the
water level falls below sensor level L1,
the output of Gate B becomes high,
which turns off the pump. This action
0.37-kW, 230V-AC
PUMP MOTOR FUSE
M
RDN 275/14
METAL-OXIDE
230V AC
VARISTOR

R2 B
5
560k 4
6
L1 7
PIEZOELECTRIC
C BUZZER
8
10
9 12V
TANK
12V
R1
100k

C
0.01 �F

Figure 1 A sump-pump controller uses a quad-NAND gate to drive a solid-state relay.

edn081215di44041 DIANE
PLACED IN 2-5 FOLDER

28 EDN | may 14, 2009

designideas
makes the output of Gate D go to a low
level, which stops the oscillator and
thus the piezoelectric buzzer.
The circuit uses HCF4093B Schmitt-
trigger-input NAND gates to square
the slow signals. The input resistor,
R1, has a value of 560 kV. Checking
the circuit with a glass of filtered water
shows an improved conductivity for
ground water. Raising the value of the
input resistor to a higher value is also
not objectionable after you account
for pickup and the voltage drop across
the resistor due to the input leakage
current.
The solid-state relay may have back-
to-back connected SCRs (silicon-con-
trolled rectifiers), random turn-on,
and snubber circuitry to handle the
motor load (Reference 2). Choose an
SSR with a voltage rating that is dou-
ble the working voltage and five to 10
times the current rating of the motor
for withstanding dV/dt and the surge
current. You should also use fast-blow
fuses or semiconductor fuses with less
than the I2t rating of the SSR, where
I is the current and t is the duration
of current flow in seconds. Choose ap-
The parallel sen-
sor wires avoid
the chance of a
moisture interface
between the wires
when the water
level falls below
the sensors.
This circuit uses sheathed, single-
strand, thick-gauge, edge-stripped
copper wires as sensors. You can con-
nect the sensor wires in two-way por-
celain connecters, which you house
in a box and place at the top of the
tank. The parallel sensor wires avoid
the chance of a moisture interface be-
tween the wires when the water level
falls below the sensors. You can also
use any other high-conductivity and
noncorrosive wire material in some
configurations. The power supply is
floating.
With few modifications, the circuit in
tank in which you want to maintain a
level of water or any conductive liquid.
Mount sensors L1 and L2 in the tank the
same as those in Figure 1. Switching
on the power supply causes the pump to
begin to fill up the liquid in the tank.
When the level reaches L2, the pump
turns off. The pump remains off until
the level falls to L1. When the level falls
below L1, the pump again starts filling
the tank until it reaches L2. The piezo-
electric buzzer announces that the pump
is running.
You can also control pumps with
three-phase motors using a three-
phase SSR or adding one appropriate-
ly rated single-phase SSR to this cir-
cuit. In this case, you can connect the
inputs of the two SSRs in series. One
SSR on each phase controls two of the
phases, and you directly connect the
third phase.EDN
R e fe r e nce s
1 “Solid-state relay applications,”
Western Reserve Controls, www.
wrcakron.com/applications/SSR_
applications.pdf.
2 “Single-phase SSRs,” ERI Solid

propriate SSRs for different ratings of Figure 2 can perform a slightly differ- State Relays, 2007, www.electronic
pump motors. ent function. Assume that you have a relaysindia.com/prod_001sjk_3.html.

12V

NAND GATES HCF4093B

L2 1 14
3 13
2 11
R1 12
560k A
D
12V R2
0.37-kW, 230V-AC
10k
PUMP MOTOR FUSE
M
R2 B
5 �
560k 4 480V-AC, 16A RDN 275/14
6 SOLID-STATE METAL-OXIDE 230V AC
L1 7 RELAY VARISTOR
�

PIEZOELECTRIC
TANK C BUZZER
12V 8
10
9 12V

R1
100k

C
0.01 �F

Figure 2 Connecting the potentiometer to NAND Gate B creates a water-level controller.

edn081215di44042 DIANE
PLACED IN 2-5 FOLDER
may 14, 2009 | EDN 31
designideas
Use an LED to sense and emit light portional to ambient light. The circuit
comprises a PWM (pulse-width modu-
Rafael Camarota, Altera Corp, San Jose, CA lator) for driving the LED, a light-in-
tensity-measurement block, and a con-


LEDs in portable devices often
show power status, battery sta-
tus, or Bluetooth-connection activity.
LEDs can be major factors in determin-
ing battery life because their intensity
is directly proportional to power drain.
Using a simple circuit, the MAX IIZ
CPLD from Altera (www.altera.com)
can measure the analog-light level of
its environment and then drive an
LED at a proportional analog intensi-
ty level. A single LED can both sense
and emit light with the same LED and
bias resistor. The circuit in Figure 1 re-
quires only 45 logic elements, and the
programmability of the CPLD makes it
easy to quickly adjust the parameters
of the circuit to the characteristics of
any LED.
You can reduce the power consump-
tion of a flashing LED by increasing the
flash period, decreasing the flash pulse
width, or decreasing intensity. Control-
ling the LED intensity based on ambi-
ent light reduces LED energy usage by
more than 47% without affecting ap-
pearance. Figure 1 shows a circuit that
uses an Altera EMP240ZM100C7N
CPLD, LED, resistor, and clock source
to blink an LED with an intensity pro-
trolling state machine and timer.
The state machine includes one hot
state comprising an 8-bit shift register
initialized to the 00000001 binary. The
carryout of Count 12, a 12-bit coun-
ter, generates an 8-Hz enable signal
for state machine Shift 8. Thus, each
of the eight states of the state machine
is active for 125 msec. In State 0, the
reset state, PWM Count 4 block and
light-measurement block Count 8 are
reset. State 1 is the light-intensity-
measurement state, which enables a
frequency counter, Count 8. Enabled
for 125 msec, Count 8 counts the cy-

PWM
VCC
COUNT 4 4-BIT ADDER
CIN
UP COUNTER
CLOCK PWM[3..0] DATAA[3..0]
Q[3..0] A RESULT[3..0]
STATE 2 DATAB[3..0] A+B
CNT_EN
B
ACLR
STATE 0 COUT
COUNT 4
ADDER
NAND2
OUTPUT
CATHODE

INSTA INTENSITY[7..4]

STATE 2
COUNT 8
OR2 NOT
OSCILLATOR 1 UP COUNTER
CLOCK
INTENSITY[7..0]
LED INSTB STATE 1 AND2 Q[7..0]
OR2 INSTD
CNT_EN
COUT
ACLR
ALT_ DFF INSTF
BIDIR IOBUF INSTC NOT COUNT 8
ANODE PRN
PIN 1 STATE 0
D Q
NOT
INPUT
INSTE
BUFFER

CLRN
INSTG
DFF
LIGHT-INTENSITY MEASUREMENT STATE 1

RESET COUNT PWM WAIT

COUNT 12
SHIFT 8 FREQ
UP COUNTER
32-kHz INPUT LEFT SHIFT
OSCILLATOR CLOCK Q[11..0] CLOCK
ASET 1 STATE 0 STATE 1 STATE 2 STATES
COUT ENABLE 3 TO 7
SHIFTOUT
COUNT 12 SHIFTIN Q[7..0] STATE MACHINE AND TIMER
8-Hz STATE[7..0]
OSCILLATOR ASET

INPUT STATE MACHINE

RESET

Figure 1 This simple MAX IIZ circuit uses an LED as an emitter and a sensor.

32 EDN | may 14, 2009

designideas
cles exiting the light sensor. The cir-
cuit senses the light by biasing the LED
and current-limiting resistor such that
the cathode lead of the LED is at logic
one. The anode connects to a relax-
ation oscillator that starts with anode
at logic zero. The LED pulls up the
anode in proportion to the amount of
light hitting the LED. The reverse-bi-
ased LED acts as a solar cell with out-
put current proportional to light. Once
the slow-rising anode signal reaches
the threshold of the input buffer, the
Pin 1 signal becomes a zero, and the D
flip-flop, DFF, toggles to zero and drives
the anode signal to zero, making Pin 1
a logic one and tristating the input buf-
fer on the next clock cycle, allowing
the anode signal to rise again.
The frequency of Oscillator 1 is pro-
portional to light intensity, with typi-
cal frequency for bright light of ap-
proximately 2000 Hz. The Oscillator
1 signal drives the clock of Count 8.
Count 8 resets in State 0 and then is
enabled in State 1 for 125 msec. In
bright light, Count 8 might count to
250 at the end of the measurement,
and, in low light, it might count to
only 16. The counter’s COUT signal
feeds back to the enable so that the
count will saturate at a count of 255
and prevent high-intensity light from
wrapping the counter back to zero and
taking a false measurement.
Two instrumentation amps make
accurate voltage-to-current source
Frank Ciarlone, Analog Devices, Wilmington, MA

Many designs require precise
voltage-controlled current
sources, especially in the presence of
variable loads. Common approaches,
which use a few op amps and a hand-
ful of passive components, have in-
herent errors due to nonideal com-
ponent characteristics, such as finite
open-loop gain, common-mode rejec-
tion, bias current, and offset voltage.
Designs using operational amplifiers
may require precision resistors to set
gain and additional capacitors for sta-
bility. In addition, some circuit designs
34 EDN | may 14, 2009
State 2 is the LED’s blinking state.
This state blinks the LED for 125 msec
at an intensity that a PWM controls.
In State 2, the cathode and anode
pins are bias to the emitter mode. The
emitter mode forces the anode signal
to VCC. The cathode node connects to
the PWM output. A logic zero on the
cathode node lights the LED, and a
logic one turns it off. The cathode sig-
nal is the inverted form of the PWM
output.
In this example, the PWM is a 4-bit-
resolution PWM, but you can use more
or fewer bits. The PWM comprises bi-
nary counter Count 4 and a binary, 4-
bit adder. The Count 4 counter is en-
abled in State 2, and the cycling output
connects to the A input of the 4-bit
adder. The B input of the adder con-
nects to the four MSBs (most signifi-
cant bits) of the light-sensor-frequency
counter. The carryout of the adder is
the PWM output. The carry-in of the
adder is a constant logic one.
The following examples show how
the PWM works:
• A logic zero from the intensity
measurement results in a logic zero
at carryout when Count 4 is zero
through 14 and a logic one when
Count 4 is 15. This 6.25% duty
cycle is a very low-intensity level.
• A value of seven from the intensity
measurement results in a logic zero
provide currents that are not directly
proportional to the input voltage. The
voltage-to-current converter in Figure
1, for example, relies on the fact that
the collector current is approximately
equal to the emitter current and pro-
vides current in only one direction.
With two instrumentation amplifi-
ers and two transistors, you can build
a 0.01%-accurate voltage-controlled
current source (Figure 2). This current
source features a 610V input-voltage
swing that is directly proportional to
the output current. It maintains high
at carryout when Count 4 is zero to
seven and a logic one when Count
4 is eight to 15. This 50% duty cycle
is a medium-intensity level.
• A 15 from the intensity measure-
ment results in no logic zero at car-
ryout for any Count 4 value and
a logic one when Count 4 is zero
through 15. This 100% duty cycle
is a full-intensity level.
The only function of states 3 to 7 is
to wait for the next LED-flash cycle.
You can add or remove states to change
the flash rate.EDN
R e fe r e nce s
1 Nicholls, Geoff, “Red LEDs function
as light sensors,” EDN, March 20,
2008, pg 90, www.edn.com/article/
CA6541376.
2 Myers, Howard, “Stealth-mode
LED controls itself,” EDN, May 25,
2006, pg 98, www.edn.com/article/
CA6335303.
3 Gadre, Dhananjay V, and Sheetal
Vashist, “LED senses and displays
ambient-light intensity,” EDN, Nov 9,
2006, pg 125, www.edn.com/article/
CA6387024.
4 Dietz, Paul, William Yerazunis, and
Darren Leigh, “Very Low-Cost Sens-
ing and Communication Using Bidi-
rectional LEDs,” Mitsubishi Research
Laboratories, July 2003, www.merl.
com/reports/docs/TR2003-35.pdf.
accuracy, even while delivering as
much as 90 mA of output current. The
AD620 low-power, low-drift instru-
mentation amplifiers from Analog De-
vices (www.analog.com) provide cir-
cuit control and error correction but
are not part of the output circuit. Thus,
you can substitute higher-power tran-
sistors for Q1 and Q2 to achieve high-
er output currents. You can configure
the instrumentation amplifiers for any
gain of one to 10,000 to accommodate
input signals lower than 1 mV. Simply
connect a resistor across the inputs of
both IC1 and IC2 to achieve the desired
gain.
The first instrumentation amplifier,
IC1, controls the base voltage of the
push-pull output stage. The resistors
 designideas
Equations for DI4439 PLACED IN THE MARCH 5 FOLDER

and diodes provide bias to Q1 and Q2 VDD 15V

to eliminate
Equations crossover
for DI4439 distortion.
PLACED ICIN2
THE MARCH 5 FOLDER 15V

provides error correction

Equation 1 and accounts VIN V�IC1
� IC
R1 VOUTIC1
for deltas in the base-to-emitter volt- 1
AD620BN R1
Equations for DI 4439 PLACED IN THE MARCH 5 FOLDER
�
V
age. The error voltage, which you mea-
( )
IC1

+ VREFIC1 5 .FOLDER

� 5k
Equations
sure forVIN
OUT
differentiallyDI 4439
ICfrom
VI+CD
= PLACED 1 V A IC1MARCH
INjunc-
/DIC 1 THE
ions for DI4439 PLACED
Equation 1 THE 1  the
MARCH 1 52FOLDER  IC
VREFIC1
Q1
tion to the output voltage, feeds into �
�15V
D1 2N2222
PLACED IN THE MARCH 5 FOLDER
the reference pin offorICDI , summing it Q 1N4148

( )
VOUT RL
Equations 1 4439 PLACED IN  THE MARCH 5 FOLDER
1

withVEquation
the
OUTinput = 1voltage.
V + VIC1 result

A IC1 is +V anREFIC1  . �
1  IC12 The
ICEquation
IE D2 IOUT
Equations for Equation
DI 4439 current
output PLACED
1 that INisTHE MARCH
directly propor- 5 FOLDER
ion 1 VIN 1N4148
tionalVto the input
achieves OUTIC
a
=  V=I+CV1
V1REF
0.01% 
voltage.
IC1 typical OUTIC (This circuit
V1 =AV
dc ICI1C+
+ 
2 accuracy 2 V
VREF  .
21A
ICIC )(
 IC25 +FOLDER
VREFIC 2 . ) 15V Q2

(
Equations for
)
DI 4439
( PLACED IN THE
) MARCH
IC R2
Equation
= 610V 2 V1 A
Equation .
 +
TIC1 =  VIC1VIC
V 1 A
across
OUT 1 a1 
ICIC
+V VI+REF
C1 input
IC. 1 span + VREF
IC1 and 1.5% 
IC1 
5k 2N2904
IC 1 V�IC2

)
Figure 1 The voltage- VOUTIC2 �
Equation 1 
typical ac accuracy at 1 kHz with an IC2
C1 A IC1 + VREFIC1  .V
 Equation
output = VOUT
VEquation
voltage
REF IC1 OUT of1 =65V
2IC  V
IC
= +V + 
( (
V A
C1IC2VIC1 ICA2IC1 IC
23 Ip-p.
+ 2VREF VREFIC
+to-current

IC1 
) )
. 2 . converter
relies on the fact that
AD620BN V�
�
IC2 �15V

ion
VOUT2 =  Equation
Equation
+ 
( )
The1equations
2
1 VICcurrent
 VICoutput 1 A IC1 are:
for calculating the
+ VREF  . the collector current
VREFIC2
IC1
V REFICV =V
1 OUT OUT=V ICOUT
( ( ) )
IC1 
V= + +
= VICIC12 VIC
IC1IC2

V A + V
IC12is

1 + ICV
Aapproximately
ICREF (  ) + VREF ,
2 IC2
. +
VIC2 A IC2
equal
 �15V

( ( )
 ( ) )  and provides current Figure 2 This handy voltage-to-current converter deliv-
2 IC 2
= VOUTIC 2 =VV + Equation
 =VV + A
3 =2 +
Equation
+VV  V .

A  + V to the
. emitter current
C1
V
REF
OUT 211= ICV
ICICIC OUT
2IC1ICICV A2ICIC12 +ICV2REFIC
2 2 IC1 IC
REF 2 . REFedn090305di44391
IC1  IC 2 DIANE
+ V 2 A
Equation
VIC2 ) IC2 VEquation

IC2 + V REF
OUTV=
.
REF
VOUT
3 = VOUT
Equation IC 2
4= ( VIC =1( VI+C2
+ V
IC1
) AV IC1)+Ain(ICVonly
2IC+2 VREF ). IC2
+  one 
V direction.
A
IC1

IC2
(PLACED IN THE 4-23 FOLDER)
+ VREFers ,high accuracy over a range of conditions.

IC2 IC 2
IC1 IC 2 IC 2

OUT = ( V2IC2V ) AIC2 + VREF A. A= A + =V1+; VV = A0. + V ,

ion
VREF Equation +3
3 = V Equation 

1OUTIN ( VIC10; V IC1) IC1IC2( IC2 REF ) IC2

IC2
IC1 IC 2
VOUTV=IC +V = V , =V +=   IC 2  
IC1 IC1 REF 1 IC
IC 22

T = VOUT =V(REF ) ( ( ) ) +2V(+VVIC )

IC1 IC 2

( IC2IC2 ) IC2 REF

VVOUT+  Equation
=VVOUT 4 = 3+ + +V
Equation  A + V
  A IC2 + VREF , 
IC1
IC1
= OUT A =
IC1
IC1 +
V V V
IC1 
V
IC1
V A A
IC 1
IC + 2
REF .
IC
IC2 1
IC 2,
IC 2 IC 2
IC2 IC 2

) ( )
IC1 IC 2
+ V 3A + V
VEquation
 
+ A IC=2 +
=IC( 1VIC1 ICV2 = 1);A IC1 ( IC2 ) AIC2 + VREF ,
V + VREF =+, A
IC2 
IC1 = VREF+ =V0+. V
IC 1 VIN ,4V
IC1 IC1 IC2VEquation
VEquation OUT = VOUT 5 0; A IC1 IC 2 
IC1 IC 2

IC2
edn090305di44392 DIANE
IC1 IC 2(PLACED IN THE 4-23 FOLDER)

= ( V3IC1V ) A IC1 + ( VIC2V ) A IC2 + VREF ,

ion 4 where
Equation
Equation +4  + 
VOUT = VOUT IC1 IC2 0.1
+ =V ,V
IC1 
= 0; A IC1 = A IC2 = 1; VREF = 0. IC 2
VIC IN IC1
IC11 ==(0A )+, = 0. ) AIC2 + VREF ,
1
Equation 5 =4V + + V + V IC 2

2 ==1(;VVIC 1V ) A IC1 + ( VIC2V


+ = V Equation V = 0;+REF 
A, IC
VOUT AIC IC22 = 1; VREF

= VIN , V =V0V OUT
A1IC=1V=IN
; IC
IC1 OUT IC1 . IC 
IC1
IC2
IC 2

IC2
IC1 IC 2 ERROR IC 2
Equation
A 4 2 = 1Therefore,
IC1 = A IC ; VREFIC 2 = +0. 
(%)
VIC1 +=5 VIN , V+IC1 = 0
Equation ; A IC1 = A IC2 = 1; VREFIC 2 = 0.

V
Equation
ion+ 5 = V , Equation

=
VOUT =Equation
0; 4
A
5 V
=
IC1
A
+ V
=
6 IC2VIC2 ,
1; V = 0 .
( 0.01
)
VIC1 IN IC1 IC1 IC2 REFIC 2 R LOAD =1 k� R LOAD =100�
or
+ = VVOUT , V  = VIC
Equation
I OUT=
+ +
0
5VINV.IC
=;1 A
+ V ,
=2A ICIC 2 (
2 = 1; VREFIC 2 = 0.
)
= V
TEquation
+ +
V
VIC
IC1 5 IC2 (
+VVEquation
1
OUT
= + +6 + R
IC
IN
2 V ,IC
IC
1
1
) V IC 
2
IC
LV
1
(
IC 2 ,
0.001)
) 0.01 0.1 1 10 100
V This circuitVIN provides a wide output
IC2 ,
I OUT
range,
Equation
EquationV=OUTas
5as well R L output
+
6 =. VIC1 +current +
VIC2

VIC2is ,
that ( ) IOUT (mA)

ion
VOUT IC1
Equation
6 = V +directly
+ +
age and
(6
VIC2proportional

VIC2 ,
high VIN )
to the input volt-
Figure 3 The circuit in Figure 2 provides a wide output range, output current
I OUT = linearity
. and precision
that is directly proportional to the input voltage, and high linearity and precision.
V
= IN .
RL
(FigureV+IN3).
OUT ==VIC1 +
VIOUT
RL
EDNR+ 6 
Equation
. VLIC 2 (
VIC2 , ) EDN090205DI4439FIG3 MIKE
Equation 6
VIN
I OUT = .
RL
VINEquation 6
I OUT = .
RL
V
I OUT = IN .
Simple circuit indicates health situations occur. This fact doesn’t
mean, however, that all cells are bad.
RL
of lithium-ion batteries In most cases, you can replace the dis-
charged battery and increase your de-
Fritz Weld, Friedberg, Germany vice’s lifetime. Figure 1 shows the cir-


Lithium-ion batteries are sensi- cell below the margin that the manu- cuit for testing battery packs.
tive to bad treatment. Fire, ex- facturer defines. Modern battery char- When the supply voltage is lower
plosions, and other hazardous condi- gers can manage the hazardous condi- than 2.6V, no current drives the base
tion may occur when you charge the tions and deny operation when il­legal of the transistor. LED1 lights up, and

36 EDN | may 14, 2009

designideas
LED2 is off. When the volt- device as a permanent display,
age exceeds 2.6V, the transis- � especially when it is in storage.
tor begins to short LED1, turn- LED2
Although a fully charged 32-
ing it off and lighting LED2. 1k Ahr cell will expire after about
This condition indicates that BATTERY
a year, an empty battery of the
the battery is below the allowed 1N4148 same size but slightly higher
UNDER
limit for recharging. The volt- TEST than the allowed margin for
1k
age margins highly depend on charging will expire after one or
LED1
the type or color of the cho- two days.
sen LEDs. A standard red LED 2N3904 You can build an array of in-
�
has a forward voltage of 1.7V; a dicators in one test module. By
green LED, about 2.1 or 2.2V. connecting to the measuring/
Figure 1 LEDs indicate the health of a battery
The circuit in this design uses balancing port of the pack, you
based on its voltage.
red LEDs with forward voltag- can easily inspect a whole pack
es of approximately 1.6V at 2 with one view. Adding zener di-
mA. Other LEDs may require a simple of operation. Although this simple de- odes in series to the LEDs also makes
redesign, mostly resulting in the re- vice draws little current, you cannot this circuit a simple indicator for high-
quirement for a Schottky diode instead expect a long battery life if you use the er voltage levels.EDN
of the 1N4148 in this circuit. Even
white or blue LEDs with 3V or more
TABLE edn081127di43941
1 Possible LEDDIANE conditions for battery voltages
forward voltage make sense for certain
(IN 12-15 FOLDER)
applications. LED1 LED2 Indication Condition
Lower-value resistors increase the Off Off 0 to 1.6V Battery is empty, defective, or unusable.
brightness of the LEDs but increase the On Off 1.7 to 2.5V Battery is below allowed limit for recharging.
supply current, as well. Table 1 shows
how this indicator provides three states Off On More than 2.6V Battery is OK and can be charged.

38 EDN | may 14, 2009

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Current-sense monitor and D Is Inside

MOSFET boost output current 47 Multiplexed, programmable-
Gyula Diószegi and János Nagy, Divelex Ltd, Budapest, Hungary gain, track-and-hold amplifier has
instrumentation inputs

A previous Design Idea des­ es. However, you may find it difficult
cribes a programmable current to purchase BCD switches that can 48 Simple circuit smoothly drives
source that used a three-terminal Na­ handle more than 25 mA, limiting stepper motors
tional Semiconductor (www.national. the circuit’s output current. By apply­ 52 Excel spreadsheet yields RLC
com) LM317 adjustable regulator ing the simple, four-pin Zetex (www. best-fit calculator
(Reference 1). Although that circuit zetex.com) ZXCT1010 current-sense-
lets you program the output current, monitor chip, you can boost current 54 Automatically turn
the load current flowed through the because it doesn’t flow through BCD secondary lamp on or off
BCD (binary-coded-decimal) switch­ switches (Figure 1). The load cur­ ETo see all of EDN's Design
Ideas, visit www.edn.com/design
RSENSE ideas.
VIN

5
IRF520

VIN
rent results in a voltage on the sense
LOAD 10k
4 resistor RSENSE. The voltage on R1, the
100V resistor, is the same as that on
R1
100
� � RSENSE, generating an output current
on R1: IOUT31005ILOAD3RSENSE, and
VOUT5 IOUT3ROUT, where IOUT is the
4.7 nF output current, ILOAD is the load cur­
IOUT
rent, and VOUT is the output voltage.
VOUT RLOAD
2 GND 3 � You can apply the output voltage as
TLC271 a control voltage to regulate the load
ZXCT1010 VREF � current.
One application for this circuit
0.25k 0.5k 1k 2.5k 5k 10k 25k 50k 100k would be to refill accumulators in
portable devices. In this case, the
0.125k 1.25k 12.5k
circuit works at 18V. The Fairchild
8 4 2 1 8 4 2 1 8 4 2 1 Semiconductor (www.fairchildsemi.
0 0 0
com) IRF520 is an N-channel, power-
9 1 9 1 9 1
2 2 2
MOSFET chip in an aluminum heat
8 8 8
sink with as much as 9.2A current
7
3
7
3
7
3 and 0.27V drain-to-source resistance
6 5
4 6 5
4 6 5
4 to connect the load current. An op
amp controls the IRF520 in the feed­
100 TO 10 TO 1 TO
900 mA 90 mA 9 mA back of the load current. In this appli­
cation, the maximum output current
is 1A, and the value of the sense resis­
tor is 0.1V. The PCB (printed-circuit
Figure 1 Passing current through a MOSFET and regulating it with a current-
board) can also have this small resis­
sense monitor bypasses the BCD switches, letting you increase load current.
tance value, which you calculate using

44 EDN | may 28, 2009 edn090423di44401 DIANE

(PLACED IN THE MAY 1 FOLDER)
designideas
the cuprum material’s 35-micron-thick
layer. The BCD switches are in paral­
lel and connect from 125V to 100 kV
to adjust the output voltage on the
op amp’s negative input. The equa­
tions to calculate resistor values are:
VSENSE5RSENSE3ILOAD, IOUT5RSENSE3
ILOAD/100, and R05VREF3100/(RSENSE3
ILOAD). If you choose a value of 0.1V
for the sense resistor and a value of
0.1V for the reference voltage, the
equation becomes R05100/ILOAD.
Applying this equation, you can cal­
culate the four weighting resistors of
the three BCD switches, which you
can determine when the current flows
through only that resistor. For currents
of 800, 400, 200, 100, 80, 40, 20, 10,
8, 4, 2, and 1 mA, the corresponding
resistances would be 0.125, 0.25, 0.5,
1, 1.25, 2.5, 5, 10, 12.5, 25, 50, and
100 kV. If the load current is 1A, then
the output current is only 1 mA, and,
if the load current is 1 mA, then the
output current is only 1 mA. Note that
the IRF520’s surface is on the drain
potential.EDN
R e fe r e nce
1 Guy, John, “Programmable current
source requires no power supply,”
EDN, June 12, 2008, pg 70, www.
edn.com/article/CA6566536.

Multiplexed, programmable-gain, gain equal to 2(11t/10 msec).

Building on the assets of that earlier
track-and-hold amplifier design, this new circuit has the desirable
features of multiple instrumentation-
has instrumentation inputs style differential inputs. Also, neither
resistor matching nor the CMR (com­
W Stephen Woodward, Chapel Hill, NC mon-mode rejection) of the op amp
limits the circuit’s CMR. Stray-capaci­


ADCs need adequate signal-
acquisition analog interfaces to
perform at their best. The classic gen­
eral-purpose ADC front end includes
multiple channels of differential in­
put, digitally programmable gain, and
track-and-hold capability. This Design
Idea presents a new, complete, high-
performance, low-parts-count ADC
til the point when hold reasserts and a
connected ADC samples and converts
the output voltage, the input voltage
and the output voltage are divergent
exponential functions of time, with a
R1
12.1k
MAX4051
tance issues do have an effect on CMR,
but you can minimize this capacitance
by careful circuit layout. The circuit
also has rail-to-rail inputs and virtually
unlimited programmable gain. Further,
VOUT
TO ADC

front end that implements the stan­ 13 CH0 R4 T=14.4 �SEC

14
dard ensemble of functions (Figure VIN
15
CH1
3
2.21k 3
CH2 COM
1). However, it also incorporates the 12
�
6
CH3 LT1022A
concepts of the flying-capacitor differ­ 1
CH4 A
11 C1 2
�
5 10 0.001 �F
ential input and the divergent-expo­ 7
CH5 B
9
R3
C 28.7k
nential negative-time constant that an 4
CH6
8
CH7 EN
earlier Design Idea describes (Refer- R2
ence 1). This Design Idea adds to that 28.7k
GROUND
circuit multiplexed inputs and a versa­ 13
MAX4051
REFERENCE
CH0
tile track-and-hold function. �VIN 14 JUMPER FOR
CH1
The multiplexer address and the state 15
CH2 COM SINGLE-ENDED
of the hold-mode bit control signal ac­ 12
1
CH3
CIRCUITRY

quisition and conditioning. With a hold CH4 A 11

5 10
CH5 B ADDRESS (0=AMPLIFY)
state of zero and the multiplexer’s ad­ 7
CH6 C
9
dress equal to the selected input chan­ 4
CH7 EN
8

nel, the flying capacitor, C1, connects HOLD

to the positive and negative differen­
tial-input terminals, which acquire the OPTIONAL DIFFERENTIAL-
INPUT CIRCUITRY NOTES:
input voltage. Moving the hold state to NEGATIVE TIME CONSTANT=T=(R1+R4+2RON)(C+CSTRAY).
VOUT =VIN[1+(R3/R2)E(t/T)] =VIN2(1+t/10 �SEC).
one isolates C1 from the input. Then,
the multiplexer’s address becomes ze­
ro, and the hold state returns to zero,
initiating regenerative negative-time- Figure 1 This high-performance, low-parts-count ADC front end implements the
constant exponential amplification of standard ensemble of functions.
the input voltage. From that point un­

edn081002di43061 DIANE
PLACED IN THE 10-16 FOLDER

may 28, 2009 | EDN 47

designideas
only the resolution of the SAMPLE AND SAMPLE AND
amplify interval’s timing T=R4C
HOLD
T=�RC
CONVERT HOLD
T=R4C
HOLD CONVERT HOLD
T=�RC
limits gain-set resolution
VOUT ACQUIRE AMPLIFY T
(figures 2 and 3). This cir­ N ACQUIRE AMPLIFY

cuit also has 610V output-

amplitude capability—two 2VIN
N

to four times greater than

that of monolithic digitally MULTIPLEXER ADDRESS ADDRESS=N ADDRESS=0 ADDRESS=M ADDRESS=0
programmable-gain instru­
t=
mentation amplifiers. LOG2(GAIN)�1
The inherent noise and HOLD
dc accuracy of the chosen
op amp, the accuracy and Figure 2 Only the resolution of the amplify interval’s timing limits gain-set resolution.
repeatability of the timing
of exponential generation, ADC sam­
64
pling resolution, and RC-time-con­ 60
stant stability are the main limits on 56
signal-processing performance and the 52
48 edn081002di43062 DIANE
amplifier’s precision—for example, its 44 PLACED IN THE 10-16 FOLDER
gain-programming accuracy, dc error, 40
noise, and jitter. In the circuit, 1 nsec GAIN 36
32
of the amplify-interval timing error or 28
jitter equates to 0.007% of gain-pro­ 24
20
gramming error.EDN 16
12
R e fe r e nce 8
4
1 Woodward, W Stephen, “Flying 0
capacitor and negative time constant 0 10 20 30 40 50
make digitally programmable-gain in- TIME (�SEC)
strumentation amplifier,” EDN, Feb 5,
Figure 3 This graph of input- and output-voltage gain shows the time elapsed
2009, pg 48, www.edn.com/article/
since the track/amplify-logic transition.
CA6632372.

Simple circuit smoothly EDN090528DI4306FIG3 MIKE

drives stepper motors

Uwe Schüler, Institute of Physiology,
Tübingen, Germany


The circuit in this Design Idea drives low-
power, unipolar stepper motors using only a
shift register, a few resistors, and low-power transis­
tors. Adding an inexpensive 4053 analog switch al­
lows bidirectional switching. Compared with other
simple stepper-motor-drive circuits, it has better-
than-half-step characteristics (Figure 1).
After power-up, all shift-register outputs are in a
zero state. Pin QP3 feeds back to the serial input
through an inverter—transistor Q5 in Figure 2 and
analog-switch IC2 in Figure 3. The circuit generates
a sequence of four ones and then four zeros. You can
use this pattern to drive, for example, NPN tran­ Figure 1 An oscilloscope snapshot shows the base voltages of Q1
sistors with emitters that tie to ground and collec­ and Q2 in figures 2 and 3.
tors that tie to the stepper-motor coils. However,

48 EDN | may 28, 2009

designideas
to achieve smoother drive character­
istics, the shift-register outputs drive
four simple DACs, each comprising
two identical resistors.
These DACs can generate output of Q1 and Q2 (Figure 1). They come
voltages of 0, 2.5, and 5V to drive four close to a quarter-step drive pattern.
emitter followers. A snapshot from an The circuit can use almost any 8-bit
oscilloscope shows the base voltages shift register.EDN

5V

R1
4.7k

FEEDBACK 5V
Q5
R2
BCR133 4.7k
Q1
R3 BC846B
4.7k
9 5V
QS1
10 R4
QS2
2 4 4.7k
D QP0 Q2
1 5 R5
5V STR QP1 BC846B
15 IC1 6 4.7k
OE QP2 5V
3 4094 7 FEEDBACK
STEP_CLOCK CP QP3 R6
14
QP4 4.7k
Q3
QP5 13
12 R7 BC846B
QP6 4.7k MOTOR
11 5V
QP7
R8 COIL 1 COIL 1 COIL 2 COIL 2
4.7k LEFT TAP RIGHT TAP LEFT TAP RIGHT TAP
Q4
R9 BC846B
4.7k

Figure 2 This circuit drives low-power, unipolar stepper motors using only shift-register IC1 and a few resistors and
transistors.

IC2A
4053
1
IN1
15
OUT

IN0 2 5V
CTL EN edn090305di44141
R20 DIANE
10 6 (SAVED 4.7k
IN 3-19 FOLDER)
5V
FEEDBACK
R21
4.7k
9 Q1
QS1
10 R22 BC846B
QS2
2 4 4.7k 13
D QP0 IN1 5V
1 5 R23 IC2B
5V STR QP1 14
15 IC1 6 4.7k 4053 OUT
OE QP2 12 Q2
3 4094 7 FEEDBACK
STEP_CLOCK CP QP3 IN0
R24 BC846B
14 EN CTL
QP4 4.7k
5V
QP5 13 6 11
TO MOTOR
12 R25
QP6 4.7k
QP7 11 Q3
R26 BC846B
4.7k 3
IN1 5V
R27 IC2C
4
4.7k 4053 OUT
5 Q4
IN0
BC846B
EN CTL
6 9

DIRECTION

Figure 3 This circuit enhances the one in Figure 2 by adding an inexpensive 4053 analog switch, allowing bidirectional
switching.

50 EDN | may 28, 2009

edn090305di44142 DIANE
designideas
Excel spreadsheet yields RLC best-fit calculator
Alexander Bell, PhD, Infosoft International Inc, New York, NY


Commercial off- ern RIA (rich-Internet-
the-shelf software application) concept and
such as Microsoft (www. corresponding develop­
microsoft.com) Excel lets ment tools, available on
you automate engineer­ the market, let you build
ing functions (references Web applications with
1 through 3). This De­ the level of interactivity
sign Idea explains how and responsiveness close
you can use Excel to cal­ to those of the desktop
culate the values of two application. A Web-based
passive components—re­ application provides for
sistors, inductors, or ca­ easy implementation and
pacitors—from the stan­ maintenance. The user
dard E-Series, which Figure 1 In the user interface, you enter the user-defined functions needs only a Web brows­
comprises E6, E12, E24, FitR 1234, P, or E192 into any cell of the Excel worksheet. er. Web applications are
E48, E96, and E192, that essentially platform-inde­
you can use in circuits such as filters. values of R1 and R2 in commonly used pendent and globally accessible. Web-
The application’s results depend on electrical-engineering format by apply­ based applications of the RLC calcu­
whether you select a parallel- or a se­ ing a scientific-to-engineering format- lator don’t require the user’s machine
ries-connected topology. conversion function, E2BOM(). to have MS Office. You can also place
The calculations appear in an Excel The computation engine for electri­ the application in password-protected
spreadsheet that you can download cal resistance and inductance compo­ directories from which you can control
from the online version of this Design nents uses the same formulas: a simple access to them. A demo version of an
Idea at www.edn.com/090528dia. The sum of the resistance for the series con­ online RLC best-fit calculator incorpo­
VBA (Visual Basic for Applications) nection and a sum of conductance for rates the latest set of Microsoft tech­
source code for this project resides in a parallel topology, whereas, in the case nologies, such as ASP.NET, C#, and
single code module (Listing 1, which of the capacitors, the formula is vice Ajax, providing a rich user experience
is also available with the online ver­ versa. You can also fine-tune the func­ with high interactivity and responsive­
sion of this article). It contains three tions by changing the constant values ness (Reference 4).EDN
main public functions, FitR(), FitL(), corresponding to the upper and lower
and FitC(), and several private aux­ search limits (Listing 1). Thus, you R e f e r e n c e s
iliary functions. The key algorithm can extend the search range and in­ 1 Bell, Alexander, “Add CAD func-
loops through the range of values, try­ crease the accuracy, although this pro­ tions to Microsoft Office,” EDN,
ing to find the best fit for the target. cess requires more computation time. March 21, 2002, pg 94, www.edn.
There is an inner loop for the first If you use Microsoft Office 2007, you com/article/CA200384.
value of RLC and an outer loop for must contend with an increased secu­ 2 Bell, Alexander, “Simplify com-
the second one. rity level and set the proper permission puter-aided engineering with scien-
Figure 1 shows the user interface. level to run the VBA content of the tific-to-engineering conversion,” EDN,
You can enter the user-defined func­ Excel workbook. Sept 30, 2004, pg 94, www.edn.
tions FitR 1234, P, or E192 into any This approach is essentially a desk­ com/article/CA454644.
cell of the Excel worksheet. The cells top application, extending the func­ 3 Bell, Alexander, “Voice feedback
accept four arguments and return a text tions of the popular Excel application. enhances engineering calculator,”
string containing the best-fit values, You can install the application on ei­ EDN, July 11, 2002, pg 108, www.
R1 and R2 in this case, and the relative ther a computer or a network. To fur­ edn.com/article/CA231578.
error of approximation. Table 1 shows ther extend its accessibility and bring it 4 Bell, Alexander, “Best Fit RLC Cal-
the functions’ parameter list. For better to the global level, you should consider culator,” www.alexanderbell.us/RLC/
readability, the spreadsheet returns the an online Web application. The mod­ RLC.aspx.
Table 1 functions fitR(), fitL(), and FITC() parameter list
No. Parameter Description Required
1 R Target value Yes
2 ParSer Topology: parallel or serial connection Yes
3 ESeries Standard series: E6, E12, E24, E48, E96, or E192 No: Default value is E24
4 ExtSearch Flag to use preferred search limit or extended No: Default is preferred search range

52 EDN | may 28, 2009

designideas
Automatically turn
secondary lamp on or off
Vladimir Oleynik, Moscow, Russia

You may sometimes need to turn
on a secondary device, such as a
lamp or an alarm, when a device that is
normally on loses power. You can build
a simple circuit using just a transformer
and a relay for this purpose. In the cir­
cuit, a primary load is in series with an
ac-mains transformer (Figure 1). The
transformer connects in an unusual
way. Its usual secondary low-voltage
winding is Winding 1, and its primary
ac-mains winding is Winding 2. Under
these conditions, the main lamp’s volt­
age is slightly less than during its ordi­
nary operation—the ac-mains voltage
minus the voltage drop over Wind­
ing 1. That situation is acceptable in
most cases because the lower voltage
doesn’t greatly affect the operation of
the load—that is, the luminosity of the
main lamp. Select Winding 1 to match
54 EDN | may 28, 2009
the main load’s current needs. In this
circuit, a 220V, 50-Hz ac voltage ap­
pears at Winding 2.
Connect a relay to Winding 2 so
that the secondary loss connects to the
relay’s NC (normally closed) terminal.
Use a relay with a winding that can op­
erate at 220V, 50 Hz for your ac-mains
voltage. For example, you can use a
TR91-220VAC-SC-C relay from Tai-
Shing Electronics Components Corp
(www.tai-shing.com.tw). This relay’s
coil operates at a 220V, 50-Hz, SPDT
MAIN
LOAD
T1
AC MAINS 1 2
Figure 1 A transformer and a relay are all you need to control a secondary load
should the main load fail.
edn081205di43881
(single-pole/double-throw) commuta­
tion of 240V ac under a 40A load.
Using an SPDT relay adds flexibility
in controlling the spare load. It lets you
switch a load on or off with no need for
additional electronic components. In
the figure, a spare lamp turns on when
the main lamp burns out because the
secondary load connects to the relay’s
NC contact.
Select a transformer whose second­
ary winding (Winding 1 in the figure)
has a low-rated voltage that provides
sufficient current for the main load—
the lamp. Match the relay’s rated coil
voltage to the ac-mains voltage and
frequency specifications.EDN
SPARE
LOAD
NC
NO SPARE-LOAD
COM POWER SUPPLY
DIANE
designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Fast 10-line-to-one-line data selector/

multiplexer comprises only two ICs D Is Inside
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia 42 Implement a simple digital-


When dealing with logic opera-
tions over BCD (binary-coded-
decimal) numbers, you often need a
10-line-to-one-line data selector/mul-
tiplexer. In the past, you could use
the famous 16-line-to-one-line 74150
multiplexer IC. Nowadays, however,
when you look at the Web sites of the
renowned semiconductor houses for
the 150 and similar 16-to-one multi-
plexers, such as the 250, the 850, or the
851, you find that vendors have labeled
them obsolete or no longer available.
On the other hand, the eight-line-to-
one-line multiplexers not only have
survived but also are parts of advanced
logic families, such as HC (high-speed
CMOS) and AC (advanced CMOS).
The circuit in Figure 1, a 10-line-
to-one-line data selector/multiplexer,
comprises two eight-to-one multiplex-
serial NRZ data-recovery algo-
ers, IC1 and IC2. The A, B, and C bits rithm in an FPGA
of the address input of IC1 connect to
corresponding address bits—A, B, C, 44 LED strobe has independent
and D—of the main address input. The delay and duration
eight data inputs, D0 to D7, of the cir-
48 Cancel sensor-wiring error
cuit are identical to the equally denot-
with bias-current modulation
ed data inputs of IC1.
Whenever the main address is a bi- 50 Simple FSK modulator enables
nary-coded eight or nine, when A, B, data transmission over low-speed
C, and D5eight, the data input, D4 link
of IC2, is active. When A, B, C, and
ETo see all of EDN's Design
D5nine, D5 of IC2 is active. This
Ideas, visit www.edn.com/design
shift in addressing of IC2’s data in-
ideas.
puts is due to the IC’s modified ad-
dressing: Address bit C connects to
the MSB (most-significant bit) D of
the main address input. The A and B
are common to IC1 and IC2, respec- of IC1 to data inputs D0 through D3
tively. To unite their outputs without of IC2. The eight lowest values, zero
using any additional logic, you must through seven, of the address always
connect the noninverting output, Y, activate a signal of D0 through D3 in

OUT

Y2 W2
Y W Y W
G G
A
A IC1 A IC2
B
B CD74AC151 B CD74AC151
ADDRESS C
C C
INPUTS D
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

D0 D7 D8 D9

DATA INPUTS

Figure 1 The maximum worst-case propagation delay of this 10-line-to-one-line data selector/multiplexer is 27 nsec,
whereas the typical value is only 6.8 nsec. The circuit can also serve as a 12-to-one multiplexer.

june 11, 2009 | EDN 41

designideas
IC2. The output signal of IC1 passes
through one of these data inputs to
the main output, Y2. If necessary, you
can also use the W2 inverting output.
Although the propagation delay from
D0 through D7 to Y2 output is twice
that from D8 and D9 to Y2, it is still
less than 2313.5 nsec527 nsec for the
CD74AC151 with a 5V supply. The
typical delay is only 6.8 nsec.
Note that you can also use the cir-
cuit as a 12-line-to-one-line data selec-
tor/multiplexer by using the remaining
data inputs, D6 and D7 of IC2, which
are idle in this circuit. In such a case,
you attribute another notation of D10
to the D6 input of IC2, and D11 holds
for D7 one. Simultaneously, you must
code the A, B, C, and D address in duo-
decimal code and, eventually, hexadec-
imal code, instead of BCD.EDN

and some buffering registers. The al-

Implement a simple digital-serial NRZ gorithm runs at eight times the serial-
data-stream speed, without a known
data-recovery algorithm in an FPGA phase relationship between both. It
clocks the data into the shift register,
Jef Thoné and Bob Puers, ESAT-MICAS, which implies that, after eight clock
Katholieke Universiteit Leuven, Leuven, Belgium cycles, the shift register will contain a


Serial-data links embed clocks edge detection, a 7-to-1 multiplexer rising edge; a falling edge; or, when the
in their data streams, and those with decoding for multiplexing the input data remains the same, no edge.
clocks must be recovered at the receiv- right-shift-register bit to the output, The multiplexer does not take into ac-
er end. This Design Idea de-
scribes a data/clock-recovery
algorithm for an NRZ (non-
return-to-zero), 1.5-Mbps da-
ta stream in a Xilinx (www.
xilinx.com) Spartan XC3S200
FPGA. The algorithm em-
ploys a modified data-recovery
application note (Reference
1). The application note uses
the DCM (digital-clock man-
ager) on the Xilinx Spartan
and Virtex models, but this
application uses a simplified
algorithm that compares the
data edges, if any, with inter-
nally generated clock edges,
dynamically changing the
data-input-to-data-output de-
lay. The simplified algorithm
allows integration in smaller
CPLDs or FPGAs that lack a
DCM (Figure 1).
The algorithm uses a 3-bit,
free-running counter to gener-
ate the output clock, an 8-bit
shift register to sample the se-
rial data, seven XOR ports for
count cases in which the shift
CLK CLK OUT register contains no edges or
CLK/8
GATING more than one edge.
The edge location is checked
in the shift register using the
DATA OUT
7-TO-1 MULTIPLEXER/XOR XOR-port array, which compares
DECODER/COUNTER-BACKUP
REGISTERS
shift-register bit 0 with bit 1, bit 1
with bit 2, and so on. Depending
on the output of the XOR array,
CLK IN showing where the edge occurs,
DATA IN b0 b1 b2 b3 b4 b5 b6 b7 a certain bit of the shift register
multiplexes to the output. This
action ensures that the output
clock always toggles around the
middle of the output-data bits.
When there are slight differ-
ences in clock speed and serial-
input-data speed—for example,
in the case of clock jitter or
clock tolerances—the data-in-
put phase continuously changes
with regard to the output-clock
phase as the algorithm tries to
track the input-data phase. In
this case, the multiplexer has an
Figure 1 A clock-recovery circuit in an FPGA recov- overflow, which happens when
ers data in a 1.5-Mbps data stream. shift-register bit 7 multiplexes
to the output, the next bit is

edn081215di44161 DIANE
PLACED IN THE 2-5 FOLDER

Figure 2 Doubling a clock output prevents a backward phase jump.

42 EDN | june 11, 2009

designideas
shift-register bit 1, or vice versa.
If bit 7 is output first—that is, the
signal edge_select is 0100 0000—and
the next selected bit is bit 1, with an
edge_select of 0000 0001, a sudden
phase jump in output data occurs. This
phase jump is 2360837/8, or 23158.
Because the next input-data bit already
had shifted in completely in the shift
register, you need to employ a double-
output clock once, so that the register
doesn’t miss a data bit (circled area in
Figure 2).
When bit 1 is output, with an edge_
select of 0000 0001, and the multiplex-
er jumps to bit 7, with an edge select of
0100 0000, a sudden phase jump in out-
put data of 360837/8, or 3158, occurs.
Because the shift-register data bit 7 is a
delayed version of the last clocked bit,
b1, the output clock must be stalled for
one cycle. Otherwise, one bit too many
will clock at the output (circled area in
Figure 3). You can solve the overflow-
phase jumps by gating the output clock
using combinatorial logic.EDN
R e fe r e nce
1 Sawyer, Nick, “Data Recovery,”
Xilinx Application Note XAPP224,
Version 2.5, July 11, 2005, www.
xilinx.com/support/documentation/
application_notes/xapp224.pdf.

Figure 3 Stalling the output clock prevents a forward phase jump.

LED strobe has independent intense. With a bank of six injectors

delay and duration with isolation panels, the reflection off

a person’s shirt or the wall behind him
would interfere with the visual inspec-
Michael C Page, Chelmsford, MA
tion. So the application instead used


The circuit in Figure 1 is not
complex, but it saved the day in
an application involving visual inspec-
tion of the spray pattern of fuel injec-
tors for quality and consistency. In this white HB LEDs (high-brightness light-
application, xenon strobe lights did not emitting diodes) on “gooseneck”-type
work because they take up too much stands for adjustability in the cham-
space, and the light they emit is too ber sections. Although the applica-

5V
R3
100 LED�

R2 BOOST LED2
1k WHITE

LED�
14
LED1 R3
5 VDD 6.8k
GREEN D 1
Q Q1
1 2 3
CLK IC2
CD4013 2 CW 100% 2N2222
4 Q2
IC1A R Q
D1
1N4148 74HC14 6 P2
S D2 2N2222
MAIN CLOCK 50k
1N4148
P1
50k DURATION
GROUND C1 DELAY
0.05 �F
6 5 4 3
CW 100%

R1 C2
IC1C IC1B 0.02 �F
470 74HC14 74HC14

Figure 1 This circuit employs HB LEDs for a visual-inspection application.

44 EDN | june 11, 2009

designideas
tion could have used
the trusty old 555 timer, DELAY
the delay and duration 5
duty-cycle controls in-
teract, which is an awk- 4
ward situation.
The circuit in Figure VOLTAGE 3
1 shows the main-clock (V)
input; the delay and du- 2
ration potentiometers,
P1 and P2; and the HB- 1
LED output. The cir-
cuit also includes an on- -0
0 1 2 3 4
board general-purpose 1 mSEC/DIV
LED for bench testing
Figure 2 With a main-clock input of 650 Hz, the delay is approximately 250 msec, with P1 at
to indicate an input sig-
10%, and the duration is approximately 600 msec, with P2 at 75%. The top trace (blue) repre-
nal, although, when the
sents the strobe delay, the lower trace (green) represents Q1’s base duration, and the 5V trace
circuit is operating at
(red) represents the main clock.
high speeds, this LED is
useless. The main-clock
input is a 5V pulse of
approximately 30 msec
coming from the fuel- DELAY

pump index. Delay po- 5

tentiometer P1 adjusts
4
the on-time delay of the
LED from about 40 msec VOLTAGE 3
to 2 msec, and duration (V)

potentiometer P2 adjusts 2
the LED-on, or flash,
time with a range of ap- 1
proximately 15 msec to
0
15 msec. 0 1 2 3 4
1 mSEC/DIV
The circuit applies
a 5V pulse, the main
clock, to diode D1 and Figure 3 An adjustment change of delay occurs with the same duration as in Figure 2. The top
capacitor C1 to form a trace (blue) represents the strobe delay, the lower trace (green) represents Q1’s base duration,
peak-hold circuit. C 1 and the 5V trace (red) represents the main clock.
then discharges at a rate
that P1 sets. Schmitt trigger IC1A moni- output of IC2 to low. Because IC2 re- start of another in the chamber during
tors C1’s voltage, and, when it reaches quires an active-high signal, you can the same flash period without encoun-
the low threshold of IC1A, it outputs a omit IC1B and IC1C, but you should use tering an error. The circuit also has a
high level to IC2’s clock input, setting a Schmitt trigger following an RC cir- boost switch for a momentary intensity
the Q output high. With IC2’s Q out- cuit for repeatability, especially on slow increase; otherwise, R3 normally limits
put high, the Darlington-transistor pair capacitor-charge/discharge times. the current to approximately 40 mA.
comprising Q1 and Q2 turns on, driv- Figure 2 shows the results of the cir- When you press the boost switch, the
ing the output to the HB LED low at cuit running with a main-clock input Darlington pair, two 2N2222 transis-
the output, lighting the LED. At this of 650 Hz and a delay of approximately tors with current of approximately 400
time, capacitor C2 charges at a rate 250 msec, with P1 at 10%, and a dura- mA, still limits the current, but long-
that P2 sets. When this voltage reaches tion of approximately 600 msec, with term use of the switch will shorten the
the upper threshold of IC1B, IC1C’s out- P2 at 75%. Figure 3 shows an adjusted LEDs’ life. You should tailor the values
put switches to high, resetting flip-flop change of delay with the same dura- of C1, C2, P1, and P2 to the application.
IC2’s output back to low and turning off tion setting as in Figure 2. The new Calculations will vary depending on
the HB LED. The circuit is now ready flash period overlaps the following the logic family you use, but, generally,
for another round. Diode D2 ensures fluid burst. You could, depending on T50.73R3C, where T is the time in
a complete discharge of capacitor C2 the injector nozzle, see the end of one seconds, R is the resistance, and C is
for repeatability when you reset the Q fuel burst of calibration fluid and the the capacitance.EDN

june 11, 2009 | EDN 47

designideas
Cancel sensor-wiring error ble popularity of this—to use the polite

with bias-current modulation term—“mature” technology.

A complicating factor and poten-
W Stephen Woodward, Chapel Hill, NC tial error source affecting these sen-
sors arises from their need for bias-cur-


The approximately 22-mV/8C Diode temperature sensors are com- rent excitation, however. The resulting
temperature coefficient of pact, stable, robust, sensitive, and in- contribution of ohmic IR (current/re-
diode junctions is a popular means of expensive, and, unlike thermocouples, sistance)-voltage drop in the wiring
temperature measurement, especially they require no reference junction. All and the connectors’ resistance to the
in cryogenic applications (Figure 1). of these benefits help explain the dura- sensor’s output voltage create spurious
and temperature-sensitive voltage off-
1.8 sets. These offsets can introduce un-
1.6 acceptably large measurement error.
This situation is especially likely when
1.4 you use small and, therefore, high-re-
1.2 sistance-gauge wire for sensor cabling,
VOLTAGE 1
such as in cryogenic applications. In
(V) those cases, designers prefer exception-
0.8
ally fine-gauge wire to minimize ther-
0.6 mal conductivity and leakage.
0.4 The usual solution to the IR prob-
lem is to employ four-wire “Kelvin”-
0.2
interconnection topologies, in which
0 one pair of conductors carries the sen-
0 100 200 300 400
sor’s bias current and a separate, inde-
TEMPERATURE (K)
pendent pair differentially senses the
Figure 1 The typical 22-mV/8C-voltage-versus-temperature coefficient of diode sensor’s output voltage. This approach
sensors is large and nearly constant over a wide range of temperatures. prevents corruption of the sensed volt-
age by IR drop in the bias pair. This
15V traditional fix works well but compli-
ONE SECTION cates the wiring and doubles undesir-
1M* LTC1043 able thermal leakage due to the extra
14
12 wires, thus defeating much of the point
EDN090611DI4425FIG1 MIKE
of using fine-gauge cabling in the first
13 place.
Figure 2 illustrates a circuit that
1M* ONE SECTION 15V
implements a different approach. It
LTC1043
IB1 IB2
8 �
cancels the wiring-resistance error
11
C2
A1 VOUT and needs only two conductors in the
LTC1043 1 �F � sensor cable. It takes advantage of the
OSCILLATOR 16 7
fact that IR-voltage drop is directly
RW2 0.01 �F
1 �F
proportional to current, but the sensor
10k* voltage is mostly constant. It works by
CRYO-CON TEMPERATURE alternating the magnitude of the ex-
10k*
S400BB SENSOR citation current, IB, between two val-
RW1 ues, IB1 and IB2, where IB152IB2. The ac
15V
component of the resulting signal is
� thus approximately IBRW, where RW is
*FILM RESISTOR
A2 the total wiring resistance plus a minor
NOTES: CIRCLED NUMBERS ARE
�
contribution from nonzero sensor
LTC1043 PIN NUMBERS.
RW=RW2+RW1= TOTAL WIRING
C1
1 �F
impedance.
RESISTANCE. The clock for both IB1/IB2 excitation
IB1= 2IB2.
modulation and synchronous demodu-
Figure 2 This circuit cancels the wiring-resistance error inherent in diode tem- lation of the resulting response is the
perature sensors and requires only two conductors in the sensor cable. internal oscillator of the LTC1043,
which you set to approximately 500

48 EDN | june 11, 2009

edn090423di44252 DIANE
(PLACED IN THE 5-1 FOLDER)
designideas
Hz by connecting the external 0.01-
mF capacitor to Pin 16. The resulting
toggling of the excitation ballast resis-
tance between 1M and 1M11M52M
creates the 2-to-1 current modulation
and an ac-signal component propor-
tional to wiring resistance: IBRW.
The other side of the LTC1043 syn-
chronously rectifies the IBRW ac com-
ponent, storing the IB1RW5VC1 phase
on C1 and the IB2RW5VC2 phase on C2.
Op amp A2 buffers VC1 and inputs it
to the resistor network and A1, which
subtracts it from the average sensor sig-
nal, producing an output voltage inde-
pendent of cabling-resistance offset.
One downside of the technique is that,
due to sensor-impedance effects on
the order of 20 mV, the thermometric
diode usually requires custom tempera-
ture calibration.EDN

Simple FSK modulator enables age across the resistor is 2VCC/2.

Select the values of R1, R2, and R3
data transmission over low-speed link so that the current pulses have mag-
nitudes proportional to samples of sin
Israel Schleicher, Prescott Valley, AZ 30, 60, and 908, respectively. Setting
all the outputs of IC1 to off produces
VCC the sample of sin(08), and no current
5V
flows through the resistors. Thus, start-
ing with all outputs of IC1 at off and
C4
R4 10 nF consecutively and periodically setting
C1
100 nF
20k GP0, GP1, and GP2 to high and then,
1%
3
� IC
8 R7 R8 in reverse order, setting GP1 and GP0
10k 10k
DATA IN
R5
2A
MCP6002
1 5
� IC high again generates the positive half
2 � 2B 7
20k MCP6002 of a sine wave. Repeating the process
1% 4 6 FSK
1
GP0 GP3
6 �
OUT
but setting the outputs to low generates
2
C3 the negative half of the waveform.
VDD 5 R3 2.2 nF
VSS IC1
49.9k
R6
12k
This scheme produces a sampled
PIC10F200T
3
GP1 GP2
4 1% sine waveform with 12 samples per
R2 C2 cycle. In addition to the desired fre-
57.6k 3.9 nF quency component, f0, this waveform
1%
contains higher-frequency components
R1
at (12k11)f0 and (12k21)f0, k51,2,3,
100k and so forth. The lowpass filter com-
1%
prising IC2B, R7, R8,
C3, and C4 easily fil-
ters out these unde-
Figure 1 This microcontroller-based cir-
sired components of
cuit generates Bell 202-compatible FSK
smaller amplitude.
modulation.
Listing 1, which is
available with the


FSK (frequency-shift keying) is Web version of this
a type of signal modulation for Design Idea at www.
transmitting digital data over an analog edn.com/090611dia,
communication link. An FSK modu- is the assembly-pro-
lator comprises a digitally controlled gram code that im-
sine-wave generator whose frequency Figure 2 The FSK modulator’s output changes fre- plements the Bell 202
edn090514di44451 DIANE
shifts between two predetermined
(PLACED fre-
IN THE 5-28 FOLDER) quency based on a digital input. FSK standard. When
quencies in response to the two logic the control input
levels of the digital data. The circuit outputs GP0, GP1, and GP2 of micro- Data In is high, the output frequency is
in Figure 1 generates a sine wave by controller IC1 produce nonoverlapping 1200 Hz; when the control is low, the
continuously sampling a single sine pulse trains. When you set either out- output frequency is 2200 Hz. The tran-
cycle. The output of IC2A is propor- put high or low, the others are off— sition from one frequency to the other
tional to the currents through R1, R2, that is, at high impedance. When you occurs in a manner that retains phase
and R3. These resistors connect togeth- set an output high, the voltage across continuity. Figure 2 shows the FSK-
er at one end to the inverting input of the resistor that connects to it is VCC/2. modulator output (CH1) in response
IC2A, which is biased at VCC/2. The When you set the output low, the volt- to a modulating signal (CH2).EDN

50 EDN | june 11, 2009

designideas
Create a swept-sine function
in LabView with just one virtual
instrument
Sean McPeak, University of California—San Diego
 Swept sine waves are useful
when you want to test a prod-
uct over a wide frequency range. A
large research project included the re-
quirement to determine wave propaga-
tion in the open ocean. This applica-
tion required the generation of a swept
sine wave to drive an acoustic trans-
ducer. Although many waveform gen-
erators have a built-in function for this
requirement, you must program it your-
self if you want to implement a swept
sine with a multifunction data-acqui-
sition card. You can create a swept-
sine function in National Instruments’
(www.ni.com) LabView with just one
VI (virtual instrument). Using this
function, you can control start and stop
frequencies, sample rate, and the over-
all duration of the sweep (Figure 1).
Figure 1 With just one LabView virtual instrument, you can control start and stop frequencies, sample rate, and the overall
duration of the sweep.
readerS SOLVE DESIGN PROBLEMS
The LabView software calculates
an array of numbers that represent
the swept-sine-wave time series at
each sample point as the frequency
either increases or decreases, depend-
ing on the direction of the sweep. You
must handle the frequency change of
the output on a point-by-point ba-
sis. The basic form of the equation is
Y(I)5V3sin((A3I2)/21B3I), where
Y(I) is the amplitude of the swept sine
wave as a function of the sample point,
I is the integer that steps through the
time series, V is the peak voltage, and
A and B are variables. You define A as
23p(fSTOP2fSTART)/N, and you define
B as 23pfSTART, where N is the number
of samples, fSTART is the normalized start
frequency, and fSTOP is the normalized
stop frequency. To normalize the start
Edited By Martin Rowe
and Fran Granville
D Is Inside
44 Charlieplexing at high duty
cycle
48 Serial port tests digital circuits
51 DAC calibrates 4- to 20-mA
output current
51 Alarm tells you to close the
refrigerator door
ETo see all of EDN's Design
Ideas, visit www.edn.com/design
ideas.
and stop frequencies, you must change
the unit to cycles per sample. You ac-
complish this task by dividing the f1
and f2 frequencies in hertz by the sam-
ple rate. You determine the sample rate
by deciding how smooth of a transition
you want to represent your swept sine
wave. A good rule of thumb is to have
at least 10 samples/cycle at the high-
june 25, 2009 | EDN 43
designideas
est frequency. When setting the sample
rate, you need to take into account the
overall frequency span you are sweep-
ing and the duration of the sweep itself.
It is also helpful to compare the results
and performance of the LabView data-
acquisition-system implementation of
the swept sine wave with those of an
AWG (arbitrary-waveform generator).
You use two methods of comparison.
First, you compare the output of both
the data-acquisition and the AWG
swept sine wave on a spectrum analyz-
er. Second, you run them both through
an audio-amplifier/speaker system and
simply listen to the output. This meth-
od is useful in determining sweep rate,
duration, and stop and start frequen-
cies. This type of comparison is valid
only if the frequencies involved are
in the audible range. The LabView VI
employs simple array manipulation and
uses a “for” loop. The input duration
is in seconds, the sample frequency is
in samples per second, and the start-
ing and ending frequencies are in hertz.
Dividing the sample rate immediately
converts the start and end frequencies
to cycles per sample. A maximum/min-
imum block takes the normalized end-
ing and starting frequencies as its inputs
and uses the maximum output of the
input pair. You use this method to de-
termine whether your design meets the
Charlieplexing at high duty cycle
Luke Sangalli, Digital Designs, Melbourne, Australia

A few articles have re-
cently appeared describ- Table 1 No. of leds and duty cycles
ing novel ways to increase the No. of No. of Charlieplexing Standard multiplexing
number of LEDs a micropro- pins LEDs duty cycle (%) duty cycle (%)/no. of pins on these LEDs. Using this
cessor can drive with a limit- Three Six
ed number of pins (Reference
1). The standard multiplex- Four 12
ing technique made popular by Five 20
multidigit seven-segment dis- Six 30
plays has, in pin-scarce designs,
given way to “Charlieplexing.” Seven 42
Charlie Allen devised this Eight 56
technique while working at Nine 72
Maxim (www.maxim-ic.com),
10 90
which has since introduced
44 EDN | june 25, 2009
Nyquist criteria, given the sample rate
and highest frequency you require.
This approach drives a simple Bool-
ean variable to alert the user about
whether the design meets the Nyquist
criteria. You set the “for” loop to run
for the total number of samples you
want to calculate. You determine this
value by multiplying the duration in
seconds by the sample rate in samples
per second. To guarantee that the loop
processes all of the generated samples,
you must add one, because the loop
stops at N21.
You implement the output function
in the “for” loop with simple algebraic
operators and the sine block. The out-
put is an array that reaches the perim-
eter of the “for” loop. It is important
to enable indexing at this node. This
action allows the circuit to individu-
ally handle each element in the array
at the output of the “for” loop. You can
also add a simple gain stage to set the
peak-to-peak value to whatever point
you want. Finally, you use the “rotate-
1D-array-block” case structure to flip
the array if the ending frequency is
lower than the starting frequency. This
approach handles cases in which you
want a frequency sweep that starts out
in a higher frequency and descends to
a lower frequency.
You can easily modify and expand
ICs using the technique (Reference
2). Allen used the high-impedance
third input state available to most mi-
croprocessors for turning off LEDs in a
33.3 50/five
25 33/seven
20 25/nine
16.6 20/11
14.2 16.6/13
12.5 14.2/15
11.1 12.5/17
10 11.1/19
this simple program. One idea would
be to use the output array, which is
nothing more than the time series
representing a predescribed frequency
sweep, to feed a loop that would drive
a data-acquisition module. The out-
put of the module should accurately
represent the frequency sweep, as long
as the module’s output sample rate is
the same as the sample rate you use for
generating the frequency-sweep time
series. You should then be able to track
the output samples and, when they are
complete, reverse the frequency-sweep
array. You then again feed this new
flipped array to the data-acquisition
module. Depending on the maximum
and minimum frequencies, sweep dura-
tion, and sample rate you use, it may be
difficult to flip the array and configure
the module quickly enough to not miss
a sample. In that case, you can prefill a
frequency-sweep array for a set number
of passes.
These modifications allow the
sweep to continue back and forth for
a set period. Another improvement
would be to add some real-time FFT
(fast-Fourier-transform) capability so
that the user can see the sweep in the
frequency domain. This approach also
adds an increased level of insurance
that the circuit properly meets the
sweep definition.EDN
matrix; the LEDs’ respective
microprocessor pins’ high or
low states individually turn
method, you can drive nine
seven-segment LED displays
using only nine microproces-
sor pins rather than the usual
17. For N pins, you can indi-
vidually address N3(N21)
LEDs using Charlieplexing.
One of the gripes people
often level at Charlieplexing
regards its poor duty cycle. A
previous Design Idea com-
designideas
pares the standard multiplexing meth-
od with Charlieplexing (Reference 3).
Using Charlieplexing, the maximum
duty cycle for a 20-LED display is only
5%. The poor duty-cycle figure is due
not to the method, however, but rath-
er to the driving capability of the mi-
croprocessor and the parasitic-leakage
paths. A single pin cannot usually sink
the current a number of LEDs require
to effectively light up, so these designs
often require one source pin and one
sink pin to light only one LED at any
time. However, adding a transistor or
two resistors allows you to circumvent
these issues.
If you rearrange the LEDs in the fa-
miliar cross-point array and add a tran-
sistor to each column to carry the com-
mon current, you’ll see the duty cycle
of the Charlieplexing method does not
differ much from standard multiplexing
(Figure 1). For a 20-LED, five-column
matrix, each LED remains on for 20% of
the time compared with 25% for stan-
dard multiplexing, but now using only
5V
470
470
470
470
470
Q1 BC337
100
P1
D21
P2
100
D31
100
P3
D41
100
P4
D51
P5
100
Figure 1 Arranging LEDs in a cross-point array and adding a transistor to each
column show that the duty cycle of Charlieplexing is similar to that of standard
multiplexing.
46 EDN | june 25, 2009
edn090305di44191
view, consider that, by the time you get
by the time you get to 90 LEDs, the PCB (printed-circuit-
board) real estate and cost of the addi-
to 90 LEDs, the PCB tional 10 transistor/resistor sets pale in
real estate and comparison to the display itself.
Examining the circuit in detail,
cost of the you’ll notice that it has five micropro-
10 transistor/ cessor pins, P1 through P5, available, for
resistor sets pale a total of N3(N21)520 LEDs. When
P3, for example, is high, the emitter of
in comparison to Q3 is at approximately 4.4V, and you
the display itself. can turn off D13, D23, D43, or D53 if you
make P1, P2, P3, or P5 low. Any pin that
you set to input, or high impedance,
five pins instead of nine (Table 1). alternatively turns off the correspond-
One of the drawbacks of adding the ing LED. When P1 and P4 are low, P3 is
transistor and resistors to each column high, and P2 and P5 are in high-imped-
is that you need additional components ance states. With P3 high, transistor Q3
to achieve a reasonable LED bright- biases on, all the other transistor bases
ness when a large number of LEDs is are either low, which ensures that no
involved. This approach, however, is a current will flow, or high-impedance,
better alternative to using a costly IC which supplies no current into the base
and no worse than standard multiplex- to allow the transistor to conduct. All
ing or “Gugaplexing,” which also re- the diodes in the third column can turn
quires additional transistors and resis- on, but only D13 and D43 have a path
tors. From a cost and benefits point of directly to ground through P1 and P4,
which are low and through the 100V
5V 5V 5V 5V
current-limiting resistors.
D23 and D53 connect to the high-im-
pedance input pins and can conduct
Q5 BC337
only through the 100V resistors at-
Q4 BC337 tempting to turn on Q2 and Q5. Be-
Q3 BC337 cause of their forward-voltage drop—
typically, 2.2V—the emitters of Q2 and
Q2 BC337
Q5 will be less than 1.6V, as the fol-
lowing equation shows: 5VCC20.6V
D12 D13 D14 D15 (Q3)22.2V (D23 or D53)20.6V (Q3 or
Q5)2ILED3100V,1.6V, where ILED is
the current of the LEDs. This scenario
D23 D24 D25 does not allow any LED in Column 2 or
Column 5 to light up to any level that
would have an undesirable effect.EDN
D32 D34 D35
R e fe r e nce s
1 Lancaster, Don, Tech Musings,
D42 D43 D45 August 2001, www.tinaja.com/glib/
muse152.pdf.
2 “Charlieplexing—Reduced Pin-
D52 D53 D54 Count LED Display Multiplexing,” Ap-
plication Note 1880, Maxim, Feb 10,
2003, http://pdfserv.maxim-ic.com/
en/an/AN1880.pdf.
3 Gupta, Saurabh, and Dhananjay V
Gadre, “Multiplexing technique yields
a reduced-pin-count LED display,”
EDN, Oct 16, 2008, pg 68, www.
edn.com/article/CA6602447.
DIANE
designideas
Serial port tests digital circuits the manufacturers’ data sheets. Place
bypass capacitors as close as possible to
the IC’s power and ground. You can re-
Yury Magda, Cherkassy, Ukraine
place the MAX232 with a MAX225 or


A PC’s serial port provides sig-
nal lines that you can use to
read voltage levels of digital circuits.
You can use the port to test digital
TTL (transistor-to-transistor-logic)-
level circuits. You just need to convert
the TTL levels to RS-232 voltages, and
you can add a multiplexer to increase
the number of signals that the serial
will run on the 2005 version, as well.
To create the application, select the
“Windows Form Application” from the
templates in the project wizard. Place
the text-box, label, and button compo-
nents on the project’s main form and
assign titles for them. You should place
the serial-port component on the de-
sign area of the project. Then, set the
MAX233.EDN
R e fe r e nce s
1 “MAX220-MAX249 15V-Powered,
Multichannel RS-232 Drivers/Receiv-
ers,” Maxim, January 2006, http://
datasheets.maxim-ic.com/en/ds/
MAX220-MAX249.pdf.
2 “CD54/74HC4051, CD54/

port can sense. appropriate parameters for the serial- 74HCT4051, CD54/74HC4052,
The circuit in Figure 1 uses a port component, including the port CD74HCT4052, CD54/74HC4053,
MAX232 IC from Maxim (www. number, baud rate, data bits, parity, CD74HCT4053 High-Speed CMOS
maxim-ic.com) to convert RS-232 and stop bits. Logic Analog Multiplexers/Demulti-
voltage levels to TTL levels (Reference When you build the circuit, follow all plexers,” Texas Instruments, 2004,
1). A 74HC4051 from Texas Instru- precautions concerning the MAX232 http://focus.ti.com/lit/ds/symlink/
ments (www.ti.com) lets you select any and 74HC4051 wiring according to cd74hct4053.pdf.
of four digital inputs and route them to
DIGITAL INPUTS
the serial port (Reference 2). Listing
5V A3 A2 A1 A0 5V
1, which is available with the online
version of this Design Idea at www.edn.
com/090625dia, lets you control the 16
RTS (ready-to-send) and DTR (data- 16
13
1 X0
terminal-ready) pins in the serial port 14
X1
that selects the signal under test. The C1 � C3 15
X2
CTS (clear-to-send) pin then reads the 1 �F �1 �F 12
3 2 X3
signal under test into the PC. 1
X4
4 6 5
The four digital-input signals, A0 PC COM PORT C4
X5
X
3
C2 � MAX232 2
through A3, from your device under DB9
1 �F
1 �F 4
X6
� X7
test connect to the first four inputs, X0 1
6
5
2 74HC4051
through X3, of the multiplexer. Only 3
7 RTS 13 12
11
one of those signals can pass through to 4
8 CTS 14 11 S0
9 DTR 8 9 10 S1
the X output, Pin 3, at a time. By set- 5
9 S2
ting the appropriate binary code on the 15 6
E
serial port’s RTS and DTR lines, you 7
VEE
can select the signal to pass through
8
the multiplexer (Table 1).
The PC software, running on Win-
dows XP, sequentially sets those binary
combinations on the port’s RTS and Figure 1 This circuit lets you pass up to four TTL-level signals to an RS-232
DTR lines and reads the digital signal port to read their status.
on the CTS line. The software then
reads the status of the selected bit and
displays it when you press the “check-
status” button (Figure 2). The code is
written in Microsoft C# 2008, but it
edn090305di44201 DIANE
(PLACED IN THE 4-23 FOLDER)
TABLE 1 INPUT SELECTION
Signal to X pin RTS bit DTR bit
A0 0 0
A1 1 0
A2 0 1 Figure 2 A main window of the running application shows that input lines A0—
A3 1 1 A2 have high logic levels and A3 has a low logic level.

48 EDN | june 25, 2009

designideas
DAC calibrates the negative input equal to that on its
positive input. The output current de-
4- to 20-mA output current pends on the value of the sense resis-
tor, the gain of the current-sense am-
Ronald Moradkhan and Steven Lau, plifier, and the control voltage.
Maxim Integrated Products, Sunnyvale, CA The DAC provides the control volt-


Industrial controls make heavy where I OUT is the output current, age that lets you automate the calibra-
use of 4- to 20-mA current loops VCONTROL is the control voltage, RSENSE tion procedure. By selecting the right
to transmit process measurements be- is the sense resistance, and KCSA is the value for the sense resistor and by using
cause current loops retain information gain of the current-sense amplifier— a suitable resistor divider for R1 and R2
in the presence of noise and changes in 20 in this case. The circuit comprises at the output of the DAC, you can ad-
loop voltage. The loop circuit requires IC2, a Maxim (www.maxim-ic.com) just the circuit’s output to 4 mA when
properEquation for 090514
calibration di 4554
to ensure (in 5 − 23
accurate folder) DAC; IC3, a MAX4376T
MAX5304 the DAC’s digital input is zero-scale
readings. The circuit in Figure 1 cali- current-sense amplifier; IC 4 , a and 20 mA when the digital input is
brates the loop by generating a current MAX420 op amp; and Q1, an N-chan- full-scale. Figure 1 shows the compo-
in response to a control voltage: nel IRFL4105 MOSFET. The op amp nent values you need to achieve that
VCONTROL lets the control voltage set the output condition.
I OUT = , current because it forces the voltage on With a zero-scale digital input, the
R ×K
SENSE CSA
DAC output is 0V and the resistor di-
10V vider produces 0.6V at the op amp’s
10V
R3 positive input, forcing the output cur-
15
C4 rent to 4 mA. With a full-scale digital
R4 0.1 �F input, both the DAC output and the
15 midpoint of the resistor divider are at
Q1 the 3V reference voltage, forcing the
C3
0.1 �F RS� RS� R5 IRFL4105
output current to 20 mA. A transfer
2k
VCC IC3 curve relates the output current to the
MAX4376T OUT
0.1 �F control voltage (Figure 2).EDN
LOAD
5V GND
V�
VREF
IC1 3V INPUT�
�
IC4 OUTPUT
IN OUT
MAX420
R1 INPUT�
C1 GND �
10.2k CCXTD
0.1 �F
V� 0.1 �F

VCONTROL CCXTD
R2 0.1 �F
C2 255k
0.1 �F

VDD REF FB
IC2
SPI CONTROL MAX5304 OUT

GND

Figure 2 The circuit in Figure 1

Figure 1 This DAC-controlled 4- to 20-mA transmitter allows digital control produces a linear output current
of the loop current. versus digital control voltage.

Alarm tells you edn090514di44541 DIANE

(PLACED IN THE 5-28 FOLDER)
circuit that this Design Idea describes,
and the gadget still operates with the

to close the refrigerator door original 9V battery. The circuit oper-

ates by sensing a decrease in resistance
Boris Khaykin, TRW Automotive, Livonia, MI of photocell PC1 that results from
light in the refrigerator when its door


The circuit in Figure 1 is a sim- ilar one I recently read about (Refer- is open. A counter is in a reset state
pler and safer device than a sim- ence 1). A few years ago, I built the when PC1 is in the dark, and its resis-

june 25, 2009 | EDN 51

designideas
tance is greater than 30 kV. Usually, resistance is lower than 15 kV—that is, state is approximately 2.5 mA.
the dark resistance is greater than 200 when the light bulb in the refrigerator You can use almost any photocell,
kV, and current consumption at this is on. Then, in 20 seconds, it turns on such as the Jameco (www.jameco.
state is less than 40 mA. Oscillator- a buzzer for 20 seconds or until some- com) 202403 CDS0018001 with 200-
counter IC1 starts counting when PC1’s one closes the door. The current at this kV dark and 3-kV light resistance.
This circuit uses a Ra-
dioShack (www.radioshack.
16
com) 273-074 buzzer. You
can use any similar piezo-
VDD D1 electric buzzer with an op-
9 1N914
OUT2 2 erating dc voltage of 1.5 to
Q13
C1 R2 � 15V. V1 can be as low as 3V.
� 270k BUZZER
R1 10 nF 10
OUT1
The trade-off is that using a
V1 20k IC1
9V
voltage this low gives you
4060
�
11 longer battery life but lower
CLK
volume of sound.EDN
5
12 Q5 R e fe r e nce
RES
VSS 1 Babu, TA, “Alarm
PC1 8 Sounds When Refrigerator
Door Remains Open Too
Long,” Electronic Design,
March 26, 2009, pg 46,
Figure 1 This gadget, placed inside a refrigerator, sounds an alarm when the refrigerator http://electronicdesign.
door is open for more than 20 seconds. com/Articles/ArticleID/
20806/20806.html.

edn090611di45191 DIANE
(PLACED IN THE 6-25 FOLDER)

52 EDN | june 25, 2009

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Illumination ring provides

D Is Inside
focused intensities 43 Digital variable resistor com-
William Grill, Honeywell Aerospace, Olathe, KS pensates voltage regulator


If you use a camera-based in-
spection or soldering fixture,
you need to see images in a small area.
Often, side lighting produces shadows
on an image that result in contrasting
colors and poor quality. Thus, your mon-
itor views may be difficult to clearly see
or interpret. Centering a light ring on
the image provides illumination on all
sides of the object and may illuminate
everything you need to see. In a camera
application for controlling a light ring,
this implementation not only controls
the light, but also enables you to direct
the light intensity by maintaining two
levels of control. It also lets you main-
tain and rotate the second-tier levels
about the illuminated object.
Based on a seven-LED set, you se-
lect three consecutive LEDs; the sec-
ond-tier settings will define the three
LEDs’ intensities (Figure 1). The re-
maining displays are maintained at a
base-tier-intensity setting. Using four
pushbutton switches, the Microchip
(www.microchip.com) 16F505 rotates,
distributes, and provides PWM (pulse-
width-modulation) control of these
two power tiers across the seven LEDs.
Two of the buttons increase or decrease
intensity, or they group or ungroup the
tier-intensity settings; the other two
buttons rotate the resulting second-tier
display clockwise or counterclockwise.
The implementation uses just a few
parts, exploiting the controller to pro-
44 Hot-swap switch provides
easy thermal protection
47 Add headphones to a Class D
amplifier
50 Circuit eases power-sequence
testing
ETo see all of EDN's Design
Ideas, visit www.edn.com/
designideas.
vide light level, state maintenance,
and PWM control. The application
debounces the buttons and indexes
the intensity controls. An eighth LED
indicates tier-grouped or -ungrouped

5V

1 200
10k 10k
10 200
9
200
2 8 470
D OPTICAL- MODE
3 7 ILLUMINATION
200
C 4 PIC16F505 6 RING
B 11 5
A 13 200
GREEN
12 200 LED
200

14
WHITE LEDs
LTW-2S3D7

Figure 1 An LED illumination ring provides directed light intensity.

edn090205di44221 DIANE
(PLACED IN THE 4-23 FOLDER)

42 EDN | july 9, 2009

mode. When you group the tiers to-
gether, their intensity-setting index-
ing is common, but their register limits
remain independent. You can down-
load Listing 1, the assembly code for
the circuit, from the online version
of this Design Idea at www.edn.com/
090709dia.
The controller provides a PWM pe-
riod of approximately 7.5 msec to all
the LEDs. It also controls each LED’s
duty cycle, according to the registered
levels the button sets, in defined and
maintained register masks and inten-
sity values. The controller provides
six bits of intensity, corresponding to
64 levels of resolution, although 8-bit
resolution is available. The operating
voltage is 5V. You can reconfigure the
controller, the display, and their limit-
ing resistors to operate at voltages as
low as approximately 3.1V. High-mil-
licandle, white, 5-mm, T1¾ through-
hole LEDs provide the light source.
The controller provides about 8 mA
of current to each of the LEDs. By
constraining the total power, surface-
mount or other LED configurations
are possible.
You can lay out the four momentary-
action pushbutton switches for opera-
tion by the left or the right hand. With
one representing the pushbuttons’ as-
serted position, the controller’s coded
sequences provide the button-control
functions found in Table 1.EDN

TABLE 1 PUSHBUTTON-CONTROL FUNCTIONS

A B C D
1 1 No function 1 1 Alternate between common-tier mode and second-tier
mode
1 0 Select second-tier mode, rotate 1 0 Increment all or second tier if in second-tier mode with
Tier 2 LEDs counterclockwise autoindexing
0 1 Select second-tier mode, rotate 0 1 Decrement all or second tier if in second-tier mode with
Tier 2 LEDs clockwise autoindexing
0 0 No function 0 0 No function

Digital variable resistor compensates nominal in this circuit. These num-

voltage regulator bers are respectable, but you can im-
prove them. First, incorporate a digi-
Jason Andrews, Maxim Integrated Products Inc, Dallas, TX tally controlled variable resistor, such
as a DS1859, into the regulator circuit


A variable resistor that inte- ther a preset 3.3V or any user-defined of Figure 1 by placing it in parallel
grates a programmable, tem- output within its operating range. with R2 (Figure 2). A temperature-
perature-indexed look-up table can For most regulator circuits, the out- indexed look-up table in an internal
compensate for the temperature drift put voltage varies slightly with tem- nonvolatile memory controls the 50-
of a voltage regulator. In this case, the perature, from 97.6 to 101.5% of kV digital resistor, allowing you to
look-up table can change program a different re-
the resistance every 28C VCC sistance value for each
over a range of 240 to 28C window.
11028C, thereby null- You can program the
ing any regulator-output look-up table to pro-
changes that would oth- IN OUT LOAD� vide any resistance-ver-
erwise occur because of sus-temperature profile.
C2 �
temperature. A typical 10 �F GND GND In this example, the
MAX604 R1
regulator circuit compris- look-up table flattens
GND GND �C
es a regulating element, a 3 the regulator’s normal
10 �F
feedback-resistor divider, OFF SET
curve over tempera-
and capacitors to provide ture. These look-up ta-
filtering and regulation R2 bles, therefore, provide
against transients and a positive resistance
load-switching conditions LOAD� slope with respect to
(Figure 1). The ratio of temperature. The resis-
the two feedback-divider tor has 256 programma-
resistors sets the regula- Figure 1 A typical voltage regulator lets you set the regulated ble resistance settings
tor-output voltage. The output level by adjusting the R1/R2 divider. of 0 to 255 decimal,
regulator can generate ei- and each one accounts

july 9, 2009 | EDN 43

designideas
VCC

VCC
4.7k 4.7k
DS1859
SDA VCC IN OUT LOAD�
SCL H1 �
C1 C2
OUT1 L1 0.1 �F 10 �F GND GND
MAX604 R1
IN1 H0
GND GND �C
OUT2 L0 3
10 �F
IN2 MON3 OFF SET
WPEN MON2
GND MON1 R2

LOAD�

Figure 2 Connecting one-half of a dual variable resistor in parallel with R2 to the circuit in Figure 1 lets you temperature-
compensate the regulated output voltage.

for approximately 192V. In this ex-

ample, the look-up table was pro- 3.4
grammed with a setting of 143 deci-
mal at 2408C. The settings were in- 3.38
UNCOMPENSATED
cremented by one for every 4 to 68C 3.36
change in temperature, resulting in a
value of 152 decimal for ambient and 3.34
158 decimal for 1858C. OUTPUT
As illustrated in Figure 3, the re- 3.32
VOLTAGE edn090514di44702 DIANE
sult of this regulated perform­ance over (V) (PLACED IN THE 5-28 FOLDER)
3.3
temperature is a drastic increase in
COMPENSATED USING DS1859
precision: The variation from 245 to 3.28
1858C is now only 62 mV. For com-
parison, note the response of the stan- 3.26
dard regulator circuit in Figure 1 (the
black curve). The digital-resistor IC 3.24
�45 �35 �25 �15 �5 5 15 25 35 45 55 65 75 85
of Figure 2 includes three ADC in-
puts for monitoring external voltages. TEMPERATURE (�C)
An alternative, the DS1847 dual vari-
able resistor, offers similar performance Figure 3 These curves compare regulated outputs versus temperature for the
without the ADC monitors and at Figure 1 circuit (black) and the compensated Figure 2 circuit (pink).
lower cost.EDN

Hot-swap switch provides necting system power when a temper-

ature exceeds a safe limit. The circuit
easy thermal protection in Figure 1 uses a hot-swap switch to
monitor overvoltage, undervoltage,
Donald Schelle, National Semiconductor Corp, Santa Clara, CA
and overcurrent conditions. When the


It is often difficult to design
an effective thermal-manage-
ment scheme that minimizes the risk
of meltdown or fire. System orienta-
tion, placement, or both complicate
matters by generating hot spots at
varying locations on a PCB (print-
ed-circuit board). A hot-swap switch
and carefully placed temperature sen-
sors mitigate thermal issues by discon-
ambient temperature exceeds a preset
threshold, a carefully placed tempera-
ture sensor, IC1, forces the hot-swap
controller, IC2, to disconnect system
power. You can use multiple tempera-

44 EDN | july 9, 2009

designideas
Q1
5V DC SI7850 PROTECTED
IN FROM 5V
AC/DC C2 RSENSE CL OUT TO
ADAPTER CIN
0.1 �F 0.01 100 �F SYSTEM
10 �F R1
10k 1% VPGOOD
1%
2 1 10 9
4 IC1 5 RPG
V� OS VIN SENSE GATE OUT
LM26 3 100k
C1 1 UVLO 1%
0.1 �F HYST R2 8 TO �C POWER-
VTEMP 3 PGD
2.15k GOOD INPUT
2
GND 1%
4 IC2
OVLO PWR 7
LM25069
R3 RPWR
2.87k 31.6k
1% 5 1%
GND
4 ICN 5 6
V� OS
CN LM26
1 TIMER
0.1 �F HYST CT
VTEMP 3 0.47 �F
2
GND

Figure 1 Carefully placed low-cost temperature sensors disconnect system power when an overtemperature thermal event
occurs.

ture switches to isolate hot spots when

you mount the system in varying ori-
entations. The circuit requires neither
a microcontroller nor a costly temper-
ature-monitoring IC. Thermal events
cut power to the system using a robust, edn090514di44811 DIANE
nondestructive technique. (PLACED IN THE 5-28 FOLDER)
In a typical overtemperature condi-
tion (Figure 2), a thermal event (upper
trace) causes the LM26 to trip, forcing
the LM25069 to disconnect power
from the system (middle and lower
traces). When the system temperature
decreases below the LM26’s trip point,
system power returns. Incorrect place-
ment or orientation can cause over-
temperature events, forcing the system
to turn on and off like clockwork; sup-
port personnel can easily diagnose this
symptom. Inexpensive temperature
sensors and an innovative power-lim- Figure 2 As the temperature rises above the threshold (top trace), the output of
iting hot-swap controller reduce the the temperature sensor (middle trace) goes low, forcing the hot-swap switch to
cost of this circuit to approximately $2 disconnect power (bottom trace) from the circuit.
in low-volume applications.EDN

Add headphones to a Class D amplifier outputs on each channel. If the ampli-

fier drives separate speakers, you can
Hiroshi Fukushima, Technical Research Center, use an attenuator circuit (Figure 1). A
D&M Holdings Inc, Kawasaki City, Kanagawa, Japan problem arises, however, with ground-


The MAX9704 from Maxim
(www.maxim-ic.com) is a small
and efficient Class D audio power am-
plifier. Its fully balanced inputs and
Class D outputs make it a convenient
chip to directly drive speakers. Some-
times, though, you want to have a
headphone output to keep the office
environment. Class D power amplifi-
ers usually have fully balanced, bridged
ed headphones: Stereo headphones use
three-pole plugs with which the nega-
tive side of each speaker connects to a
common ground. Thus, you may think
that you can’t directly connect head-

july 9, 2009 | EDN 47

designideas

�
R5 LEFT
� �
LEFT �
LEFT R3 SPEAKER
R2 R3 R2 R5
� �

R4 HEAD-

�
� �
LEFT RIGHT PHONES
� �
RIGHT
RIGHT R6 SPEAKER
R1
R4 R1 R6
� �
�
RIGHT
�
Figure 1 A Class D amplifier has separate
drivers for each speaker.
Figure 3 This speaker configuration lets you connect headphones
with a common ground to a Class D amplifier.
edn090611di45061 DIANE
(PLACED IN THE 6-11 FOLDER) phones to a Class D amplifier without nel’s drivers. Resistors R3 and R2 con-
OUTL� using a transformer. nect to the left output terminal. Re-
To solve the problem, look at the sistors R4 and R1 connect to the right
OUTL� output waveform of the MAX9704 output terminal. The inactive chan-
as it swings (Figure 2). Each channel nel’s output
edn090611di45063 DIANE voltage must be the same
output alternates between high andIN THE
(PLACED voltage, which means that R4, R1, and
6-1 FOLDER)

OUTR�
low. You can take advantage of the R6 connect to the same voltage when
fact that the channels aren’t on at the the left-channel output is active. R3,
same time by configuring your circuit R1, and R5 connect to the same volt-
OUTR� like the one in Figure 3. age when the right-channel output is
Figure 4 shows the circuit details. active. The values of R1 and R2 affect
Figure 2 The MAX9704 applies Because the MAX9704 alternates the how much crosstalk you get between
power to one channel at a time. outputs of each channel, the R3/R6 channels. The values in Figure 4 pro-
combination doesn’t affect the chan- vide sufficient channel separation.EDN

0.47 �F J1
10 32
LEFT STEREO INPUT INL� OUTL�
9
edn090611di45062 DIANE INL� OUTL� 31 LEFT
0.47 �F
(PLACED IN THE 6-11 FOLDER) 16 30 SPEAKER
RIGHT STEREO INPUT INR� OUTL�
15 29
INR� OUTL�
0.47 �F 0.47 �F IC1
MAX9704 J2
28
OUTR�
27
OUTR� RIGHT
AGND
26 SPEAKER
OUTR�
25
OUTR�

R1 R2 R3 R4 R5 R6 J3
100 100 470 470 470 470

HEADPHONES
T

Figure 4 With the resistors in place, you can connect headphones to the MAX9704 amplifier.

48 EDN | july 9, 2009

designideas
Circuit eases power-sequence testing C3 is 33 mF and R3 is 11 kV for a
400-msec delay between powering the
Goh Ban Hok, Infineon Technologies Asia Pacific Ltd, Singapore two supplies. The timer triggers with a


Systems on chip (SOCs) nor-
mally require one power supply
for the core and another for I/O. To
properly apply power to the device, you
often need one supply to apply power
before the other. The circuit in Figure
1 lets you test the power sequencing of
the SOC. Two TPS75501 linear regu-
lators, IC3 and IC4, generate two power
supplies. The TPS75501 adjustable reg-
ulator provides output voltages of 1.22
to 5V from a maximum input of 6V.
The circuit uses 5V as the input source,
and it can supply as much as 5A. The
SOC requires 3.3 and 1.5V. The fol-
lowing equations describe how to set
the voltages. VOUT15VREF (11R4/R5)
for IC3, and VOUT25VREF(11R6/R7) for
IC4. The reference voltage is 1.22V.
In the circuit, R5 and R7 are 30 kV.
Variable resistor R4 is 7 kV for the 1.5V
supply, and R6 is 50 kV for the 3.3V
supply. Green LED D2 lights when the
3.3V supply is present, and red LED
D1 lights for the input-supply voltage.
Pin 1 of the TPS75501 is the enable
pin. When low, it enables the output
voltage at Pin 4. Switch S2 selects the
sequence of the power supplies. IC1 is
a 555 timer operating as a monostable
circuit. It provides the delay between
the two power supplies. You can adjust
the delay by using the time constant of
R3 and C3: Delay51.13R3C3.
negative pulse at Pin 2 of IC1. It pro-
duces a positive pulse at Pin 3 of IC1.
The output becomes inverted at IC2A
before passing to IC6’s Pin 11. IC5 and
IC6 are the latched circuits. The set
pin, S, connects to the 5V supply, and
the reset pin, R, connects through re-
sistors R2 and R10 and capacitors C4 and
C7 to ensure that the Q output is high
during the initial power-up stage. Reg-
ulators IC3 and IC4 are initially off.
When analog switch S2 is in the on
position, the sequence of the 1.5V
power supply starts first, and the 3.3V
supply follows. To start the power-se-
quence testing, press and release trig-
ger switch S1 to momentarily produce

IC2B
3 4
74LSU4N
�

VIN VOUT1
5V 1.5V
VIN 2 R4
IC2A 4 5 5 10k
1 2 S 1 IC3
74LS04 4 1 3 D1
R1 R2 3 C IC EN TPS75501 V
� 13 RED
10k 40k 2 5 OUT 2
D 7474N 6 GND 3 1.5V
12
1 11 C5 R5
1 R 30k R8
2 R3 47 �F
2 TR 16
Q 3 10k
15 1k
C4 14
4 IC1 7 0.01 �F VOUT2
R DIS R10 10 9 S2
2 LM555N S 3.3V
5 6 3 10k 11 VIN 2 R6
S1 4 CV THR C IC
6 1 IC4 5 50k
DT6 1 GND 12 1 3
C2 C1 V+ 8 D 7474N 8 MABSA 4
0.01 �F 0.01 �F C3 C7 13 EN TPS75501 2
D2
R V GREEN
33 �F 0.01 �F GND 3 3.3V OUT
C6 R9
R7
47 �F
30k

Figure 1 A configurable sequencing circuit uses a 555 timer to delay one power supply.

edn090514di44861 DIANE
(PLACED IN THE 6-11 FOLDER)

Figure 2 The 1.5V power supply (green trace) comes Figure 3 The 1.5V power supply (green trace) comes on
on first, and the 3.3V supply (red trace) and 555 timer first, and the 3.3V supply (red trace) and 7474 latch-cir-
follow. cuit input follow.

50 EDN | july 9, 2009

designideas
a low pulse. This pulse triggers the
555 timer, IC1, which produces a pos-
itive pulse. This pulse in turn produc-
es a delay before enabling IC4’s power
3.3V supply. When you press and re-
lease S1, another signal goes to invert-
er IC2B before passing to the latch pin,
Pin 3 of IC5. There is no delay for the
1.5V regulator that connects to this
pin. It enables IC3’s 1.5V power sup-
ply. Because IC3’s enable pin imme-
diately receives the enable signal, it
produces the 1.5V without delay. IC4’s
enable pin, which receives a signal af-
ter the delay by the 555 timer, later
produces the 3.3V, thus achieving
the power sequence. The 1.5V power
supply comes first when you press S1,
and the 3.3V power supply comes on
only after the 555
timer delay (figures 2 and 3).
Switch S2 connects to pins 13 and
16. When S2 is off, the power sequence
changes. In this case, the 3.3V supply
powers up first, and the 1.5V supply
follows (figures 4 and 5). When you
press S1, the 3.3V power supply comes
first, and the 1.5V supply follows after
the 555 timer delay.EDN

Figure 5 The 3.3V power supply (red trace) comes on

Figure 4 The 3.3V power supply (red trace) comes on first, first, and the 1.5V supply (green trace) and 7474 latch-
and the1.5V supply (green trace) and 555 timer follow. circuit input follow.

52 EDN | july 9, 2009

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Quasiresonant flyback converter easily

D Is Inside
charges energy-storage capacitors 42 First-event detector has
Todor Arsenov, Toronto, ON, Canada automatic-reset function


Designers often use chargers
with flyback topologies to
quickly charge energy-storage capaci-
tors (references 1 and 2). In a flyback
topology, the energy transfer takes
place only when the charger’s power
MOSFET is off, which effectively iso-
lates the power switch from the load,
comprising high-energy storage-ca-
pacitor banks. Thus, the voltage levels
on the circuit transformer’s secondary
can vary from zero to a predetermined
value and corresponding energy level
without any significant stress on the
components on the primary side of the
The classical flyback capacitor char- 43 Signal-powered linear
ger operates in CCM (continuous-con- optocoupler provides isolated
duction mode). Flat-topped, short-du- control signal
ration current pulses on the transform- 45 Dark-activated switch needs
er’s secondary charge the storage ca- only threeforcomponents
pacitors (Reference 3). Unfortunately, Equations DI4484 (in 5 − 23 folder )
this charging strategy requires complex ETo see all of EDN's Design
control circuitry to limit both the sec- Ideas, visit www.edn.com/
ondary current and the capacitor volt- designideas.
Equation 1
age. Most circuits use a specialized
PWM (pulse-width-modulation)-con-
troller IC, which increases the overall 1
cost of the charger. Another disadvan- ∆W = × (L P × I2P L P × I2P ),
2 PK OFFSET
tage of the CCM is the small portion
of energy that accumulates during the where IP2 signifies the initial non-
OFFSET

transformer. on-time of MOSFET conduction: zero primary current at the beginning

Equation 2
OPTIONAL RESISTOR-
CAPACITOR-DIODE
D1
SNUBBER
1
STTH512
380V DC ∆W = × L P × I2P . 400V
2 PK
C1 � � C2
R1 C3 T1 2000 �F
2000 �F
D3

15V
� �
C4 C5
R3
2000 �F 2000 �F
C8 � 56k
22 �F 1
450V R4 INV IC1 VCC 8 �400V
13k R5 R6 D4
L6565
51k 10 STTH512
2 7
COMP GD
Q1
3 6 STP4N150N
VFF GND
R7 4 CS 5
C6 ZCD
51k
330 nF R8
R9 1k
10k
R10
C7 0.5
470 pF 1W

Figure 1 A flyback capacitor charger uses BCM operation.

40 EDN | july 23, 2009

of the on-time interval.
Equations for DI4484 (in 5 − 23 folder )
Only this limited portion of ener-
gy transfers from the primary to the
secondary sides and enters the stor-
Equation
age capacitor. 1
Therefore, you can
considerably increase the amount of
energy transferable to the capacitive
load if the 1
converter
∆W = × (L Pcan
× I2Poperate
L P × Iin
2
POFFSET
),
BCM (boundary-conduction
2 PK mode).

The secondary current becomes zero,

the power MOSFET turns on, and
the primary current builds from zero.
Thus, a bigger portion
Equation 2 of energy ac-
cumulates during every consecutive
on-time interval:
1
∆W = × L P × I2P .
2 PK

With all other conditions equal,

BCM operation ensures faster accu-
mulation of a predetermined amount
of energy because of the bigger stored Figure 2 When the secondary current reaches 0A, the MOSFET turns on, and
portions of energy during the on-time the primary current increases from 0A.
intervals. Many converter circuits
that operate using BCM incorporate
PWM controllers that implement
BCM operation for capacitor charg-
ing. These circuits often use Maxim
(www.maxim-ic.com) MAX8622 or
Linear Technology (www.linear.com)
LT3468 ICs. These ICs are special-
ized devices to accommodate BCM
operation.
You can, however, implement fly-
back BCM operation without these
specialized parts. Manufacturers imple-
ment BCM in the variable-frequency
versions of flyback converters, which
are quasiresonant, ZVS (zero-voltage-
switching) converters that commonly
find use in TV SMPS (switched-mode-
power supplies). For example, you can
use the STMicroelectronics (www.
st.com) quasiresonant-SMPS-control-
ler L6565 to build a flyback capacitor
charger working in BCM (Reference
Figure 3 The output-capacitor voltage reaches its full level in about 3 seconds.
4). Doing so eliminates the need for
using a specialized chip for capacitor
chargers. Q1. When the circuit interrupts the duces the charging time of the storage
Figure 1 shows the power stage of a secondary current—indicating full de- capacitors.
charger using the ST L6565. It achieves magnetization of T1—it detects the At the beginning of the charging
the BCM using a second primary wind- minimum of the first valley of ringing, sequence, the output voltage is low
ing on T1 that feeds the transformer- and the L6565 turns on the MOSFET. because of the large capacitance val-
sensing input at the ZCD pin of the This action eliminates the idling and ues. The secondary current decreases
L6565. The voltage of this winding zero-phase-time intervals, thus estab- slowly. The reflected voltage on the pri­
is a scaled-down replica of the drain- lishing BCM. The elimination of the mary side is too low to trigger the ZCD
to-source voltage of power MOSFET zero-phase-time intervals greatly re- pin of the L6565. Thus, the L6565’s

july 23, 2009 | EDN 41

designideas
initial starting timer sets the switch-
ing frequency to 2.5 kHz at the start
of charging. The output voltage across
the storage capacitors increases to a
point at which the switching frequen-
cy becomes variable because of the de-
magnetization of the transformer core.
Figure 2 shows that, as soon as the sec-
ondary current (Channel 2) becomes
0A, the power MOSFET turns on, and
the drain-to-source voltage decreases
(Channel 1). At that time, the pri-
mary current again increases (Channel
4). At the output voltage close to full
charge, the switching frequency is ap-
proximately 100 kHz. Figure 3 shows
the total voltage of 750V across C1, C2,
C4, and C5 within a 3-second charging
time.
The waveforms in figures 2 and
First-event detector has
automatic-reset function
Vasil Borodai, Zaporozhje, Ukraine

The circuit in Figure 1 lets you
indicate which game player
presses a button first. Each button has
a corresponding LED that indicates
the pressing of the button. All other
LEDs remain locked out until some-
one presses a reset button. When a
player presses a pushbutton, the corre-
sponding optoisolator turns on, which
illuminates the appropriate indicator
VPS
9V
R1
1.5k
A 2
RESET S1 S2 LED1
PLAYER 1 PLAYER 2
D1
3.9V
R2
5k
Figure 1 This circuit lets you indicate which game player presses a button first.
42 EDN | july 23, 2009
3 are evaluation measurements of
a prototype capacitive charger us-
ing the L6565 and power MOSFET
STP4N150. A low-power PFC (pow-
er-factor-correction) stage, using tran-
sition-mode-PFC controller L6562,
delivers the input-bus voltage of
380V dc. This configuration ensures
not only the dc-voltage bus for the
power stage of the charger, but also a
high power factor during the charging
phase.EDN
R e fe r e nce s
1 Lan, Rayleigh, and Hunter Chen,
“Flyback Charge Xenon Flash Capac-
itors,” Power Electronics Technology,
March 2007, http://powerelectronics.
com/mag/703PET24.pdf.
2 Creel, Kirby, “Expedite Transformer
LED. The LED remains on after the
player releases the pushbutton. The
voltage at Point A pulls down to near-
ly 3.7V, which you determine by add-
ing the forward voltage of the optoiso-
lator’s internal LED, the phototrans-
istor’s voltage, and the LED’s voltage:
1.310.611.8V53.7V. The green LED
then turns off.
Beginning at time T1 (Figure 2),
S3 LED2 SN+1 LEDN
PLAYER N
Calculations for Flybacks,” Power
Electronics Technology, January
2008, http://powerelectronics.com/
passive_components_packaging_
interconnects/magnetics/transformer-
calculations-defibrillator-capacitors-
0108.
3 Sokal, NO, and R Redl, “Control
algorithms and circuit designs for op-
timally flyback-charging of an energy
storage capacitor (e.g., for flash lamp
or defibrillator), IEEE Transactions on
Power Electronics, Volume 12, Issue
5, September 1997, http://ieeexplore.
ieee.org/xpl/freeabs_all.jsp?tp5&ar
number5623007&isnumber513547.
4 “L6565 Quasi-Resonant SMPS
Controller,” STMicroelectronics,
http://eu.st.com/stonline/products/
literature/ds/7587/l6565.pdf.
no other player can change the situa-
tion by pressing a pushbutton because
switching on any other optoisola-
tor requires a voltage exceeding 3.9V.
Resistor R1 depends on VPS such that
R15(VPS2VD1)/IOPTOLED, where VPS is
the power-supply voltage, VD1 is the
voltage of diode D1, and IOPTOLED is the
current of the optoisolator LED. Thus,
for a 9V power supply, R1 has a value of
1.5 kV. When a player presses the reset
button, the player LEDs turn off, and
the green LED illuminates. The volt-
age at Point A returns to 9.2V (time
T2 in Figure 2).
IC1 R3 � C
300k 14 2
3 5 6.8 �F
1 4
6
D2 R4 7 IC1
1.5k CD4093B
C1 �
100 �F
GREEN
LED
 VPS VPS
9.7V 9.7V
VA
9.2V

6.2V

VC1
VA
3.7V

0 0
T1 T2 TIME T1 T2 TIME
PLAYER N RESET PLAYER N AUTO
PRESSED PRESSED PRESSED RESET

Figure 2 When a player presses the reset button, the Figure 3 When Point A drops to 3.7V, the inputs at IC1,
player LEDs turn off, and the green LED illuminates. The pins 1 and 2, go low, and the output at Pin 3 goes high,
voltage at Point A returns to 9.2V. charging C1.

You can also add an auto-reset feature ure 3), C1 has enough voltage to force rent in any optoisolator LED. As a re-
edn090611di44522
to the circuit. When Point A drops to DIANEIC ’s Pin 4 low. R and C determine sult, the circuit
edn090611di44523 automatically resets,
DIANE
(PLACED IN THE 6-25 FOLDER) 1 3 1
(PLACED IN THE 6-25 FOLDER)
3.7V (time T1 in Figure 3), the inputs the charging time. A pulse of current and the green LED lights. IC1’s Pin 3
at IC1, pins 1 and 2, go low, and the flows through C2, which forces the goes low, which discharges C2 through
output at Pin 3 goes high, charging C1. voltage at Point A to nearly 2V. That R2, resetting the circuit to its original
After about 30 seconds (time T2 in Fig- action momentarily interrupts the cur- state.EDN

Signal-powered linear optocoupler photodiode. A feedback loop around

provides isolated control signal the emitting side of the optocoupler

keeps the feedback current in propor-
Mitja Rihtarsic, Škofja Loka, Slovenia tion to the transmitted signal. When
the feedforward current and the feed-


The circuit in Figure 1 pro- rent IFF, is the output current, and you back current are equal, the output cur-
vides an isolated control volt- must set this current in proportion rent is proportional to the transmitted
age, such as 0 to 10V. In the low part to the transmitted signal voltage, V1. signal.
of the range, 0V to approximately 2V, This current equals the feedback cur- The hidden cost, however, is a power
the controlled device is off. There- rent, IFB, through the transmitter-side supply. You need some power on both
fore, the upper part of the range must
be as linear as possible. You can meet VC
this requirement using a linear opto-
coupler, such as Vishay’s (www.vishay. R2 IFF
com) IL300 or Avago Technologies’ IR1 220
6 R4
(www.avagotech.com) HCNR200 or R1
�2 IC1
18k
IL300 VBE3
HCNR201. 150k
Q2 5
These optocouplers each comprise V1 IB3
�1 K2
IB1 BC857 Q3
an LED and a photodiode on the trans- A V2
Q1
mitting side and an identical photodi- IFB VBE1 BC847 2 R3 �3 BC857
3
ode on the receiving side. Because of C1 IC1 K1 IC1 150k
IL300
this construction, the emitted light 10 nF IL300 4 1
from the LED should cause the same ILED

current to flow in both photodiodes.

The current through the photodiode Figure 1 Optocoupler IC1 isolates the control circuit’s input and output.
on the receiving side, feedforward cur-

july 23, 2009 | EDN 43

edn090611di44711 DIANE
(PLACED IN THE 6-25 FOLDER)
 I 1 K2
K 2I FF =FF
=Equation(V1.V2BE1) × × ; K 2β1β2 >> 1. 1 K2

designideas
I FB I R1 K1 I FF = (V1VBE1) × × ; K 2β1β2 >> 1
K1 = , LED Equation 7 R 1 K1
I FF Equation I LED1 K
K2 = . K3 = 2 .
I LED K1
I FF
K2 = 3 7 .
Equation
Equation
I FB 2 I LED K Equation 7
KEquation
1= , K3 = 2 .
Equation 3 I LED K1
Equation 8
V1VBEK1 2
= =. I 3 + I .
KEquation K
I R3 K1 FB B1 K3 = 2 .
K 2 = FF
Equation 2 1.
Equation 8 K1
V1VBE1 I V2 = (I FF + I B 3) × R 3 + VBE 3 .
= I FB + I B1.LED
R1
V1VBE1
K 2 = Equa
I FF Equation
. tion
8 = I FB + I B1.
R4 V2 = (I FF + I B 3) × R 3 +Equation VBE 3 . 8
I LED 3 1
Equation Equation 9
Equation 4
I LEDV2 == β(I1FF β2 + × I B13.) × R 3 + VBE 3 .
Equation Equation 4 Equation 9 V2 = (I FF + I B 3) × R 3 + VBE 3 .
V1VBE31  
= I FB + I B1. 1
I LED = β1β2 × I B1. R1 I FF =  (V1VBE1) × I B1  × K 3 .
 R 1 
V1VBEEquation Equation 5β9β × I .
1 =IILED+ = 1 2 B1  Equation  9
FB I B1 . 1
R1 I =  (V1VBE1) × I B1  × K 3 .
Equation 5 Equation 4 Figure 3 AnFF XY plot of the circuit’s R1 inputand output

Figure 2 The output voltage (upper trace) turns off when voltages shows linearity once Equation
the 10 is high
input voltage
Equations for DI 4471 ( Saved int o the June 25 
folder ) 1 1 K 2β1β2
the input voltage (lower trace) gets too low. I Equation
= (
I = (V  V  V 5 ) ×
V ) ×to power
enough × I 1the .
× circuit.
K .  1 
EquationFF4FF 1 1BE1 BE1R1 RK1β1B β2 + 1 3 I FF =  (V1VBE1) × I B1  × K 3 .
Equations for DI 4471 ( Saved int o the June 25  )
folder 1 R
Equations Equations for DIo4471 (Saved int o I LED the 1June= β1βK 25×βfolder
I Bβ12. ) Equation 10  1 
sidesforofDI
the4471 signal (Saved
path. int theI June
The circuit FF =in (V25 1
folder
VBE1))×
When × 2 2 1of
the product feedback
. gain K1 R3  R3 
Equation
this DesignEquations
Idea uses power 1 R K β β + 1 V = V K + V
3  BE 3 V K3  + R
for DIfrom 4471 signal (Saved and int oItransistor gains b and ) V b2)is× much
1 1 1 2 1 K 2β1β2 2 1  BE1
the =June
LED β1β2I× 25IB=1folder
. (V1  × . R 1  R 1 
voltage VEquation
to supply1 a feedback loop in greater than Equation
one, FF you
Equation 6 110 canBE cancel
1
R1outK1β1β2 + 1
1
Equation 1 Equation 5gains, yielding a char- R3  EquationR10 
Equation the1transmitting side similar to the way the transistors’
V2 = V1 K 3 +  VBE 3VBE1 3 K 3  + R 3(I B 3I B1K 3).
some circuits in aIF4-B to 20-mA loop Equation 6 Equation
get acteristic that5 is linear: R1 R1
K Equation
= loop 1,forcurrent.   (10)
power from 1 the
Equations DI4471 Both (Saved int o the June 25 folder) 1 K Equation 11
I
I FLED I Equation
= ( V  VR 3 6 ) ×  × 2 ; K β R
β 3 >> 1.
I photodiodesK1K=operate BI FB, in reverse-biased, FFV = V 1 BE1K1 + KV β β V 2 1 2 K 3  + R 3(I B 3I BR1K ).  R 
K1 = Fphotoconductive
B , 1 I=LED , I FF = (V1 2
VBE11)R×1 3× R1 2BE1K3(6) 12 .BE1 R
1  V2 = V1 3 3K 3 +  VBE 3VBE1 3 K 3  +
I LED I mode.
LED The currents 1 K 2 ; )K× β1 β× R1 K 2K β11ββ21β 2. + 1
Equation 11 R1  R1 
I B = (V1VBEI1FF) ×= (V1
toIFFinci- × VBE 1 2 1 2 >> 1.
through them K1 =are Fproportional
Equation
Equation 21, R1 K1 R1 K1β1β2 + 1 In the first V 2 ≈ Kin
term 3 ×Equation
V1. 10, the
dent-light flux, which I LED feedback gain K1 1 K 2 ratio of resistors R and R is approxi-
EquationI FF = (7V1VBE1) × × ; K 2β1β2 >> 1. 3 1
Equation
and forwardEquation 2
gain K2 describe.2 ratio of 6feedback gain K1 1andK1 mately 1-to-1.Equation
TheEquation Equation 11 R You must11 be careful with
Equation 2 V2 ≈ K 3 × V1.
forward gain K is transfer gain K3. Be- the transfer gain, K3, which is the rea-
K = IIFF
FB , Equation
(1) cause 7 Equation 6 2
Equation
K2 = I
1 2. K 1
and K2 are similar, K3 is ap- son that K3 remains in Equation 11.
K 2 reality, K may de-
IIFFLED
LED
I FF.
proximately K 3one. 2 ≈In
V=Equation K.3 × V71. 3
Iwhere K = = K1 )less 1K K 2 V2 ≈ K 3 × V1. (11)
. ILED is the
K LED’s current, and
. viate,IFF but=it(Vchanges 1 than 2×; KKβ or2βK12β2 >> 1.
2
I FF = (V1VBE1) ×1 × ×V 1; K
K2 = FF 2 I LED 1  BE
I K R1K K1 2 1β 2 >> 1 .
I LED I
LED
K3 = 2 . alone: R 1 1 When K 3
is one, voltages V BE1
and
K 2 = FF 32.
Equation
Equation (2)K1 V cancel each other to some degree.
I LED K BE3
EquationK 3 = 82 . (7) Therefore, Equation 11 omits the sec-
Equation 3 K1
Equation A3 description Equation 3
of the circuit begins with Equation7 7
Equation ond term in Equation 10. Base cur-
a sum of theVdc  V I
currents
FF at Node A.
Equation Equation
8 6 subtracts the base-to-emit- rent IB3 depends on resistor R4 and the
K12 = BE1 =
Equation 3. I FB + I B1. ter voltageVfrom (Ithe input voltage. Al- output load. When you can set both
V1 VR1I LED 2 =EquationFF + I B 38) × R 3 + VBE 3 .
K 2Kbase-to-emitter
V1VBE1 V  BEV 1 = I + I . (3) though K3 = the voltage is base currents to be equal, the last term
K 3 =K1 .2 .it is desirable to remove would cancel out, too. The values of re-
1 BE1 = FBI FB + B1I B1.
= I FB + I BR 1.1R1 V = ( I not
+ I constant,
) × R + V .
R1 2 FF B3 K
3 1 BE 3
V1VBE1 it. You accomplish this task using the sistor R2 and capacitor C1 must be small
Equation
Equa t ion 43= I FB + I B1. Equation 9 + I )× R + V .
The gains of both R1 transistors amplify emitter follower V2 in = (Ithe FF receiving
B3 3 cir- BE 3enough so that transistors Q1 and Q2
current IEqua into
tion the 4 base of Q . The cuit. Equation
The 8
output voltage, V , is a sum don’t saturate. C1 enhances stability.
B1 Equation 4 1Equation 9
Equation 4 Equation 8 R and the2 base-to-
amplified current then flows through of voltage across Figure 2 shows the necessary voltage
V1V=BE β11β2= ×I I B1+. I .  Q. 9
3
1  for the circuit to begin operation. The
the LED. IEqua LED tion 4 emitter voltage I = of
Equation
( V V ) × I × K
R1
FB B1
V2 = (I FFFF+ I B3) × 1R 3 +BE 
3
1 3.
VBE  B1  3.
I LED = β β × I .  R1  output voltage (upper trace) has flat-
I LED = β1β2 × I B1. I LED = β1β2 × I B1.
1 2 B1 (4) V2 = (1I FF + I B3) × R 3 + VBE 3 . (8) ness at its lowest voltages as opposed
I FF =  (V1VBE1) × I B1  × K 3 .
Equation R1 to the input voltage (lower trace).
I LED = β1β52 × I B1.   1
Equations Equa 1 throughtion 4 4 yield the out- You Equation can use 9
aIFF
Equation different
= 10 VBE1) × to
(V1equation  × K 3 .3 shows the two signals’ linear-
I B1Figure
Equation
Equation 5 5  R1  Dividing the measured maximum
Equation 5put feedforward current: yield the
Equationfeedforward 9 output current: ity.
1 Equation K 2β1β210 of voltages V1 and V2 yields 0.91V. A
IIEquation
FF = (=Vβ1 β5VBE × I1) ×. × . I =  (V V ) × 1 I  × K . test circuit uses an IL300, which has
LED 1 2 B1 R1 K1β1β2 + 1 FF 1 BE 1
R 3 R110   B 1 3
 of 0.851 to 0.955. The mea-
I FFI 1= (=V1( V ) ×
1 1 K 2K
×
β1ββ2 β
.  V =Equation
 V K +  V  V(9) Ra3gain K  + R 3(I B 3I B1K 3).
VK 2
 βBEV
1 β
12 ) × × (5) 2 1 2 . 2 1 3 1 BE 3 BE 1 3
I FF = (V1VBE1) × FF × 1 BE1 .R1R K1K β1ββ2 β+ 1+ 1 I FF =  (V1VBE R11) × I B1  × K 3 . Rsurement 1  meets the requirements of
R1 K1β1β2 + 1 1 1
KV
1 1
β1R
2
βYou3 K can  rearrange
 R 3 R1 8 and  9 Equation 11 despite the equation’s
V = 2 2 + V
 BE 310 BE1 V equations K + R (I I K ).
IEquation
FF = (V1
Equation 65VBE1) × R ×2K β 1β Ras: .3Equation  3 3 B 3 B1 3
R1R   simplifications.
1 1 1 2+ 11  3 R  EDN
Equation 6 EquationV2 = V11 1 K 3 +  VBE 3VBE1 3 K 3  + R 3(I B 3I B1K 3).
Equation 6 Equation 6 Equation 10 R1  R1 
11 K K 2β1β2 R3  R3 
= ((V
IIEquation V1 VBE1))×× Equation × 2 11 . V2 =1.V1 K 3 +  VBE 3VBE1 K 3  + R 3(IB 3IB1K 3).
FF =
FF 1 6VBE 1 R × K1β; 1K β22β+1β12 >> R1 R1
44 EDN | july 23, 2009 1R111 K K 2K; 2K β β >> 1. V2 ≈Equation
1 K 3 × V1. 
I FFI 1= (=VK  V )
BE1 1) ×× ×  11 
I FF = (V1VBE1) × FF × (V21 ; KV2BE .×1K ; K 2β1β2 >> 1. R R
1 2 1 2
β1β2R>> 1R11K V2 = V1 3 K 3 +  VBE 3VBE1 3 K 3  + R 3(I B 3I B1K 3).
R K 1
Dark-activated switch needs voltage level of approximately 40V.
To achieve this level, the circuit uses a
only three components voltage divider comprising a photocell
and resistor R1. When you light the
Abel Raynus, Armitron International, Malden, MA photocell, its voltage drop is lower than
the triggering level of the threshold


Assume that you have a device Electronics (www.teccor.com) origi- voltage, and Q1 is locked, so the load
that receives its power from the nally developed. The primary purpose disconnects from the ac line. When it
main 120 or 220V-ac line and you need of any triac is bidirectional-ac switch- becomes dark, the peak voltage ampli-
to add a switch between the ac line and ing. The Quadrac triac has a built-in tude on the photocell increases to 40V,
the device so that the device works triggering device with the threshold- opening Q1 and making the load con-
only when it is dark. Although you may nect to the power line.
LOAD
think this task would be trivial, it is dif- The choice of Q1 depends on
R1 LOAD
ficult to find a workable approach be- 47k 2 the load current and ac-line volt-
cause most of the published schematics 1W 3
Q1 age. This circuit uses the Q4004LT
1 Q4004LT
need 6 to 12V-dc power supplies and re- 120V AC from Littelfuse (www.littelfuse.
lays. Several off-the-shelf dark-activat- 120V AC com) with a maximum current of
ed switches, such as devices from Suns 4A rms and a voltage of 400V. You
International (www.suns-usa.com), are can use any photocell, but this cir-
available, but they’re expensive for a PHOTOCELL
cuit uses an off-the-shelf model
consumer product. After looking at and accordingly uses a value of
products from dozens of Web sites, you Figure 1 This dark-activated switch 47 kV for R1 to achieve reliable
may decide to make your own. The so- needs only a photocell, a resistor, and switching. For an inductive load,
lution is simple and inexpensive. a triac to switch between the ac line and add a 100V resistor in series with
The circuit in Figure 1 employs an the device. a 0.1-mF capacitor between pins 1
internally triggered triac, which Teccor and 2 of Q1.EDN

edn090625di44671 DIANE
(PLACED IN THE 6-25 FOLDER)

july 23, 2009 | EDN 45

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

High-speed op amp enables

IR-proximity sensing D Is Inside
44 Set your lights to music
Arpit Mehta, Maxim Integrated Products Inc, Sunnyvale, CA


48 Current limiter allows
IR (infrared)-proximity sensors modulate the LED’s IR signal with a large USB bypass capacitance
can sense the presence of an ob- convenient frequency and then de-
ject, its distance from a reference, or tect only the IR with that modulation, 50 High-speed pulse modulator
both. Applications include speed de- which identifies it as a reflection from retains signal envelope
tection, sensing of the hand in auto- the object.
EWhat are your design problems
matic faucets, automatic counting or This Design Idea describes an IR-
and solutions? Publish them here
detection of objects on conveyer belts, proximity sensor with simple transmit-
and receive $150! Send your
and paper-edge detection in printers. ter and receiver sections (Figure 1).
Design Ideas to edndesignideas@
The latest-generation smartphones, for The transmitter consists of an Ever-
reedbusiness.com.
example, can turn off the LCD touch- light (www.everlight.com) 940-nm
screen to prevent the accidental acti- IR11-21C IR LED, which turns on and ETo see all of EDN’s Design
vation of buttons when you press the off using a 10-kHz oscillator frequency. Ideas, visit www.edn.com/design
screen against your chin or your ear. By varying the LED’s current, you con- ideas.
To sense an object, a proximity sen- trol the level of transmitted power and,
sor transmits IR pulses toward the ob- hence, the detection range. To save
ject and then “listens” to detect any power, the transmitting pulses have a
pulses that reflect back. An IR LED typical duty cycle of only 10%. tects; the photodiode’s peak sensitivity
transmits the IR signals, and an IR The receiver circuit demodulates occurs at 940 nm. The photodiode out-
photodetector detects the reflected sig- and amplifies the IR signals that the put ac couples to the op amp’s nonin-
nal. The strength of this reflected sig- Everlight PD15-22C photodiode de- verting input. This coupling allows the
nal is inversely proportion- 10-kHz signal to pass, but
al to the distance of the ob- the coupling capacitor sets
ject from the IR transceiv- a 300-Hz cutoff frequency
OBJECT TO BE DETECTED
er. Because the reflected that prevents dc noise and
IR signal is stronger when background IR from reach-
the object is close, you can ing the amplifier.
calibrate the output of the Low noise, high band-
photodiode detector to de- width, and rail-to-rail-I/O
termine the exact trigger capability make the op amp
distance of an object. The a good choice for demodu-
trigger distance indicates IR LED PHOTODIODE lation and amplification in
the threshold for making a this circuit. In addition, its
decision on whether an ob- IR-SIGNAL- RF immunity prevents the
ject is present. DETECTION annoying 217-Hz audio
BIASING-
AND
The photodiode detects CIRCUITRY
-AMPLIFICATION
buzz that you commonly
IR not only that the object TRANSMITTER find in GSM (global-sys-
RECEIVER
reflects, but also from the tem-for-mobile)-commu-
ambient conditions. You nications cell phones. For
must filter out this IR noise Figure 1 An IR-proximity sensor detects an object by receiving the IR receiver, the op
to prevent false detections. reflected light. amp acts as a gain-of-100,
A common method is to second-order bandpass fil-

august 6, 2009 | EDN 43

edn090611di45211 DIANE
(PLACED IN THE 6-25 FOLDER)
designideas
470 pF
5V
2.5V 475k
5V PEAK DETECTOR
180 5V
2.49k 470 pF
4
IR11-21C �
IR LED OUT
MAX4230
PD15-22C 470 pF
�
OSCILLATOR 3 1 �F 100k
50k
1M
2

IR TRANSMITTER
2.5V
AMPLIFIER AND
IR DEMODULATOR
RECEIVER

NOTE: CIRCLED NUMBERS REFER TO THE OSCILLOSCOPE TRACES IN FIGURE 3.

Figure 2 An IR transceiver detects the presence of an object and provides an approximate distance from the transceiver.

ter with a center frequency of 10 kHz.

Thus, the op amp amplifies the incom-
ing IR signals and demodulates them
with a bandpass filter.
With no input IR signal present,
the op amp is biased at 2.5V. With a
edn090611di45212 DIANE
10-kHz IR signal incident, its output(PLACED IN THE 6-25 FOLDER)
varies around 2.5V with a dynamic
range of 5V. The output drives a sim-
ple diode detector, which rectifies the
10-kHz signal and provides a dc sig-
nal proportional to its amplitude. This
analog-output signal is proportional to
the distance of the object from the IR
transmitter. You can use it as is or feed
it to an ADC for further processing.
Figure 2 shows circuit operation at
three nodes for objects at 1.2 and 1.4
in. from the IR transceiver. The circled
Figure 3 Different distances produce received waveforms of different
numbers in Figure 2 refer to the oscil-
amplitudes.
loscope traces in Figure 3.EDN

Set your lights to music Its output (DOUT), which the rising
edges of SCLK clock, comprises four
Hanif Saeed, Maxim Integrated Products Inc, Sunnyvale, CA
leading zeros followed by the 12-bit


As one of many ways you can
implement a light show, the
circuit in this Design Idea selectively
activates various subsets in a group of
six strings of lights, causing them to
flash on and off according to the level
and tempo of music you are playing.
The stand-alone circuit requires no
microcontroller, no software, and no
trimming (Figure 1). You apply the
audio signal you want to display to
IC1, a 12-bit ADC. The signal rang-
es from 0 to 2.048V, causing the first
string of lights to come on at 2 mV.
Although the circuit controls six ac
outlets, you can expand it to control
12 outlets.
A short positive pulse at the CNVST
pin of IC1 triggers it to initiate a con-
version, which the SCLK signal clocks.
conversion result, MSB (most-signifi-
cant bit) first. Thus, one conversion re-
quires 16 clock pulses at SCLK.
A vertical stack of six switched out-
lets, in which the top outlet repre-
sents the MSB, powers the display. You
might, for example, plug a separate
string of lights into each outlet. During
operation, the circuit scans each con-
version result as it is generated (MSB

44 EDN | august 6, 2009

designideas

C4
100 pF VCC VCC
Q7 Q7 A D
CTC
R5 MR Q6 B PB1
10k SH_CP Q5 C E
RTC Q4
IC4 ST_CP
R4
74HC4060 Q3
22k DS VCC
RS Q2
IC5 IC6 A D
Q9 74HC595 Q1 74C901 B PB2
Q0
Q4 C E
C3
100 pF MR GND OE GND
C2
100 pF A D
B PB3
VCC C E
IC2 VCC
Q7 Q7
74HC132
MR Q6
SH_CP Q5 A D
R3 ST_CP Q4 B PB4
10k D2 Q3 C E
DS
1N4148 Q2
IC5
GND
74HC595 Q1
C5 Q0
A D
220 pF
OE GND B PB5
R2 GND C E
10k

D1 C6
10 �F A D
1N4148
B PB6
5V
7 4 C E
VL VDD EMI
IC1 FILTER
MAX1276
10 9 ISOLATION POWER BLOCK A2
SCLK CNVST D
BARRIER Q1
12 A D3
� AIN� 6 T1 R6
IN5817
4 18.5 G
1 8 V 1
� AIN� DOUT B SD CC D1
C7 C8 R7
2 IC7 0.1 �F
REF 22 �F 7.8 A1
C1 R1 MAX253
E
10 �F 3 RGND GND 10k 3
FS D2
8
6 GND1 GND2 NOTE:
D4
0 2 7 1CT:1CT IN5817 TRIAC IS MOUNTED
TO INSULATED HEAT SINK.
C

(a) (b)

Figure 1 Driven by a 0 to 2.048V music signal at pins 12 and 1 of IC1, this circuit activates the six ac outlets according
to the music amplitude, in a logarithmic thermometer-code format (a). The power block (b) represents each of the power
blocks, PB1 through PB6.

first, as described previously) and notes
the first bit to assume a value of one. It
then turns on the corresponding outlet
and all those below it in the stack. The
result is a logarithmic column, in which
the change of input voltage necessary
to move the column one step up or
down (a 12.04-dB increment) is either a value of one charges C5 through D1
quadruple or one-fourth the immediate to the logic-one level. The voltage on
value. Although the number of steps C5 connects to the data input (DS) of
available equals the ADC’s resolution
edn090423di44491 DIANE
the first of two cascaded 74HC595 ICs,
of 12 bits,(PLACED
this circuit
IN THEuses only every
7-9 FOLDER) which together form a 16-bit shift reg-
other one to drive the six outlets. ister. The signal that clocks the ADC,
At DOUT, the first output bit with slightly delayed, also clocks this shift

august 6, 2009 | EDN 47

designideas
register through the NAND gates in
IC2 and thereby inserts into the shift
register the value present at its input.
At the end of a conversion, the voltage
stored on C5 forces to one all the bits
following the first one that exhibits a
value of one.
At the completion of each conver-
sion, a negative pulse applied to the
ST_CP inputs of both 74HC595 ICs
transfers these shift-register contents
to a parallel-output register, IC6. The
same pulse discharges the storage ca-
pacitor through diode D2, leaving the
circuit ready for the next conversion
scan. The parallel-register outputs then
serve as drivers for the 12-bit logarith-
mic column, with the MSB driving the
top outlet.
IC4, a 74HC4060, serves as a clock
and timing-sequence generator, and
IC2, a 74HC132, provides some nec-
essary glue logic. For each connected
74HC595 output, the signal, which
IC6 inverts, activates the correspond-
ing MAX253 transformer driver, IC7
in one of the six power blocks. A 1-
to-1 transformer isolates this driv-
er signal, which then triggers solid-
state TRIAC (triode for alternating
current), Q1, to its on state. For the
component values in the figure, the
circuit has a display-sampling rate of
about 2.5 kHz and uses the 12th, 10th,
eighth, sixth, fourth, and second bits
to control the six outlets. The result-
ing light show adds an extra dazzle to
the music you are playing.
This circuit operates at lethal voltag-
es and requires proper handling. Note
that the transformer must withstand a
line level of 120V ac. It operates with
incandescent light bulbs; you should
not use any other type of light bulb.
Even though the outlets are standard
120V-ac outputs for use with commer-
cial incandescent lights, fast switching
in the TRIACs makes them unsuitable
for driving other types of loads, such
as appliances, electronics, or ac adapt-
ers. Transformer T1 is a TGM-350NA
from Halo Electronics Inc (www.halo
electronics.com), and TRIAC Q1 is
a T1235-T from STMicroelectron-
ics (www.st.com). For a video of this
circuit in action, go to www.edn.com/
090806dia.EDN

Current limiter allows rent-sense amplifier, IC1, to limit in-

rush current below the specified maxi-
large USB bypass capacitance mum, allowing the device to use more
capacitance when necessary.
Daniel Morris, Group IV Technology, Renton, WA The LTC6102 usually translates the
voltage across a current-sense resistor


The USB (Universal Serial Bus) age drop at the device as inrush cur- to a larger ground-referenced voltage
specification requires a connect- rent charges its capacitance. Occasion- in an output resistor. The part features
ed USB device to present a load to the ally, a bus-powered device needs more an amplifier with low offset voltage,
host or hub of no greater than 10 mF than 10-mF bypass capacitance to pro- letting you use low-value sense resis-
in parallel with 44V, including the ef- vide an adequate reservoir for current tors. In the usual circuit configura-
fects of any bypass capacitance visible spikes. The circuit in this Design Idea tion, output current flows through an
through the device’s voltage regula- repurposes a Linear Technology (www. onboard FET whose source connec-
tor. This limit avoids excessive volt- linear.com) LTC6102 precision cur- tion connects to a force pin separate
USB
from the amplifier in-
R1
VBUS 0.02
put pin to minimize er-
rors across trace and pin
Q1 resistances.
R2 R3 R7 SI2323DS This circuit grounds
10k
402 402 C2
1 nF
the LTC6102’s output
8 1 pin and uses the on-
board FET as a source
follower to drive the
� �
5 7

C3
C1 � gate of an external
200 �F LOAD
6
100 nF current-limiting FET
(Figure 1). The feed-
3
R5 R4 2 back loop around the
249k 1M
LTC6102 maintains
HIGH-POWER
Q2 equal voltages at the
BSS123
ENABLE IC1 positive and negative
4
LTC6102 inputs of the amplifier,
R6
10k pins 8 and 1 of IC1. Re-
USB
GND sistor divider R2/R4 sets
the positive input of
Figure 1 This circuit limits USB-device current both at connection and after configuration. the amplifier, IC1’s Pin

48 EDN | august 6, 2009

designideas
8, approximately 2 mV below the 5V
USB-voltage rail. With Q1 initially
off at device connection, the negative
amplifier input, IC1’s Pin 1, is higher
than the positive input, causing the
amplifier’s output to go low. As the
amplifier’s output drops, the onboard
FET follows, pulling the gate of Q1 low
and turning it on. Current increases in
Q1 until the voltage drop across sense
resistor R1 matches the drop across
resistor R2.
Resistor R3 and capacitor C2 com-
pensate the feedback loop against os-
cillation and slow the turn-on of Q1,
preventing an initial current spike
when the device connects to the bus.
Capacitor C3 bypasses a regulator on
IC1. Resistor R7 meets the allowed
maximum 1-mA current through the
FET on IC1. Q1 turns on at a gate volt-
age low enough that it does not exceed
the input range of 4V positive voltage
to IC1’s Pin 7 to Pin 2.
Instead of the large capacitive load
of C1, the circuit presents a resis-
tive load to the USB host equal to
R1(R21R4)/R4549.8V, lighter than
the 44V maximum requirement. Af-
ter C1 charges, the circuit continues
to limit current below the 100-mA
maximum permitted to a low-power
USB device. Upon configuration, the
device can raise the current limit to
the 500-mA maximum permitted to a
high-power device by turning on FET
Q2 to place R5 in parallel with R4, in-
creasing the voltage maintained across
sense resistor R1.EDN

The circuit uses just one and one-half

High-speed pulse modulator retains ICs from Analog Devices (www.analog.
com). IC1 is a triple video amplifier, the
signal envelope ADA4856-3 with a gain of two (Ref-
erence 1). Amplifier A1 acts as a volt-
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia
age follower, which gives a maximally


The circuit in Figure 1 enables and its mean value approaches zero. smooth and flat frequency response.
you to convert an arbitrary, rela- This situation holds true for any input Amplifier A2 acts as an inverter, hav-
tively slowly varying voltage waveform waveform, even a dc voltage. The near- ing a voltage gain of negative one, and
to a new waveform in which the instan- ly zero dc component of the output of A3 serves as an impedance converter
taneous values of the original waveform the circuit in conjunction with the up- with a voltage gain of one.
alternate with positive and negative conversion of the frequency band lets IC2, an ADG772 high-speed 2-to-1
signs. The new waveform retains infor- the modulated waveform pass easily multiplexer (Reference 2), alternately
mation about the original waveform, through a transformer (Figure 2). switches the outputs of A1 and of A2 to
the input of A3. You must keep
LOGIC INPUT, the duty cycle of IC2’s logic-con-
FREQUENCY,
NOTES:
VS
2.4V
VDD
1.2V DUTY CYCLE=0.5 trol signal, IN2, close to 0.5 to
INx=LOW=�VS: ensure the “zero” mean value
B CHANNEL CONNECTED.
INx=HIGH=�VDD: of the output voltage, even at
A CHANNEL CONNECTED; x=1,2. 100 nF VDD IN2 IN1 �VS
a nonzero input voltage. At
IC2 a modulation rate, or the fre-
ADG772
IN
LOGIC INPUT
quency of the logic-control sig-
16 15 14 13
NC NC
REFERRED nal, of approximately 6 MHz,
TO �VS
IC1
S2B S1B the output voltage’s dc compo-
ADA4856-3 nent shifts negligibly only from
1 12
NC
D2 D1
the low-frequency mean-offset
�
A1 voltage of the circuit, which is
S2A GND S1A
2
�
�
less than 4 mV.
0V
A2 11 Experiments have confirmed
�
this value for an input voltage
100 nF 3
NC
� 10 of 0V and for the precise refer-
A
� 3 ence dc voltage of 0.8188V. At
4 �V 9 a frequency of 60 MHz, the dc
PD S
component of the output volt-
�VS
100 nF
age remains at about 4 mV for
5 6 7 8
OUT
an input voltage of 0V and rises
to approximately 175 mV for an
input voltage of 0.8188V. This
�1.2V result is still remarkable because
Figure 1 Video amplifiers and a switch pulse-modulate analog waveforms.
the ADG772 is a BBM (break-
before-make) type of multiplex-

50 EDN | august 6, 2009

 designideas
er/switch. During time interval longer, and the difference in
INPUT-VOLTAGE
tBBM, which is typically 5 nsec, VP WAVEFORM turn-on times of the A and B
both the S2A and S2B switches VIN(t) channels will be less signifi-
are temporarily off. Thus, the 0V cant. To prevent short over-
(a)
corresponding switch is on for t loading of amplifiers A1 and
approximately 8.2 nsec within A2, you can place SMD resis-
a half-period of a 60-MHz con- VP
OUTPUT-VOLTAGE
tors of about 20V to the out-
trol signal, yielding an on-state WAVEFORM puts of A1 and A2 when using
duration of only 3.2 nsec. An 0V VOUT(t) an MBB multiplexer.EDN
eventual 320-psec difference
of the turn-on times of switch- �VP t R e fe r e nce s
es S2A and S2B would cause a (b) 1 “ADA4856-3 Single-Sup-

shift in the dc component of ply, High Speed, Fixed G

81.88 mV. The corresponding Figure 2 The pulse-modulated waveform can pass 5 12 , Rail-to-Rail Output
dc components of output volt- through a transformer, providing signal isolation. Video Amplifier,” Analog
ages for an input voltage of 0V Comparing the input waveform, V (t) (a) with the Devices, 2008 to 2009,
IN
and an input voltage of 0.8188V output waveform, V (t) (b) shows that the frequency www.analog.com/en/
ation
ation
uationfor
for
forDI
DI
DI4508
4508
4508 ((Saved
differSaved
(Savedin
ininthe
by about the
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asfolder
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re- make
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flushleft
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leftfor
for
forwe
webbOUT
we ))b) audiovideo-products/video-
spectrum of the output waveform upconverts while its
sult of the difference in turn-on dc component becomes zero. ampsbuffersfilters/ada4856-
times of S1A and S1B. You can es- 3/products/product.html.
Equation
Equation
timate this difference
Equation 11 1 the follow-
using Thus, this application calls for an 2 “ADG772: CMOS Low Power
ing equation: analog multiplexer
edn090801di45082 DIANE having the speed Dual 2:1 Mux/Demux USB 2.0 (480
and bandwidth of the ADG772, and it Mbps)/USB 1.1 (12 Mbps),” Analog
175
175 mV mV should operate as an MBB (make-be- Devices, 2007 to 2008, www.analog.
320
320
320ppsec
psec ××× 175 mV≅≅≅
sec 81
8181..88
88 mV
mV
.88 mV fore-break) type. At a switching rate of com/en/switchesmultiplexers/analog-
684
684 ppsec.
sec. 60 MHz, the channels of such a multi- switches/adg772/products/product.
684 p sec.
plexer will conduct almost three times html.

52 EDN | august 6, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Triac tester allows for manual D Is Inside

or automatic operation 41 Handheld DMM copes
with logic nanosecond-pulse-
Abel Raynus, Armatron International, Malden, MA width waveforms


Triacs are bidirectional ac switch- ly attractive for micro­controller-driven 42 Build a simple complementary-
es that can control loads with devices. You can activate a triac direct- bracket-pulse generator
currents as high as 25A rms at voltages ly from microcontroller-output ports
as high as 600V. They find wide use in because of the triac’s trigger current of 44 Power-miserly voltage
motor-speed, heater, and incandescent- only 3 to 10 mA. As with any electron- reference needs just one pin
lamp controls. Logic triacs are especial- ic device, triacs can have some internal ETo see all of EDN’s Design
problems that you can de- Ideas, visit www.edn.com/design
tect before using them in a ideas.
TRIAC
9V design.
UNDER
TEST Figure 1 shows a simple
LED and inexpensive test fixture this idea to SMDs (surface-mount de-
1 2 3 S2 that tests the L2004F31, vices), provided that you can find or
S1 TRIGGER L2004F61, L2004L1, and create an appropriate test socket. Po-
POLARITY L4004V6TP triacs from larity switch S1, a DPDT (double-pole/
R1 R2 NC
1k 1k Littelfuse (www.littelfuse. double-throw) device, lets you check
NO
COM com), but you can use it conductivity in both directions. Trig-
to test any other leaded ger switch S2, a momentary SPST (sin-
triac because all the stan- gle-pole/single-throw) pushbutton de-
dard packages, including vice, activates the triac under test by
TO-220AB, TO-202AB, connecting the gate (Pin 3) with MT2
NC=NORMALLY CLOSED TO-251, and IPak, have (Pin 2) through resistor R2 (Figure 1).
NO=NORMALLY OPEN the same pin layout. An The test takes less than 5 seconds
IC socket provides easy and comprises four steps (Table 1). An
Figure 1 A triac tester uses a switch to reverse
insertion of a triac under LED indicates the result of each step
the polarity of the test signal.
test. You can also apply to the test operator. A triac is good if
NEON
TRIAC UNDER R1 TRIAC UNDER TEST R3
LAMP
TEST 4.7k 4.7k
LOAD LOAD
MT2 MT2
LED1 LED2 LED1 LED2
G MT1 G MT1 R2
R1 30k
100
edn090625di44951 DIANE
(PLACED IN THE 6-25 FOLDER)
LOAD LOAD
C1
0.047 �F 120V AC
120V AC
120V AC 120V AC

Figure 2 With a resistive load, the tester uses two Figure 3 For an inductive load, add a neon lamp to minimize leak-
LEDs to indicate pass and fail in both directions. age current.

august 20, 2009 | EDN 39

edn090625di44952 DIANE edn090625di44953 DIANE
(PLACED IN THE 6-25 FOLDER) (PLACED IN THE 6-25 FOLDER)
designideas
NEON 5V
LAMP
TRIAC UNDER TEST 606-A1C R3 OPTOCOUPLER
4.7k PS2501-2
LOAD
MT2
8 2 3 6
G MT1 R2
R1 30k
100 MICRO-
CONTROLLER
7 1 4 5
LOAD PA0
C1 PA1
0.047 �F 120V AC R4 R5
10k 10k
120V AC

Figure 4 An optocoupler isolates the triac from ground.

NEON 5V
LAMP
TRIAC UNDER TEST 606-A1C R3 OPTOCOUPLER
4.7k PS2501-2
LOAD
MT2
8 2 3 6
G MT1 R2
R1 30k edn090625di44954 DIANE
100 MICRO-
(PLACED IN THE 6-25 FOLDER)R6 CONTROLLER
7 1 4 5 100k
LOAD ADC0
C1 ADC1
0.047 �F 120V AC R4 R5 R7 � C2 � C3
10k 10k 100k
2.2 �F 2.2 �F
120V AC

Figure 5 RC filters let you use PWM signals.

it passes all four tests. You should per- ac is closed, both LEDs should be off. lel with the triac (Figure 3). Unfortu-
form another triac test during manu- When it is open, both LEDs should be nately, the snubber circuit introduces
facturing to ensure that there is no on. In the case of an inductive load, a small current leakage into the test
problem with the subassembly board such as a motor, use an RC snubber circuit even when the triac is closed.
and that the triac works properly. This circuit comprising C1 and R1 in paral- The circuit in Figure 3 shows you how
test saves time and labor in case you
detect a problem after assembling the TABLEedn090625di44955
1 TEST FOR TRIACS
DIANE
entire product. You perform this test (PLACED IN THE
Step no. 6-25 FOLDER)
Operations LED status Result
with the triac soldered into place on Off OK
Insert triac under test into
the board. You use the nominal pow- 1
the socket; turn on power On Shortage inside triac
er-supply voltage of 120/220V ac. The
test should have minimal influence on Off Break inside triac
the DUT and should use minimal time Push and release trigger Stays on OK
and labor. This test uses the triac tes- 2
switch S2
On but goes off Bad “hold” function
ter in place of a load. The connection after you release S2 in triac
from the tester to the DUT can vary,
and be sure to take some safety mea- Move polarity switch S1 Off OK
3
sures when connecting 120/220V ac. into another position On Shortage inside triac
You use a different test fixture for Off Break inside triac
triacs that drive a resistive load, such
Push and release trigger On OK
as an incandescent lamp or a heater 4
switch S2
(Figure 2). Each LED checks conduc- On but goes off Bad “hold” function
tivity in one direction. When the tri- after you release S2 in triac

40 EDN | august 20, 2009

to avoid this problem using resistor R2
and a neon lamp with an ac break-
down voltage of 95V.
The indicators of the test result in
figures 1, 2, and 3 are LEDs. Some-
times, the triac test is part of a multi­
tasking test system that checks oth-
er components or parameters of the
whole device, which includes the triac.
This test involves a sequence of mea-
surements, and a system operator gets
only one of two possible signals: pass or
fail. These tests use a microcontroller-
based system. Thus, all the interface
signals should be in digital format: high
or low.
You can also use analog signals by ac-
tivating the microcontroller’s ADCs.
This approach is less preferable, how-
ever, because of the limited number
of ADCs in low-end microcontrollers
Handheld DMM copes with logic
nanosecond-pulse-width waveforms
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia

When testing sequential-logic
circuits, you may find that, al-
though the repetition frequency of a
logic signal is within the range of your
DMM (digital multimeter), you can’t
measure it. The displayed frequency
value is either dubious or chaotically
changing in time. The DMM may also
behave as if there were no signal. Any
of these undesired states might appear
when the duty cycle of the measured
POWER-SUPPLY TERMINAL
C1
100 nF
R1
100
LOGIC SIGNAL
GND
LOGIC CIRCUIT UNDER TEST
Figure 1 A binary divider turns low- or high-duty-cycle waveforms into square
wave so that you can measure their frequencies.
edn090723di44131 DIANE
and more complicated software. Inter-
facing the triac under test with the mi-
crocontroller creates no problem if the
triac’s MT1 pin is grounded. In most
cases, MT1 and MT2 are isolated from
the ground. When this scenario occurs,
you can use an optocoupler, such as the
PS2501-2 from California Eastern Lab-
oratories (www.cel.com, Figure 4). It
comprises two optically coupled isola-
tors containing LEDs and NPN pho-
totransistors with a maximum voltage
of 80V.
If the triac output comprises a se-
quence of pulses, such as a PWM
(pulse-width-modulated) signal for
motor-speed or lamp-brightness con-
trol, then use a lowpass RC filter be-
fore the microcontroller’s ADC inputs
(Figure 5). The time constant of this
filter, t5R63C2, depends on the PWM
waveform is either close to zero or is ap-
proaching one—in other words, when
the width of a pulse—high or low—is
much narrower than the repetition pe-
riod of these pulses. This problem occurs
because you can’t expect a DMM with
an upper frequency limit of perhaps 200
kHz to measure 100-nsec-wide pulses,
even if the repetition rate of these puls-
es is well below the upper limit of the
DMM’s frequency range—perhaps just
DMM
7 8
PRE VDD
2
D 5
IC1 Q
SN74AUC1G74
1 FLIP-FLOP 3 biguous, and any noise in the measured
CLK Q waveform or that the comparator itself
CLR GND
6 4
signal period and duty cycle. The mea-
surement in the chain of tests should
start no earlier than 325t. Using the
microcontroller’s ADC requires addi-
tional firmware. To avoid this require-
ment, you can compare the voltage af-
ter the filter with a reference voltage
with a comparator, such as the LM393
from National Semiconductor (www.
national.com), to produce a logic-high
level for the microcontroller’s input.
Reference 1 describes an alternative
approach with minimal external com-
ponents for the expense of the firm-
ware complication.EDN
R e fe r e nce
1 Raynus, Abel, “Microcontroller
detects pulses,” EDN, July 24,
2008, pg 58, www.edn.com/article/
CA6578137.
5 kHz. For a rough estimation of band-
width for measuring at a pulse width
this(pulse a 6 folder))
of 100 nsec, consider
Equation for DI4413 placedtoinbe8 −
half-period of a square-wave signal. Use
the following equation to calculate the
required bandwidth:
1 1
B≈ = = 5 MHz.
2TW 2 × 107
This frequency is well beyond the
bandwidth of most DMMs. The second
cause of failing to measure the repeti-
tion rate of logic waveforms with too-
low or too-high duty cycles lies in the
internal ac coupling of the DMMs dur-
ing frequency measuring. Due to this
coupling, the decision threshold of an
internal comparator, which you derive
from the mean value of the measured
waveform, is close to either the low or
the high level of this waveform. In the
case of narrow pulses, the operation of
the internal comparator becomes am-
generates may cause an error.
You can address the problem by plac-
ing a binary divider between the source
of a logic signal and the DMM. The bi-
nary divider comprises IC1, a positive-
edge-triggered, D-type flip-flop (Figure
1). The supply pin of IC1 connects to
the supply terminal of the tested logic
august 20, 2009 | EDN 41
designideas
circuit. Therefore, you can run
the logic at any industry-stan-
dard supply voltage of 1.2, 1.5,
1.8, or 2.5V. In testing 3.3V
logic, use an external 2.5V
source to supply IC1. The in-
ternal protective diodes at Pin
1 of IC1, along with resistor
R1, reduce the voltage swing
at Pin 1 to an acceptable level
in such a case.
A square-wave signal is at
the output of the binary di-
vider (Figure 2). The DMM
no longer sees nanosecond
pulses at its measuring termi-
nal. You have only to mul-
INPUT LOGIC SIGNAL
tiply the displayed frequen-
SMALL DUTY CYCLE cy value by two to obtain
the correct frequency. Due
Q to relatively low values of
R1 and of the input capaci-
tance, approximately 2.5
pF, at the clock input of the
INPUT LOGIC SIGNAL
flip-flop, you need not worry
LARGE DUTY CYCLE about frequency compensa-
tion. The time constant of
Q
R13CIN is merely 0.25 nsec.
The width of pulses—either
low or high—at the input of
Figure 2 The flip-flop output, Q, produces a signal with a the circuit can decrease to
50% duty cycle. 1 nsec.EDN

edn090723di44132 DIANE
(PLACED IN THE 8-6 FOLDER)

Build a simple complementary- to form the desired outputs (Table 1).

Because IC1 is an analog demultiplex-
bracket-pulse generator er, you can set its outputs either active
high or active low with pull-up or pull-
Horst Koelzow, Global Thermoelectric, Calgary, AB, Canada
down resistors. You determine the high


When building push-pull
switching power converters or
motor controllers, you often need alter-
nating pulses with a small amount of
dead time between them to minimize
simultaneous conduction in output-
switching devices. Switching control-
ler ICs have this feature, but they usu-
ally operate within closed loops to min-
imize IC pin count. When optimizing
switching output stages, you may need
open-loop control. Figure 1 shows how
you can build such a generator with just
two common ICs. As a bonus, both the
overlapping, P-channel drive and the
nonoverlapping, N-channel drive are
available simultaneously.
The circuit’s input, Pin 10 of IC1,
comes from clock generator IC2F. A
slightly delayed and inverted version
occurs at IC1’s Pin 9 from IC2A. IC1 then
decodes the original and delayed inputs
or low inactive state by tying the X or Y
pins to either the power-supply voltage
or ground. Depending on the state of
IC1A’s A and B inputs, internal switches
in IC1 close between X and X0 to X and
X3, as well as from Y and Y0 to Y and
Y3. Buffers IC2B through IC2E buffer and
invert the resulting outputs. You can
use the remaining gate as a variable-
frequency or variable-duty-cycle gen-
erator. You determine the dead time,

VCC VCC
RV
R3 IC2D NONOVERLAPPING
R4
IC1B 10k 10k CD4584
RT CD4052 9 8
VARIABLE 12
X0
FREQUENCY VCC
13 12 14
13 X1
X 15 11 10
IC2F 16 X2
CT CD4584 INPUT 10 VCC 11
A X3 IC2E
OR CD4584
D1 R1
1N4148 IC1A IC1C
10k
CD4052 VCC CD4052 IC2B
VARIABLE 1 2 9 1 CD4584
B Y0
DUTY CYCLE 5 3 4
RV D C1 IC2A INH VEE VSS 3 Y1
2
1N4148 100 pF CD4584 Y 2
6 7 8 Y2
RT 4
Y3 5 6
13 12
R6 R7 IC2C
IC2F 10k 10k CD4584
CT CD4584
OVERLAPPING

Figure 1 You can build a simple pulse generator with just two commonly available ICs.

edn090723di44091 DIANE
42 EDN | august 20, 2009 (PLACED IN THE 8-1 FOLDER)
designideas
which is independent of frequency or TABLE 1 original and manufacturers, including Texas Instru-
duty cycle, using the time constant of delayed inputs ments (www.ti.com, Reference 1) and
R1 and C1. Depending on output-device On Semiconductor (www.onsemi.com,
Pin 9 Pin 10
characteristics and switching frequency, Reference 2).EDN
(Input (Input
output buffers may require an addition- B) A) Sequence
al stage, or you can replace them with R e fe r e nce s
0 1 Phase A
MOSFET-gate-driver devices. Sup- 1 “CD4051B, CD4052B,
ply voltage is not critical but should 1 1 Dead time CD4053B,” Texas Instruments, Octo-
be high enough to guarantee that out- 1 0 Phase B ber 2003, http://focus.ti.com/lit/ds/
put devices fully turn on. In general, a symlink/cd4052b.pdf.
0 0 Dead time
higher supply voltage allows for higher- 2 “Semiconductor and Integrated

speed operation. The MC14xxx series at lower supply voltages, then use the Circuit Devices,” On Semiconductor,
of ICs is the same as the CD4xxx series. 74HC4xxx-series devices. All of these www.onsemi.com/pub_link/collateral/
If you need higher-frequency operation ICs are available from a number of mc14584b-d.pdf.

Power-miserly voltage reference lations of initial watt-seconds minus

watt-seconds used yield even lower
needs just one pin values. Subtracting these fixed, repeat-
able losses from the initial steady-state
Peter T Miller, Applied Inspirations LLC, Bethlehem, CT 1.225V yields a new reference voltage
 The supply rail normally pow-
ers a microcontroller’s voltage- GP1/AN1/VREF
of 1.225VREF20.020V shutdown
drop20.080 IR drop51.145V.
reference source. In power-critical bat- 6 Allowing 75 msec to do the an-
tery-operated applications, the con- R1
alog-to-digital conversion, store
stant drain, even of a few 10s of micro­ 10k the value, and set up for the next
amps, can be prohibitive. This situa- PIC12F675 conversion on another channel,
MICROCONTROLLER
tion requires adding a pin to turn the 3 11 conversions will result in the
reference voltage on and off. By adding 1 last one’s reference voltage being
NC
a 0.1-mF capacitor in parallel with the C1 lower by 22.5 mV—that is, 10
ZXRE4041 0.1 �F
2
voltage reference and a simple bit of 1.225V conversions375 msec3(60 mV/
software that you can download from 2000 msec). This error is only
the online version of this Design Idea 1.9% compared with the first
at www.edn.com/090820dia, you’ll Figure 1 A voltage reference and a capaci- conversion’s results.
need just one pin to both power and tor provide a reference voltage for a micro- If you just need an approxi-
read the reference voltage. controller. mate voltage for a consumer
When you connect the voltage refer- product, for example, to warn
ence as in Figure 1, the software con- poses, you can consider it linear for this of low battery voltage, you can use an
figures the Microchip (www.micro- short time window. LED instead of the ZXRE4041. Just
chip.com) PIC chip’s VREF (reference- You must also consider that the change the value of R1 to 300V to pro-
voltage) pin as a switched-on output. ADC also draws current through the vide sufficient current to turn on the
After approximately 300 msec, the 10-kV resistor during conversion, caus- LED. Although LEDs lack the tem-
voltage across the capacitor stabilizes ing voltage drop. Although Microchip perature stability of dedicated voltage-
at 1.225V. doesn’t characterize this
edn090820di45021 voltage drop reference chips, the variation may be
DIANE
There is an initial overshoot when in its(PLACED IN THE 9-3 FOLDER)
documentation, tests consistently acceptable for the application because
the ZXRE4041 powers up. The pin is measured a drop of 80 mV for sever- most consumer products find use with-
then reconfigured as an analog input al devices, giving a calculated current in the comfort range of humans. If an
for the ADC’s reference-voltage source. of 6.67 mA. Using a conservative in- LED is already part of the system, then
The reference voltage quickly drops ternal 4-MHz clock and allowing an the voltage-reference cost is only that
by 20 mV in the next 50 msec as the ADC clock of frequency oscillation di- of the software. Using this technique,
ZXRE4041 shuts down. With a 0.1-mF vided by 16 for operation at the min- an LED can now provide status-indica-
capacitor, the voltage then slowly drops imum operating voltage, one conver- tor, photodetector, and voltage-refer-
60 mV over 2 msec because of leakage. sion takes 45 msec. This action slightly ence functions and enter a zero-power
Although this delay is exponential, the drains the capacitor, but this drainage state using only software to reconfigure
rate is so slow that, for practical pur- appears to be only 2 or 3 mV. Calcu- the changes.EDN

44 EDN | august 20, 2009

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Turn a set/reset latch into an D Is Inside

astable/monostable multivibrator 45 555 timer eliminates LED
Luca Bruno, ITIS Hensemberger Monza, Lissone, Italy driver’s need for microproces-
sor control


This Design Idea describes a
simple way to form a reliable
astable or monostable multivibrator
from a set/reset latch. You may find it
useful because it lets you minimize the
number of standard digital ICs your de-
D1
1N4148
R1
sign requires when absolute precision
isn’t an issue. You can use a set/reset
latch either with active-low or active-
high inputs, which you can build with
two NAND or NOR logic gates. You
can also use integrated set/reset latches
46 Smart photoresistor timer
needs few components
48 High-performance adder
uses instrumentation amplifiers
50 Nonvolatile standby/on
switch remembers its state
ETo see all of EDN’s Design
Ideas, visit www.edn.com/
designideas.

C1
S Q CLOCK OUT
or any type of flip-flop that comes with
TH TL
CMOS asynchronous preset and clear inputs
TH=R2C2 ln(VDD/VDD�VTH).
C2 LATCH because they have the same function
CLOCK OUT TL=R1C1 ln(VDD/VDD�VTH).
R Q as the set/reset inputs when the clock
R2 and data inputs are grounded. This
method functions only with CMOS-
logic families that offer the benefits of
high input impedance; a quasi-ideal
D2
(a) 1N4148 voltage-transfer characteristic with a
threshold voltage, VTH, typically equal
to the drain-to-drain voltage, VDD, di-
D1 vided by two; and low power consump-
1N4148
tion. This concept has undergone test-
ing with a 74HC00 quad NAND, a
R1 74HC02 quad NOR, a CD4001 quad
VDD NOR, a CD4011 quad NAND, and a
C1 CD4013 dual-D-type flip-flop.
VDD S Q CLOCK OUT TH TL Connecting two RC networks be-
CMOS tween the complementary outputs Q
C2 LATCH TH=R2C2 ln(VDD/VTH).
R Q CLOCK OUT TL=R1C1 ln(VDD/VTH). and Q and set and reset inputs enables
astable operation (Figure 1). Due to
R2 complementary outputs, the circuit has
no stable state, and it toggles continu-
ously, generating an output clock. The
D2 time constants R2C2 and R1C1 set the
(b) 1N4148 high and low time periods, TH and TL,
respectively, and also the duty cycle.
Figure 1 Capacitors that connect to ground or VDD depend on active-high (a)
Diodes D1 and D2 quickly discharge ca-
or active-low (b) inputs.
pacitors C1 and C2 so that, on the next

42 EDN | september 3, 2009

cycle, they will recharge from 0V.
In monostable mode, connect one
RC network (Figure 2), depending
whether you need a positive-pulse or a TRIGGER IN S Q PULSE OUT TW
negative-pulse trigger. When an input CMOS
C1 LATCH
trigger pulse occurs, it sets the output R Q PULSE OUT
pulse, TW, which remains in this state
until the RC network activates the R1
TW
reset pin. The RC time constant sets
the output-pulse width. For correct op- TW=R1C1 ln(VDD/VDD�VTH).
eration, the trigger pulse must be short- D1
(a)
er than the output pulse. Diode D1 re- 1N4148
duces recovery time.
The threshold voltage has the typi-
cal value VDD/2, but it may change from
0.33 to 0.67 of VDD for the CD4000 TRIGGER IN Q PULSE OUT
S TW
CMOS family. The parameters of the VDD CMOS
generated output signals of the cir- C1 LATCH
PULSE OUT
cuits in figures 1 and 2 present varia- R Q
tions from unit to unit as a function of R1 TW
threshold-voltage shift. On the other
hand, the threshold voltage presents TW=R1C1 ln(VDD/VTH).
good stability with supply voltage and
D1
temperature variations. (b) 1N4148
For best accuracy, the timing ca-
pacitors for both astable and mono­ Figure 2 The leading edge of the trigger pulse depends on active-high (a) or
stable circuits should be nonpolarized, active-low (b) inputs.
have low leakage, and be much larger
than the inherent stray capacitance
in the circuit, and the timing resis- CMOS on-resistance in series with the supply voltage for safety to prevent
tors for both astable and monostable them, which typically is hundreds of voltage spikes, which may disturb the
circuits must be much larger than the ohms. In addition, you must decouple circuits.EDN

edn090820di45372 DIANE
(PLACED IN 9-3 FOLDER)

555 timer eliminates LED driver’s 

LEDs find their way into appli-
cations that range from high-
need for microprocessor control end video displays to low-end light-
ing applications. Designers often need
Michael Day, Texas Instruments, Dallas, TX only some of the functions of a dedicat-
ed LED driver but can’t afford the cost
VCC
C2 VCC
0.1 �F IC1 IC2
555 C4 TLC5917 HIGH-POWER
R1 10-kHz CLOCK 0.1 �F LED
8 16 5
37.4k VCC VDD OUT0
4 3 3 6
RESET OUT CLK OUT1
4 7
7 DISCH LE(ED1) OUT2 OUTPUTS CONNECT
R2 13 8
6 ON/OFF CONTROL (ED2)OE OUT3 IN PARALLEL
20k THRES 2 9
ON/OFF SDI OUT4 FOR 842-mA
2 5 14 10 LED CURRENT
TRIG CONT SDO OUT5
1 15 11
GND C3 R-EXT OUT6
C1 R3 1 12
0.1 �F GND OUT7
1500 pF 178

Figure 1 A 555 timer provides the necessary pulses for configuring an LED driver.

september 3, 2009 | EDN 45

edn090820di45341 DIANE
(PLACED IN 9-3 FOLDER)
designideas
of the microprocessor to control them.
Microprocessors typically control ded-
icated LED drivers, enabling features
such as analog or PWM (pulse-width
modulation) for LED-current control,
independent control of each LED, and
reading LED status and faults. If your
design requires a constant-current
LED, such as those in LED lighting
or luminaires, then you may not need
these advanced features. In these ap-
plications, a 555 timer can replace the
microprocessor and still allow accurate
control of LED current independently
of input voltage, temperature, and LED
forward-voltage drops.
IC 2, a TLC5917 dedicated LED
driver, controls eight independent
constant-current sinks (Figure 1). It
normally requires a microprocessor to
drive four digital-input signals. The
command OE (output enable) enables
and disables the IC. Data on the SDI
(serial-data-input) pin clocks into the
IC’s input shift registers on the rising
edge of the clock. The data in the shift
registers transfers into internal on/off
latches on the falling edge of the LE
(latch).
Either the TLC5917 outputs can
drive eight independent LEDs, or you
can parallel its outputs to increase the
current to drive one higher-power
LED. Its internal current-setting reg-
isters have default values at start-
up. These values, along with exter-
nal current-setting resistor R3, set the
LED current. In this application, R3
sets each output’s current to 105 mA:
18.75V/R3518.75A/178V. Connect-
ing all outputs in parallel yields 842
mA of LED current.
Smart photoresistor timer needs
few components
Abel Raynus, Armatron International Inc, Malden, MA

An application required a photo
timer with some unusual func-
tions. It had to switch on the load, a
lamp, an hour after sunset. After work-
ing for three hours, the timer should
turn the load off, which had to remain
46 EDN | september 3, 2009
Figure 2 The LED current (lower trace) ramps up and down in eight steps.
At power-up, the internal on/off
latches that turn each output on or off
default to zero, so you must set these
latches to one before the outputs turn
on. The 555 timer replaces the micro-
processor for this function. The clock
and latch lines both connect to the
555 timer’s square-wave output. At
each rising edge of the clock, the SDI
shifts into the TLC5917’s input shift
register. This data latches into the on/
off latch at the falling edge of the latch
signal. Because shifting the data and
latching the data occur at different
clock edges, the clock and latch pins
can connect to the same input clock
signal. Hard-wiring OE to ground per-
manently enables the IC. You can
connect SDI to the power-supply
voltage to automatically turn on the
LED at power-up. This connection
continuously clocks in ones to turn on
all outputs. You can also connect SDI
to a switch or a digital input to allow
for LED on/off control. Then, SDI
off until an operator manually reacti-
vated the timer. The timer had to re-
side between the main 110/220V-ac
line and the load. And, as with any
other consumer product, it had to be
cost-effective. You can achieve these
can pull to the power-supply voltage,
which continuously clocks in all ones
to turn on the outputs. Alternatively,
it can pull to ground, which continu-
ously clocks in all zeros to turn off the
outputs.
The 555 timer’s clock speed deter-
mines how fast the LEDs turn on and
off. The LED current ramps from 0 to
100% in eight clock pulses as each fall-
ing edge of the latch pin latches the
SDI data into another of the eight in-
ternal on/off latches, turning on or off
another one of the eight outputs. Fig-
ure 2 shows the resulting stair-stepped
LED current increasing and decreasing
with each successive falling edge of the
latch. Even a relatively low clock speed
of 10 kHz results in an off/on and on/off
transition of only 0.8 msec, which the
human eye perceives as instantaneous.
You can achieve gradual turn-on and
turn-off with low clock speeds. Setting
the clock to 0.1 Hz gradually turns the
LED on and off in 0.8 sec.EDN
goals by using a voltage comparator
and dual timers with an RC-timing
network, but an inexpensive, 8-bit mi-
crocontroller with a built-in ADC pro-
vides a more elegant approach. You can
perform all the functions in firmware.
Listing 1, which is available at www.
edn.com/090903dia, contains down-
loadable source code.
Figure 1 shows the circuit, which
uses an eight-pin MC68HC908QT2
microcontroller from Freescale Semi-
designideas
D1
R1 R2 current and main voltage.
BLACK 4.7k 1N4003 1k
120V
LOAD The L2004F31 requires
AC 1 Q only 3 mA of dc-gate-trig-
WHITE 1 R4 1

(NEUTRAL) R 3 430 3 2
L2004F31 ger current, and it conducts
3
� � C 20k MC68HC PA4 4A rms at 200V ac. The
C1 D1 2 908QT2
100 �F 1N4733 22 �F
IC1
VT90N1 photoresistor
16V 2 PA0 7 from PerkinElmer (www.
ADC3
LED
4
optoelectronics.perkin
RST
RESET elmer.com) has a dark re-
8 sistance of 200 kV, which
drops in light to 10 kV or
Figure 1 This circuit uses an eight-pin microcontroller and a logic switch to provide a smart less. The LED indicates the
photoresistor. status of the timer: It is on
when the timer is ready for
work and waits for darkness. It blinks
POWER
during the delay, and it is off when
DARK RESET
ON the timer waits for reactivation (Fig-
LOAD
LOAD IS ON
TIME ure 2). The W934GD5V LED from
Kingbright (www.kingbright.com) has
a built-in resistor that minimizes the
LED
ON ON
TIME
number of necessary components. To
edn090723di45201 DIANE reactivate the timer, press the pushbut-
(PLACED IN THE 8-6 FOLDER) ton reset switch. All time delays are set
ONE HOUR THREE HOURS
in firmware, and you can easily change
them.EDN
Figure 2 The LED is on when the timer is ready for work and waits for darkness.
It blinks during the delay, and it is off when the timer waits for reactivation. R e fe r e nce
1 Raynus, Abel, “AC line powers
conductor (www.freescale.com). Ref- triac from Littelfuse (www.littelfuse. microcontroller-based fan-speed reg-
erence 1 describes a microcontroller’s com), switches the load on and off; the ulator,” EDN, Nov 9, 2006, pg 128,
power supply. Q1, an L2004F31 logic type you use depends only on the load www.edn.com/article/CA6387025.

the source impedance of the driving

High-performance adder uses signal is large or requires the design of
low-impedance driving sources. This
instrumentation amplifiers circuit also has no common-mode-re-
Moshe Gerstenhaber and Michael O’Sullivan, jection capability, so inputs must be
Analog Devices, Wilmington, MA single-ended. The channel with the
edn090723di45202 DIANE largest gain limits the performance of


As instrumenta-
tion amplifiers be-
come less costly, they can
provide improved per-
formance in applications
that operational amplifiers
traditionally served. The
op-amp adder in Figure
1 has a few shortcomings.
First, the inputs have low
to medium input imped-
ance, which the input re-
sistor of each signal deter- Figure 1 A typical adder configuration uses a single op
mines. This arrangement amp.
causes gain errors when
(PLACED IN THE 8-6 FOLDER)
the entire system. Higher gain
10V P-P, 1-kHz on one channel results in lower
SINE WAVE
10 10k
bandwidth, higher distortion,
and increased system noise on
all channels. To limit these ef-
fects, even low-performance ad-
10k
� SINE-WAVE
ders require high-performance,
OUT
OP27 OUTPUT high-bandwidth op amps.
10V P-P, 1-kHz �
SINE WAVE
The noise gain of this op-
amp adder is 1110,000/
(10||10,000). The input signal
with the highest gain and 10V
input dominates the noise gain,
but all inputs suffer increased
offset voltage, gain error, noise,

48 EDN | september 3, 2009

edn090820di45401 DIANE
(PLACED IN THE 9-3 FOLDER)
designideas
and distortion. You can
increase input impedance
and improve common-
mode rejection by using
instrumentation ampli-
fiers. The output voltage
of an instrumentation
amplifier is proportional
to the voltage difference
between the positive and
the negative inputs. You
can amplify this signal
by connecting a resistor,
RGAIN, to the RG pins (Fig-
ure 2). The output volt-
age is generated between
the reference pin and the
output pin. This arrange-
ment allows you to use the
reference pin to cascade
multiple signals together
Figure 2 Two instrumentation amplifiers provide increased input
in an adder configuration.
impedance in this adder circuit.
You can set each instru-
Figure 3 The instrumentation-amplifier configuration shows improved THD1N
at frequencies greater than 300 Hz.
RGAIN
mentation amplifier to a
different gain.
This system has several
10V P-P, 1-kHz
SINE WAVE R G � R G � advantages over the sim-
ple op-amp adder. For ex-
IN�
� ample, each input has ex-
AD8221 OUT SINE-WAVE tremely high input imped-
OUTPUT
IN� ance and has independent
�
REFERENCE common-mode rejection,
which the instrumenta-
tion amp connected to
that channel determines.
10V P-P, 1-kHz The higher the channel
SINE WAVE RG� RG�
gain, the higher the com-
IN� mon-mode rejection, and
�
AD8221 OUT the smaller the resulting
IN� error. You can also easily
�
REFERENCE
add or subtract signals by
using the inverting or non-
inverting terminals of the
instrumentation amplifier,
and the amplifier enables
the use of differential input
signals if you wish. Further,
the distortion, noise gain, and band-
width of each signal are independent
of the other signals, leading to lower
offset voltage, gain error, noise, and
edn090820di45402 DIANE distortion. Figure 3’s THD1N (total-
(PLACED IN THE 9-3 FOLDER)
harmonic-distortion-plus-noise) plot
demonstrates five times less distor-
tion for the instrumentation-amplifier
adder than that of the op-amp adder,
even though the instrumentation am-
plifier has 1-MHz bandwidth and op-
erates at 1 mA, whereas the op amp
has 8-MHz bandwidth and operates at
4.5 mA.EDN

single-bit nonvolatile-memory cell. To

Nonvolatile standby/on switch remember the state of the standby/on
switch, this circuit programs IC4’s out-
remembers its state put voltage high or low and can repro-
gram it at least 50,000 times. IC1 is a
Anatoly Andrusevich, Maxim Integrated Products Inc, Moscow
low-dropout linear regulator with reset


You can use the standby/on
switch in Figure 1 for indus-
trial or telecom applications in which
the circuitry must somehow “remem-
ber” its state—standby or on—after a
power failure that occurs when no op-
erator is present. An alternative ap-
proach uses a battery or a supercapac-
itor and a flip-flop. This approach is
less reliable, however, because the cir-
cuit can lose its state if leakage current
drains the battery. Another alternative
involves the use of a microcontroller
and EEPROM, but that approach re-
quires software plus a provision for
start-up time. Also, a stand-alone
EEPROM for this application has an
awkward interface.
You can use an electronically pro-
grammable voltage reference, IC4, as a
output and a wide input-voltage range
that extends to 72V. A microproces-
sor supervisor, IC 2, debounces the
standby/on pushbutton and supports
the programming of IC4 by increasing
the pause length between pulses. IC4’s
output drives IC5, an inverter with
Schmitt-trigger input, which in turn
drives the gate of transistor Q2 to con-
trol the main power supply.

50 EDN | september 3, 2009

designideas
Flip-flop IC3 helps to change the sets IC1’s reset time-out to be longer 1.32V input-threshold voltage of IC5
standby/on state with each press of the than IC2’s reset time-out. The thresh- guarantees the standby position at first
control button. At the end of IC4’s pro- old voltage of IC2, 2.9V, is also lower power-on because the factory-preset
gramming cycle, a low-to-high edge at than that of IC1, 4.6V. The worst-case output for IC4 is only 1.2V.EDN
IC3’s clock input sets
the flip-flop to its op- 5.5 TO 72V
posite state, thanks IC1
VIN
MAIN
5V
to the feedback from MAX6766TTLD2 POWER
SUPPLY
the inverter. IC 2’s IN OUT
UVLO
TIMEOUT R1
reset triggers this C1 ENABLE C3 100k
1 �F 10 �F
action at power-up GND RESET C2
0.47 �F
to ensure that the
Q1B
switch is ready to 5V R2 R3
NTZD5110N 5V
change state. Tran- 100k 5.1k
sistor Q1B and IC1’s C4 C5
0.1 �F
reset output prevent Q1A 0.1 �F
NTZD5110N
the programming of IC2
MAX6468XS29D3
IC4
DS4305R
incorrect states by STANDBY/ON VCC
IC3
IC5 Q2
74LVC1G79 VCC VOUT
blocking IC4’s adjust MR RESET ADJ 74LVC1G14 BSS123L
CLK
input during start- GND
Q VIN VOUT
D
up and power-fail GND

conditions. D1
R4
510
You must block the
effect of IC2’s power- STANDBY

up or -down reset
pulse on IC4’s adjust Figure 1 The circuit remembers its standby or on state if power fails with no operator present.
input; C2 therefore

edn090820di45431 DIANE
(PLACED IN 9-3 FOLDER)

52 EDN | september 3, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Missing pulse detects position

or produces a delay D Is Inside
Michael C Page, Chelmsford, MA 47 Emulate SPI signals


Consider an application that
needs a series of pulses to indi-
cate position in which the lack of a
pulse “indexes” the count. To achieve
that goal, the application uses a rotat-
ing, 36-tooth sprocket with one miss-
ing tooth. Rotational speed ranges
from 500 to 7000 rpm. The mecha-
nism uses an inductive pickup to sense
the sprocket’s teeth. With one of the
sprocket’s 36 teeth missing, the detec-
tor senses 35 pulses, and then a pulse
disappears.
Unfortunately, the mechanism fre-
quently breaks down or simply breaks
apart. Because the application uses
this wheel just to trick the computer
by simulating an operating engine,
the application’s designers replaced
the rotating gear with a simulator cir-
cuit (Figure 1). Given the rotational
speed and number of teeth, the maxi-
mum pulse frequency is 7000/60336,
or 4200 Hz. The circuit works well
from single stepping to more than 1
MHz before starting to break down.
The maximum frequency depends
on the logic family and construction
methods you use.
Figures 2 and 3 show the outputs
with a digital-I/O card
48 Resistive DAC and op amp
form hybrid divider
49 Connect two buttons
with just two wires
ETo see all of EDN’s Design
Ideas, visit www.edn.com/design
ideas.
running at 100 Hz and 1 MHz, respec-
tively. At power-up, capacitor C1 re-
mains the same, which forces RST on

SIGNAL IN
R6 IC4B
R7
1k HC08 SENSE
1k

IC1A IC1B
R3 HC14 HC14 IC4C
1k R4
HC08 3.3k DETECT

CLOCK
� D4 D1 R2 R5
BZD23-4V7 D1N4148 1k 6.8k
1

CLK D2
Q0
D1N4148 D SET Q
RST Q1 IC3A
2 C1
Q2 4013
QN 1 nF
IC2 Q3 RST POWER
4024
D3 RESET � 5V
Q4 V1
D1N4148
Q5
32
Q6 R1
1k

IC4A
HC08

Figure 1 IC2 combines with three diodes to produce a stream of 36 pulses before resetting.

september 17, 2009 | EDN 45

designideas
5

VOLTAGE 3
(V)
2

0
0 50 100 150 200 250 300 350 400
TIME (mSEC) 50 mSEC/DIV

Figure 2 Operating at 100 Hz, the circuit signals include the clock-sine-wave signal (red), the sense-square-wave signal
(green), and the detect signal (blue), which indicates the missing pulse.

5 EDN090917DI4503FIG2 MIKE

3
VOLTAGE
(V) 2

0
0 5 10 15 20 25 30 35 40
TIME (�SEC) 5 �SEC/DIV

Figure 3 The pulse train at a clock frequency of 1 MHz still shows the missing 36th pulse along with the power-reset
signal (blue).

IC3A low. That action puts the D flip- in.” Diodes D1, D2, and D3 pull up to As clock pulses continue into IC2
flop into a known state. As C1 chargesEDN090917DI4503FIG3
5V through R2 and
MIKEform an AND gate and when outputs Q0, Q1, and Q5 are
through R1, the voltage at the power to select the desired count. Coun- all high, with a count of 35, IC3A’s D
reset falls, letting clock pulses set IC3A’s ter IC2’s outputs are binary, so, for a pin pulls high through R2. On the next
outputs. You must keep the small val- 36-tooth sprocket with one missing clock pulse, the Q output of IC3A goes
ue for the C1/R1 combination if you tooth, outputs Q0, Q1, and Q5 cor- high and the QN output goes low, stop-
use a high input frequency with a low respond to 112132535. ping the pulses from passing through
count rate. As Figure 3 shows, the de- You can produce any count as high IC4B. This action indicates the missing
sired count must exceed the duration as 128 by adding the appropriate di- tooth and produces the sense condition
of the power reset. The values in Fig- odes on the Q outputs on IC2. In oth- (the missing pulses in figures 2 and 3).
ure 1 provide a time of approximate- er words, you need to generate one Meanwhile, the Q output of IC3A’s out-
ly 0.6631 kV (the value of R1)31 nF missing pulse of 36 to simulate the put goes high, yielding a single detect
(the value of C1), or 0.66 msec, leav- 36-tooth sprocket. Thus, you select a pulse at IC4C through R4 and R5. On
ing a minimum count of approximately count of 35; the circuit automatically the next clock pulse, with IC3A’s Q
three at 1 MHz. adds a count of one due to the one- output high, IC2 resets logic zero and is
For the clock signal, the circuit clock delay of the counter. Because ready for the next count cycle. R4 and
uses a sine-wave signal with an am- you reset IC2 at power-up, all outputs R5 halve the clock signal just to make
plitude of 5 to 10V from the system. are low, keeping the D input of IC3A the graphics clear at “detect.”
The clock signal goes through R3 to low, with a count of zero. The 4024 is an eight-stage binary-
D4 and IC1A to produce a 5V square- ripple counter. You can replace it with
wave signal. The signal goes to coun- a 4040 counter to achieve a count of
ter IC2 and to one input of AND gate
the circuit auto- 2048, and you can cascade counters to
IC4B. With the other input of IC4B matically adds a get longer counts or delays. The 4040’s
coming from IC3A’s QN output, which count of one due pinout differs from that of the 4024,
is high from power reset at start-up, but their operation is identical. Some
the input-pulse train passes through to the one-clock systems have an extra tooth instead of
IC4B, which simulates sprocket teeth delay of the a missing tooth, and some have mul-
at the sensor. Resistors R 6 and R 7 tiple missing teeth at odd locations
halve the clock-signal amplitude just counter. around the sprocket, all waiting for re-
to make the graphics clear at “signal placement by this simple circuit.EDN

46 EDN | september 17, 2009

Emulate SPI signals in/slave-out) lines. The clock line is a
signal from the master to the slave. All
with a digital-I/O card SPI signals are synchronous with this
clock. The SS line selects the slave for
Andy Street, Autoliv Electronics, Lowell, MA communication. The SPI specification


A design-verification tester for defines four modes of operation, which
millimeter-wave SOC (system- you can store effectively specify the clock edges for
on-chip) devices needed to combine toggling and sampling and the clock-
switching, electrical measurements, a maximum of 32 idle level. The specification makes no
temperature measurement, a parallel- traces in the pat- requirements on voltage levels or data
digital interface, and a serial-digital in- rates, and many SPI implementations
terface into one instrument. To mini- tern RAM per bank. can clock in excess of 10 MHz. Fig-
mize rack space, the circuit uses an Agi­ ure 1 shows a block and timing dia-
lent Technologies (www.agilent.com) gram of the 34950A’s Bank 1, config-
34980A multifunction mainframe be- However, the card’s handshake lines ured for synchronous, buffered output.
cause its plug-in cards could support a provide insufficient control for imple- H0 through H2 denote the handshake
force/sense dc matrix and multiplexed menting SPI transactions. To get ade- lines. The figure also shows an 8-bit
temperature measurements. The ad- quate control, you can emulate the SPI SPI transaction for reference.
dition of an Agilent 34950A 64-bit bus using three of the data-I/O lines. You cannot use the 34950A’s hand-
digital-I/O card formed the basis of a Motorola (www.motorola.com) shake lines to emulate all modes of the
system that could provide both an SPI micro­controllers first used the SPI SPI bus because the bus latches data
(serial-peripheral-interface) bus and a master-slave protocol. Today, it’s be- on the falling edge of the clock, mak-
simple parallel bus. The 34950A groups come the control interface in a va- ing the bus unsuitable for slaves that
its I/O lines into two banks of four 8- riety of ICs, including PLLs (phase- use the rising edge. Inverting the clock
bit channels. It provides 64 kbytes of locked loops) and RF ASICs (refer- polarity is not a solution because you
memory per bank for pattern genera- ences 1 and 2). The SPI bus uses the may lose the last data bit. Furthermore,
tion or signal capture. It also has three clock, SS (slave-select), MOSI (mas- if you write a number of transactions
I/O lines per bank for handshaking. ter-out/slave-in), and MISO (master- to a slave, you must store each trans-
action as a separate
SPI PROTOCOL trace memory in the
34950A. Although
CLOCK each bank supports
D CLK
64k38 bits, you can
store a maximum of
34950A SLAVE
BANK 1 SELECT 32 traces in the pat-
D00
D SS tern RAM per bank,
8 CH 01 thereby limiting the
D07 number of SPI trans-
D08 MASTER
D DATA bO7 bO6 bO5 bO4 bO3 bO2 bO1 bO0 OUT/ actions. In addition,
8 CH 02
D15
SLAVE IN the card lacks a se-
D16 quencer, so you can-
8 CH 03 not download a num-
D23
D24
ber of bit patterns and
8 CH 04 34950A SYNCHRONOUS BUFFERED OUTPUT then play them in se-
D31 quence. You must load
H0 H0 each pattern into the
H1 S TART /
H2 S TOP I/O card’s memory
T/2 T
and then play each
H1
pattern under SCPI
S TROBE (standard commands
T PD
for program­mable in-
struments) from a
DATA IN VA LID VALID VALID VALID VALID VALID VALID VALID VALID host computer, slow-
ing transactions.
Figure 1 The 34950A synchronous buffered output uses the falling edge, making it unsuited to
Instead of using the
rising-edge SPI implementations.
handshake lines, this
solution uses three da-
EDN090917DI4507FIG1 MIKE

september 17, 2009 | EDN 47

designideas
ta-I/O lines to emulate the SPI clock,
SS, and MOSI. The software driver for
the I/O cards then has the responsibil-
ity of translating the data to be sent
into an SPI-compatible bit stream.
Listing 1, which is available at www.
edn.com/090917dia, contains the algo-
rithm in pseudocode, which translates
a hexadecimal string, DH, of characters
to an SPI signal. LD, LSS, and LCLK
are integers to define which data out-
puts represent the MOSI, CLK, and SS,
respectively.
Assuming a 24-bit register write
with two bits of overhead for the SS
prefix and postfix, the 64-kbyte mem-
ory can support more than 1000 SPI
transactions. The approach has two
additional advantages: The three lines
that form the SPI bus are under soft-
ware control, which provides cabling
flexibility, and the implementation
can support multiple slaves through
the use of additional SS lines. Fig-
ure 2 shows an MSO (mixed-signal-
oscilloscope) screen that shows the
SPI transaction. The SPI clock rate is
5 MHz, which the 34950A’s internal
10-MHz clock limits. The different
payload sizes correspond to writing
data toEquations for DI4530
16- and 24-bit (placed
registers in 8 − 20 folder)
within
the slave.EDN
Equations for DI4530 (placed in 8 − 20 folder)

R e fEquation
e r e n c1 e s
Leens,1Frederic, “An Introduction
Equation 1

to I²C and SPI Protocols,

1024D” IEEE In-
R WA (D) = × R AB ,
strumentation & Measurement,
1024D1024
R WA (D)12,
Volume = No. 1, February
× R AB , 2009,
1024
pg 8, www.imm.ieee-ims.org/docs/
ColumnsFebruary2009.pdf.
Equation 2
Equations for DI4530 (placed in 8 −220“SPI
folder) Guide V04.01,” Freescale
Block
Equation 2
Semiconductor, JulyD2004, www.
) (D) = 1024 × R AB .
R WB
freescale.com/files/microcontrollers/
Equations for DI4530 (placed in 8 − 20 folder
Figure 2 An MSO screen shows the SPI transactions using the digital-I/O lines. D
Equation 1 doc/ref_manual/S12SPIV4.pdf.
R WB (D) = × R AB .
1024
Equation 1 1024D Equation 3
R WA (D) = × R AB ,
1024
Equation 3
Resistive DAC and op amp R WA (D) =
1024D
1024
× R AB , R WA data
TheApotentiometer’s
V = 1+
R
=
1024sheet pro-
.
vides the R 1024 Dparasitic ca-
ground-referred
form hybrid divider WA WB
Equation 2 A V = 1 + at the
= .
pacitancesR WB A, D B, and W termi-
nals of the potentiometer. Thorough
Marián Štofka, Slovak University of Technology, Bratislava,
Equation 2 D Slovakia measurement
Equation of
4 the capacitances at
R WB (D) = × R AB .


A resistive DAC in a resistive- tween the ends of1024 the digital potenti- these terminals provides enough data
D Equation 4
feedback loop of an op amp lets ometer. The(Dcircuit
R WB ) = uses × Rresistance RWA to determine capacitances
1024 between the
AB . =V
you create an analog-digital-analog as a feedback resistor, 1024 and resistance VOUTAn
terminals. IN ×
evaluation .
Equations for DI
DI4530
4530 in 88−−20 1024 D of the mea-
divider. The resistance,
Equations for RWA((placed
,placed
between
in 20
RWBfolder
))
Equation
connects
folder 3
between the inverting sured
V data shows that. the direct capaci-
OUT = VIN ×
the W and A terminals of the Analog input of the op amp and ground. The tance between the D A and W terminals
Devices (www.analog.com) AD5293 voltage gain of 3the
Equation R noninverting
1024 am- at theEquation
midscale 5position of the wiper is
Equation A V = 1 + WA = .
(Figure
Equation 11
1) decreases linearly with in- plifier becomes R WB D just 2.4 pF:
creasing the digital-control data, D: R WA 1024 Equation 5
AV = 1 + = . C AW (X = ½)  2.4 pF.
1024D
RRWA D))==1024D ××RR AB,,
WA((D
R WB D
1024 AB If you
C AW = ½)  2that
(X assume .4 pFthe
. five segments
1024 Equation 4
The output voltage is of the potentiometer are ordered topo-
and the value of the RWB, the resistance Equinto
logically ationa6chain, then the direct
Equation 4 1024
between the W2and B terminals of the
Equation VOUT = VIN × . intercapacitance
Eq uation 6 between the A and B
Equation 2 D
DAC, rises proportionally to D as ends of (X = ½)  ½isC AW (X = ½)  1.2 pF.
potentiometer
C AB
Both the input 1024
D VOUT = Vvoltage
IN ×
and. the digital-
C AB (X = ½)  ½C AW (X = ½)  1.2 pF.
RRWB D))== D ××RR AB..
WB((D input data can be time D variables, and
1024 AB
1024 Equation 5 for fetching digital-
the clock frequency The capacitance
Equation 7 per segment of the
RAB is a constant value of resistance be- input data can be as high as 50 MHz. five segments of the potentiometer is
C AW (X =5 ½)  2.4 pF.
Equation Equation 7
Equation 33 C SEGM  5C AB (X = ½)  6 pF,
Equation
C AW (X = ½)  2.4 pF. C SEGM  5C AB (X = ½)  6 pF,
48 EDN A
| septemberRR WA 17,
1024
1024
2009 Equation 6
A VV ==11++ RWA == D .. Equation 8
R WB
WB D
Equation 8
 Equuation 6
C AB (X = ½)  ½C AW (X = ½)  1.2 pF.
n6
C AB (XEqu
= u½ation
)  ½6C AW (X = ½)  1.2 pF.
= ½)  ½C AW (X =Equation
½) C1.2 7pF
(X. = ½)  ½C = ½)  1.2 pF.
AB AW (X
Equation 7
C SEGM  5C AB (X = ½)  6 pF,
AD5293 AD8677
n 7 Equation
C
where 1 5C
 (7X = ½)  6 pF,
X5 ⁄2 denotes
SEGM AB the midscale of 5 OR 3.3V 15V

the resistive
 5C AB (X = ½)  6Equation
DAC.
pF, C 8  5C (X = ½)  6 pF,
VLOGIC
The five-step
SEGMdistributed
AB RC line of
theEquation
potentiometer
8 has a time constant RESET
R
of τSEGM = AB × C SEGM = R AB × C AB =DIGITAL
24 NSEC
INPUT,
n 8 5 8
Equation CA 100 nF
R 8 6 1 3
τSEGM = AB × C SEGM = R AB × C AB = 24 NSEC, Y 10 A
R AB 5 SDIN VDD 47 pF
= × C SEGM = R AB ×τ C AB ==24R AB
NSEC 11 NC
5 Equation
SEGM9 × C,SEGM = R AB ×SPI
C AB = 24 NSEC,12 SCLK
5 SYNC NC
where RAB is9 20 kV. The ground-re-
Equation
13
SDO
1
8
W 4 2 7
τWwiper
ferred  R WB × CW .
capacitance, CW, of 40 pF NC
14 � 5
RDY CW 6
EXT_CAP OUT
n9 is much higher than the intercapaci- 7
τW  REquation 9 3
WB × C W .
tances and creates a time constant: GND VSS B � 4
1 �F 100 nF
9 2 5
WB × C W . τW  R WB × C W . CB
ANALOG INPUT 100 nF
The feedback network of the amplifier X
is frequency-compensated for tSEGMQ
tW. Thus, you can calculate the value
of RWB as 600V, meaning that the volt- �15V
age gain of the amplifier, AV, is 32.3.
For gains higher than 32.3, the effect of Figure 1 The resistive DAC-potentiometer forming the feedback for an op amp
CW becomes negligible, and you need controls the op amp’s gain as inversely proportional to the digital-input-data
not bother about amplifier stability. To word. The circuit thus becomes a two-quadrant divider.
suppress the derivative behavior of the edn090820di45301 DIANE
amplifier for gain values of two to 32.3, dard SPI (serial-peripheral interface).
(PLACED IN which equals 0110, and you put the
9-3 FOLDER)
you can add a 40-pF compensating ca- After power-on, you must initially neu- desired C2 and C1 values at data po-
pacitor in parallel to feed back part of tralize the write-in protection of the sitions D2 and D1. After performing
the potentiometer. The amplifier thus resistive DAC. You have to first pro- these steps, you change the wiper posi-
has an integrating character for all gram the control bit C1 to the value of tion in which the control bit is C3, C2,
gains down to a value of two. one, whereas it is zero by default. You C1, and C0, which equals 0001, and the
You fetch the divisor, Y, which is a achieve this task by clocking in the data bits, D9 to D0, represent the gain
digital-data word, D, through a stan- word containing C3, C2, C1, and C0, as 1024/D.EDN

Connect two buttons

VCC

with just two wires IC1

4N35 6
R3
10k
R4
10k
DOUTS1
1
Fikret Yilmaz, Mobil Elektronik, Istanbul, Turkey 5


R1 DOUTS2
1 T1 1k
Sometimes, you need to read the status of 13 2 4
12 TO �12V
pushbuttons that are as much as 5m away AT 30 mA
7
from your electronic circuit. That task is easy if 9
R2
IC2
4N35 6
you have just one button. You simply design a 1k
1
constant-current source, connect the current line 5

from your button, and measure the current in the 2 4

line. If you press the button, current flows through S1
it. Otherwise, current does not flow.
Problems occur, however, when you need to 1 2 D1
1N4004
read two or more buttons. Several approaches S2

to this problem are available. For example, you 1 2 D2

1N4004
could use an RS-485 interface with two wires
for communication and two for power. Alterna- Figure 1 You can connect two buttons using diodes.
tively, you could use a single-wire connection

edn090903di45311 september
DIANE 17, 2009 | EDN 49
(PLACED IN THE 9-17 FOLDER)
designideas
VCC
with one wire for communication and
two for power. Another option is to
IC1 R3 R4 use separate wires for each button.
4N35 10k 10k
1
6
DOUTS1 In that case, you would use one more
R1
5 DOUTS2 wire than there are buttons. Finally,
1 T1 1k you could use a POE (power-over-
13 2 4
12 TO �12V
AT 30 mA
Ethernet) approach, employing four
7 9
R2
IC2 wires for communication and power.
4N35 6
1k
1
All of these approaches require a but-
5 ton reader or a controller, which you
2 4 VCC must program, adding complexity and
cost.
S1
The circuit in Figure 1 shows you
1 2 D1 IC3
4N35
R7
10k
R8
10k
how to connect two buttons using di-
1N4004 6
S2 1 DOUTS3 odes. Because the diodes steer the cur-
1 2 D2 R5
5
DOUTS4 rent, the circuit needs just two wires.
1N4004 1k 2 4 On a positive cycle from the trans-
former secondary and with switch S2
R6
IC4
4N35 6
closed, current flows through IC1, R2,
S3 1k 1 and D2. Thus, output DOUTS2 pulls low.
5
1 2 D3
Conversely, if S1 closes on a negative
1N4004 2 4 cycle, then current flows through D1
S4
to R1 and IC2, which pulls DOUTS1 low.
D4
1 2
1N4004 The circuit in Figure 2 extends the
concept to four pushbutton switches
Figure 2 By adding a third wire, you can connect four pushbutton switches. by adding a third wire.EDN

edn090903di45312 DIANE
(PLACED IN THE 9-17 FOLDER)

50 EDN | september 17, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Unused port adds a PWM/analog D Is Inside

channel to a microcontroller 44 Capacitance meter uses PLL
for high accuracy
Vishwas Vaidya, Tata Motors Ltd, Pune, India 50 Resistor compensates


Low-cost, 8-bit, single-chip
micro­controllers are stingy
when it comes to on-chip PWM (pulse-
width-modulation) resources. The use
of a PWM resource often forces a de-
signer to sacrifice a capture/compare or
timer channel because the PWM chan-
nel shares the same on-chip hardware.
This Design Idea describes how you
can use an on-chip unused synchro-
for instrumentation-amp gain
drift
ETo see all of EDN’s Design
Ideas, visit www.edn.com/design
ideas.

OTHER I/O
INTERFACES
PWM OUTPUT ON nous serial port to generate PWM sig-
SYNCHRONOUS nals and convert them to a slow-mov-
TRANSMIT DATA ANALOG ing analog signal (Figure 1). Many
OUTPUT
MICROCONTROLLER microcontroller-based stand-alone
PULSE-WIDTH electronic units don’t use the synchro-
DEMODULATOR
RC-LOWPASS-FILTER nous serial port. Thus, you can use the
NETWORK microcontroller’s baud-rate generator
and parallel-to-serial-converter blocks
to generate bit patterns to form a 256-
Figure 1 You can use an on-chip unused synchronous serial port to generate bit PWM pattern. You can then filter
PWM signals and convert them to a slow-moving analog signal. the PWM output with an RC filter to
extract an analog signal (Reference 1).
The synchronous com-
munication is devoid of
edn090820di45451 DIANE the start and stop bits
(PLACED IN THE 9-3 FOLDER)
256-BIT PWM CYCLE1 of asynchronous mode,
so the bit pattern can
TOTAL BYTES=20 ON-STATE BYTES+TRANSITION BYTE+11 OFF-STATE BYTES=32
generate long periods of
high or low level.
20 ON-STATE BYTES WITH VALUE 0�FF2 TRANSITION BYTE3 OFF-STATE BYTES 0�004 You can generate raw
00011111B data with a decimal
value of 165 using this
concept (Figure 2). A
PWM-conversion cy-
cle consists of generat-
1
RAW DATA=165; ON-STATE=5V; OFF-STATE=0V. ing 256 bits—that is,
2
NUMBER OF ON-STATE BYTES=165/8=20 (INTEGER DIVISION). 32 bytes. The number
REMAINDER=165�(8�20)=165�160=5.
3
TRANSITION BYTE=00011111B=0�1F (NOTICE FIVE ONES FROM LSB SIDE).
of “on” bits corresponds
4
NUMBER OF OFF-STATE BYTES=TOTAL 32 BYTES�ONE TRANSITION BYTE to the value of the raw
�20 ON-STATE BYTES=32�1�20=11 BYTES.
ANALOG OUTPUT AFTER LOWPASS FILTER=(165/256)�5=3.22V.
data to convert into
PWM. Hence, for 165
Figure 2 You can generate raw data with a decimal value of 165 using this concept. bits as the raw data,
165 bits are on and 91

OCTOBER 8, 2009 | EDN 43

designideas
period. In this case, the circuit needs
five more on bits: 160155165.
COMPUTE VALUES FOR VARIABLES FOR PWM GENERATION
Hence, the transition byte should have
ON-BYTE COUNT=RAW DATA/8 a 00011111b pattern (byte5031f).
REMAINDER=RAW DATA�8�(ON-BYTE COUNT) Figure 3 illustrates the process in
FORM TRANSITION BYTE BASED ON REMAINDER VALUE1
OFF-BYTE COUNT=31�ON-BYTE COUNT2
flow-chart form. You can tailor the
PWM frequency to your application
by selecting a crystal, PLL (phase-
locked loop), and baud rate. A simple
OUTPUT 0�FF BYTES (TOTAL NUMBER=ON-BYTE COUNT) ON
SERIAL-TRANSMIT OUTPUT PIN, FORMING THE BULK OF THE RC filter can convert the PWM into
ON-PERIOD OF A PWM DUTY CYCLE a slow-moving analog value. Although
this idea describes an 8-bit PWM, you
can increase or decrease resolution by
OUTPUT THE SINGLE TRANSITION BYTE, MARKING THE changing the total bits per PWM cy-
TRANSITION FROM ON-PERIOD TO OFF-PERIOD OF THE PWM cle. You correspondingly increase or
decrease the conversion time.
Listing 1, which is available at www.
OUTPUT OFF-PERIOD BYTES 0�00 (TOTAL NUMBER=OFF-BYTE edn.com/091008dia, provides a sample
COUNT) code for illustrating the concept. The
code uses the Microchip (www.micro
chip.com) PIC18F4525, which has a
END OF PWM CYCLE 4-MHz crystal and 10-kHz baud rate
for the synchronous serial communica-
tion, yielding 10,000/256539.31 Hz of
1
TRANSITION BYTE CONSISTS OF A NUMBER OF ONE BITS STARTING FROM LSB. PWM frequency. You can filter it with
REMAINING BITS ARE ZERO. THE VALUE OF THE REMAINDER DECIDES THE
NUMBER OF ONE BITS. IF THE REMAINDER IS THREE, THE TRANSITION BYTE IS a 0.1-sec RC filter, which is sufficient
00000111B. FOR A REMAINDER OF FIVE, THE TRANSITION BYTE IS 00011111B. for slow-moving analog signals, such
THE LSB TRANSMITS FIRST. as speed setpoints for motion-con-
2
FOR A SINGLE PWM CYCLE, TOTAL BITS=256 AND TOTAL BYTES=256/8=32. trol applications. By using a 20-MHz
BECAUSE THE TRANSITION BYTE OCCUPIES 1 BYTE, THE OFF-BYTE COUNT= crystal, you can achieve synchro-
31�ON-BYTE COUNT.
nous serial baud rates greater than 1.5
MHz and PWM frequencies of a few
Figure 3 You can tailor the PWM frequency to your application by selecting kilohertz.EDN
a crystal, PLL, and baud rate.
R e fe r e nce
bits are off. To generate a 165-bit on- ing the 21st, or transition, byte. This 1 Mitchell, Mike, “Make a DAC with a
period, the first 20 bytes—that is, 160 byte has some of its LSBs (least signifi- microcontroller’s PWM timer,” EDN,
bits—transmit as 03ff on-state bytes. cant bits) as ones and the rest as zeros Sept 5, 2002, pg 110, www.edn.
The trick lies in judiciously compos- to form the required length of the on- com/article/CA240913.

Capacitance meter uses PLL with the PLL (phase-locked loop). IC1,
an Analog Devices (www.analog.com)
for high accuracy AD8033 op amp, does the job because
of its 1000-GV input impedance and
Jim McLucas, Broomfield, CO 1.7-pF input capacitance. It also has
only 50 pA of input bias current over


An old Electronics Designer’s 10 pF to 10 mF with high accuracy. It temperature. Its 80-MHz bandwidth
edn090820di45453 DIANE
Casebook described a(PLACED
circuit IN
that needs
THE 9-3 no microprocessor; thus, it needs
FOLDER) and 80V/msec slew rate are more than
provided capacitance measurements of no code. Even in the 1- to 10-pF range, enough for this application. It can op-
10 pF to 1 mF with 1% accuracy (Ref- the circuit is accurate to about 61 pF erate with just an 8V power supply.
erence 1). A number of issues emerged when reading values as low as 5 pF. Unfortunately, the AD8033 is avail-
with the circuit during testing, and this The circuit requires a high-input- able only in surface-mount packages,
Design Idea describes an improved cir- impedance device to interface with which makes breadboarding some-
cuit. The meter circuit in Figure 1 (pg the high-value resistors, R6, R8, R9, and what tedious. IC2, an Analog Devices
48) lets you measure capacitance from R10, and a fast comparator to interface ADCMP601 comparator, interfaces

44 EDN | OCTOBER 8, 2009

designideas
with the AD8033 op amp and IC3, a
74HC4606A PLL. The comparator
has a typical propagation delay of only
4.3 nsec. It has built-in hysteresis and
needs only a 5V supply. It is also avail-
able only in surface-mount packages.
The capacitance meter generates
two signals; one of them lags the oth-
er by 608. A 3-bit, self-correcting, di-
vide-by-six twisted-ring counter com-
prising IC6, IC7, and IC13B provides the
lagging signal. The lagging signal con-
nects to the COMP input of the PLL
(Pin 3), and the other signal is applied
to an RC circuit, which provides a 608
phase lag before it gets to the SIG in-
put of the PLL (Pin 14). The PLL ad-
justs the frequency of its VCO (volt-
age-controlled oscillator) so that the
two input signals are in phase. The
resulting period of the VCO’s output
signal (Pin 4) is proportional to the
measured capacitance.
On the low-capacitance range, sig-
nals with frequency FO are applied to
the PLL. On the high-capacitance
range, the frequency is FO/1000. IC8
through IC 10 provide the division,
and S2, IC4B through IC4D, IC5D, IC5E,
and the associated components pro-
vide the high-capacitance/low-capac-
itance range switching. The VCO of
the PLL runs at 6FO. The circuit di-
vides this signal by three to provide
an output with a period that’s propor-
tional to the measured capacitance.
It provides the correct digits when
you measure with a frequency coun-
ter that you set to measure the peri-
od. You can calculate FO or FO/1000
from 0.1505/RXCX, where RX is R6, R8,
R9, or R10, depending on the selected
range.
The 74HC4046A PLL can exhibit
several problems. For example, it may
not start when you apply power, or
it may hang with the VCO running
with the VCO-input pin (Pin 9) stuck
high or low. The start-up circuitry,
TABLE 1 capacitance measurements
Range 1 to 10 pF 10 to 100 pF
Capacitance 5.24, 10.04, 23.22,
10.04 47.6, 102.68
Measurement 18.85, 6.37, 14.78,
error (%) 2.89 13.68, 10.61
comprising IC13F, Q4, and associated
components, applies a positive volt-
age of approximately 2V to the VCO’s
input, which forces the VCO to os-
cillate. After the VCO starts, D4 be-
comes back-biased, which disconnects
the start-up circuitry from the VCO’s
input pin. If the VCO is running but
hung with its input stuck high or low,
one-shot IC12A detects that it’s not
phase-locked by responding to pulses
The 74HC4046A
PLL may not start
when you apply
power.
from Pin 1 of IC3. The one-shot then
issues a 1.5-sec pulse that causes IC12B
to produce a 0.5-sec pulse that causes
either a positive pulse at the inhibit
pin or a low pulse at the VCO’s in-
put pin, depending upon whether the
PLL is low or high. After the 0.5-sec
pulse ends, the pulse from IC12A con-
tinues for 1 sec, giving the PLL time
to lock. LED D7 indicates phase lock.
If the PLL phase locks, all is well. If
it does not, the IC12A/IC12B one-shots
continue issuing pulses. Experiments
determined these methods for recov-
ering from the anomalous states. It’s
possible that the circuit won’t always
recover, but these methods have been
effective on the test unit.
The circuit applies the 6FO signal,
divided by three, to buffer IC5F’s Pin
5. This action provides an output fre-
quency whose period is proportional
to the value of the measured capaci-
tance. The output provides the correct
digits without regard to the location of
the decimal point. To determine the
value of the unknown capacitance,
observe the setting of S1 and S2.
You can calibrate the circuit by us-
100 to 1000 pF 1000 to 10,000 pF
102.68, 1022.1, 5226.9,
469.32, 1022.1 10,140
10.86, 12.5, 10.89, 11.28, 0
10.7
ing a capacitance of a known value
of approximately 1000 pF, with S2 at
the low-capacitance position and S1
at the 100- to 1000-pF/0.1- to 1-mF
position. Set R22 at its midposition,
connect a frequency counter to Pin 6
of IC5F, and set the meter to measure
the period of the signal. Adjust R12 for
a period whose digits agree with the
known value of capacitance. Next,
use a capacitance of approximately
100 pF and set S1 to the 10- to 100-
pF/0.01- to 0.1-mF position. Record
the measured value of the capacitor.
Then, using the same capacitance of
approximately 100 pF, set S1 to the
100- to 1000-pF/0.1- to 1-mF position
and adjust R22 to get the same value
as you obtained on the 10- to 100-pF/
0.01- to 0.1-mF position. The R22/C13
combination provides a small variable
delay relative to the signal at Pin 14
of IC3. This fine adjustment improves
accuracy in the lower range.
Employing measurements made
with the available equipment, which
did not include an accurate, high-res-
olution capacitance meter, this me-
ter is accurate to approximately 62%
over 100 pF to 10 mF (Table 1). The
accuracy degrades over 10 to 100 pF
because of the input capacitance of
the op amp and the associated para-
sitic capacitance at IC1’s Pin 3. R7 and
C6 provide some compensation at the
10- to 100-pF range for the inherent
capacitance at that node. R5 and C5
provide compensation at the 1- to
10-pF range.
You can also measure the inherent
capacitance and then subtract it from
the reading on the two lower ranges.
If you take this approach, omit R5, R7,
C5, and C6 from the circuit. Then, with
S1 at the 1- to 10-pF range and S2 at
the low-capacitance position, you can
measure the capacitance at that node
with no external capacitance. The in-
(continued on page 50)
0.01 to 0.1 mF 0.1 to 1 mF 1 to 10 mF
0.01014, 0.10052, 1.034,
0.10052 1.034 10.07
0.89, 0.88 2.27, 2.03,
10.87 1.24
OCTOBER 8, 2009 | EDN 47
designideas
R5
C5
270k
4.7 pF
1%

R6
301k
1% S1
8V C7
1 TO 10 pF 1 �F 5V 5V
R7 C10
5V C6 R11
270k C8 0.1 �F
4.7 pF 510
C4 1% 0.001 �F
0.1 �F
R8 R12
30.1k 500 6�
1% 4
Q2
5 � ADCMP601
4� � IC2 1
C2 R3 1 3
10 TO 100 pF/0.01 TO 0.1 �F IC1 5
39 pF 4.7k FO OR 2N3906 3 �
R9 � AD8033
�
FO/1000 � R13 2
3.01k 2 C9
C3 R4 AT 0� 1.5k
2N3904 1% 100 pF R14
39 pF 4.7k
82k
Q1 100 TO 1000 pF/0.1 TO 1 �F CX
R10
301
1% R22 IC13D IC13E
1k 74HC04 74HC04
IC13A 13 12 9 8
74HC04 1000 TO 10,000 pF/1 TO 10 �F
C13
6 5
IC13B 47 pF
74HC04
2 IC13C
1
74HC04 C14
6FO OR 6FO/1000 4 3 R24 2N3904
0.22 �F 4.7k
11 10 Q4
5V D3 R25
IC13F
R21 4 1N914 4.7k
IC6 74HC04
2.2k PRE
74HC195 2 5
1 D IC Q
7A
MR 74HC74 6
9 3
PE CLK Q
10 CLR
CP
2 J 1
3
K
4 15 10
D0 Q0
5 14 PRE
D1 Q1 IC8 IC9
6 D2 13 12 9
Q2 D IC Q 74HC192 74HC192
7 D3 12 7B
14 14
Q3 74HC74 8 MR MR
11 11
Q3 CLK Q 5 5
CPU CPU
4 4
CLR CPD CPD
11 11
13 PL 12 PL 12
TCU TCU
13 13
TCD TCD
15 3 15 3
D0 Q0 D0 Q0
1 1
AMIDON FB 101 D1 Q1 2 D1 Q1 2
10 6 10 6
FERRITE BEAD L1 D2 Q2 D2 Q2
5V 9 7 9 7
IC5D IC4C D3 Q3 D3 Q3
74HC04 74HC00 IC4D
9 8 5 74HC00
HIGH LOW 6 13
CAPACITANCE CAPACITANCE IC5E IC4B 4 11
S2 74HC04 74HC00 12
R 11 10 2
26
18k 3
1
6FO/1000
C16 R27 C17 6FO
0.1 �F 47k 0.01 �F

Figure 1 A capacitance meter connects to a frequency counter measuring pulse width to provide a capacitance measurement.

ed
(PL
48 EDN | OCTOBER 8, 2009
 5V

IC3 D2
74HC4046A 5V R18
1k 1N914
VCC 16
PLL �
2 4 3
PC1
14
SIG PC2 13 IC5A
FO OR FO/1000 1 74HC04
PCP R15 2N3904
AT �60� 3
COMP PC3 15 22k D1
Q3
C1 1N914
1300 pF VCO 9
6
5% C1A VCO 4 8
5V 7
C OUT C12 R19 10
11 1B 0.22 �F 2k 5V
R1 IC4A
12 DEM 10 R17 R20
R2 74HC00
R23 9 OUT 100k 4.7k
R1 VCOIN
82k R2 5
3.4k INH
1M 8 R16
1% VSS D5
56k C11 1N914
0.47 �F
IC5B
D6
D4 74HC04
1N914
1N914 1 2

5V
IC12A HLMP-1321
C15
R33 74HC4538
0.22 �F 6FO R32 LOCK
220k
220k 2 RX/CX INDICATOR
C20 D7
R31 20 �F
R30 220k
10k 10%
5V � 1 CX R34
5V IC5C 330
R29 74HC04 S
R28 6
2.2k 12 13 4 A Q
2.2k
5 B T
7
C18 C19 Q
IC10 IC11 R
0.01 �F 100 pF
74HC192 74HC163
14 1 3 R
MR R
5 9
CPU PE IC12B
4
CPD 7 74HC4538
11 CEP
PL 10
12 CET 14 RX/CX
TCU 2 CP
13 C21
TCD DIVIDE BY 3 6.8 �F
15 3 3 14 10%
D0 Q0 D0 Q0 15 CX
1 4 13 �
D1 Q1 2 D1 Q1
10 6 5 12
D2 Q2 D2 Q2 S
9 6 D3 11
D3 Q3 7 Q3 12 A Q
10
15 T
TC 11 B 9
Q
R
13 R
C22 �
20 �F
6FO 10%
IC5F
74HC04
5 6 2FO TO COUNTER (MEASURE THE PERIOD)

dn090820di45441 DIANE
LACED IN THE 9-17 FOLDER)
OCTOBER 8, 2009 | EDN 49
designideas
(continued from page 47)
trinsic capacitance of the test circuit is
2.8 pF. Using this correction, the val-
ues you obtain on the lowest two rang-
es are accurate to approximately 62%,
or 61 pF.
You must observe capacitor polarity
when measuring electrolytic capaci-
tors. Connect the negative end of the
protection, so be sure to discharge the
capacitors before connecting them to
the capacitance meter and use an ESD
wrist strap to avoid damaging the cir-
cuit. For best results, you need accu-
rate and stable 5 and 8V power sup-
plies. Both supplies should be accurate
to 62%. You can raise the 8V supply
to 9V and relax the accuracy to 5%. If
performance of the meter. You must,
however, maintain the 5V supply at
a constant, accurate value. Note that
all of the ICs except IC1 have 0.1-mF
bypass capacitors from their 5V pins
to ground.EDN
R e fe r e nce
1 Pyle, Ronald E, “Phase-locked loop

capacitor to the grounded terminal. you use a 9V battery to supply the 8V, aids in measuring capacitance,” Elec-
Also, the circuit provides no overvolt- you can let the voltage drop to about tronics Designer’s Casebook, No. 4,
age or ESD (electrostatic-discharge) 7.9V before adversely affecting the pg 32.
Equations for DI4523 (placed in the 9 − 3 folde

Resistor compensates Equation 1

sheet (Reference 1) is

for instrumentation-amp gain drift GAIN = 1for

Equations
49, 400
+ DI4523
RG
. (placed in the 9 − 3 folder
Kenneth Gustafsson, Karlskoga, Sweden
From this gain-set equation, you can


Some instrumentation amplifi- As an example, Analog Devices’ assume Equations
that the for chipDIuses
4523 (placed
two in the 9 − 3 folder)
24.7-kV
Equation
Equations
Equation 12 for DI4523 (placed in the 9 − 3 fo
ers use external resistors to set (www.analog.com) AD8295 has a drift resistors with the external gain resis-
Equations for DI4523 (placed in the 9 − 3 fo
their gain. Unfortunately, the lack of of as much as 250 ppm/8C, even if for
Equations youDI4523
tor, R(placed
G
, to setinthe
the49amplifier’s
3 foldergain.
9 ,−400 ) The
temperature-coefficient matching be- use a zero-drift gain-setting resistor. In chip has Equation
GAIN 11+ 20-kV
two =more 49, 400 . resistors.
(1 + ∆)  Be-
 2 × RA
tween the external and the internal this Design Idea, you can compensate cause all GAIN
of = 1 +chip
Equation
these 1R G resistors are  1of+
Equation  1 they R G  20, 000 (1 + ∆)
resistors results in a high gain drift. If, this drift with an extra zero-drift resis- the same magnitude, 49, 400 probably
Equation 1 GAIN = 1 + 49,.400
however, another on-chip resistor is tor in combination with an internal will have good temperature-coefficient
GAIN = 1R+G49, 400 .
available, you can use it to compensate chip resistor. matching, and you
Equation
GAIN 2= 1can
+ use R G this. match-
for gain drift as a result of temperature. The gain-set equationGAINfrom the 49, 400 for Equation 3 RG
= 1 +data ing . compensation. If the amplifier
R G resistance, R , and the gain resistor are
Equation A  49, 400 (1 + ∆)   2 × RA 
GAIN
zero-drift 400= 21 +R
49,resistors  1 +
Equation= (Figure
2A , 1), then 
REquation
G
 10,2000 R G   20, 000 (1 + ∆) 
VS A2�IN A2�IN
Equation 2  49, 400 (1 + ∆)   2 × RA 
16 15 14 13 GAIN = 1 +  49, 400 (1 +∆ 1 )+  2× R ,
GAIN = +
  49,G400 (1 +
1 R 
 ∆)   201 ,
+ 000 (1 + ∆)A
2 × R A
AD8295  49, 400 (1 + ∆
GAIN34= 1 +
Equation
Equation
)  2 × R A RG
RG  1 + 20, 000 (1 +
GAIN = 1 +  1 + ,   20, 000 (1 +
�IN 1
12 A2 OUT 
�
+ ∆
�

 R G 49, 400 20 , 000 (1 ) 

A2 Equation=349R , 400
A ,
2
INSTRUMENTATION where RD RG
G =
is the
Equation drift
10, 000 3 of ; the internal
AMP EquationGAI 3N11
�
matched resistors.
49, 400 RA If
Equation 3
R 49,=400 R,
RG
11 G49, 400 ,=000R A ,
10
EquationR G 45= 10, 000 A ,
49, 400 RA Equation
� RG 10, 000
=
�
10 ,
RG 10, 000 then the first-order drift of the gain
49 , 400
( )
3 A1 R1
Equation
cancels,
RRGand the4, 000
gain splits equally
11 . be-
20k A== 10 GAIN
;
� Equation
tween theEquation GAIN411
instrumentation amplifier
�IN 4 4
R2 9 and A1. Solving 49, 400
for RG and RA yields
20k Equation 4 RG = 491 ;
, 1400
R GGAI
Equation = 6N 49 , 400 ;
5 6 7 8 Equation
R G = 5 GAIN11;
RA 49 , 400 GAI N 1 1
�VS RG = ;
GAIN11
A = 10=
Equation
RGAIN ,5000
1 + GAIN11 .  (
 49, 400 (1 + ∆))   2 × R A
) 
=
Equation  5 RG   20, 000 (1 + ∆) 
For gainEquation
greater 5than 100, the am-
OUT
Equation 5 A = 10, 000becomes
plifierRresistance GAIN ( 11 . than )
(( ))
greater
R A =610, 000 GAIN11 .
Equation
Figure 1 In this configuration, the first-order drift of the gain cancels, and the 90 kV, whichR A =can 10, 000 be problematic.
GAIN11 .In
gain splits equally between the instrumentation amplifier and A1. R = 10, 000 GAIN
A
this 1 1(
case,.
ing configuration
Equation 6 49
)
you can use A1 in an invert-
with, 400a (gain
1 + ∆))of
 21 2 × R A  
GAIN = 1 + 6
Equation  =
edn090903di45231 DIANE Equation 6 RG   20, 000 (1 + ∆)  
(PLACED IN THE 9-3 FOLDER)
Equation 6  49, 400 (1 + ∆))   2 × R  
GAIN = 1 +  49, 400 (1 +∆))   2A× R  = 
GAIN R
 = 1 + 49,G400 (1 + 20 , 000 (1 +
 ∆))   2 × R A ∆ )A
50 EDN | OCTOBER 8, 2009
GAIN = 1 + RG 20, 000 (1 + ∆)
 49
 49, 400 (1 + ∆))   2 × R A  
R G 1   20 000 (1 + ∆)
, 400
GAIN = 1 +  = + .
N11 Equation 5

designideas
( ) R A = 10, 000 GAIN11 .

0 ( GAIN11 . ) (Figure 2). With

Equation 6 an amplifier resis-
tance of 10 kV, A2�IN A2�IN
VS
 49, 400 (1 + ∆))   2 × R A   1 49, 400  16 15 14 13
GAIN = 1 +  = + .
 R  20, 000 (1 + ∆)   (1 + ∆) RG
AD8295 
G

49, 400 (1 + ∆))   2 × R A   1 49, 400  �IN 1 � 12 A2 OUT

�
+  = + .
RG  20, 000 (1 + ∆)   (1 + ∆) RG  INSTRUMENTATION
A2
2
AMP
This case sizes RG using a value from
�
the data-sheet formula. If the gain is 50,
RG
the internal matching and the negative 11
drift compensate the “49” part of the � �
10
gain, and the “one” part is just the drift
3 A1 R1
divided by 50 in the total gain, result- 20k
ing in a typical figure of 21 ppm/8C. �
�IN 4
In both cases, the resulting gain tem- R2 9
20k
perature coefficient can be less than 5
ppm/8C, which is 10 times better than 5 6 7 8
the original outcome.EDN �VS RA

R e fe r e nce
1 “AD8295: Precision Instrumentation
Amplifier with Signal Processing Ampli-
fiers,” Analog Devices, www.analog.
com/en/amplifiers-and-comparators/
instrumentation-amplifiers/ad8295/
products/product.html.
OUT
Figure 2 For gain greater than 100, the amplifier resistance becomes greater
than 90 kV, in which case you can use A1 in an inverting configuration with a
gain of 21.
edn090903di45232 DIANE
(PLACED IN THE 9-3 FOLDER)

52 EDN | OCTOBER 8, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Astable multivibrator gets hysteresis D Is Inside

from positive-feedback stage 45 Class B amplifier has
Robert Larson, Seattle, WA automatic bias


Many designs exist for logic- ues, and the process repeats. The tim- 48 Cable tester uses
based astable multivibrators, one ing depends on both the RC time con- LEDs to find faults
of the simplest being an RC feedback stant and the hysteresis resulting from 48 Dual-coil relay driver uses
loop around a single inverting Schmitt the spread between the two threshold only two MOSFETs
trigger inverter (Figure 1). The out- values (Figure 2). Unfortunately, al-
put charges the capacitor to the upper though inverter manufacturers speci- ETo see all of EDN's Design
switching threshold, at which point fy the hysteresis voltages in their data Ideas, visit www.edn.com/design
the output switches to its opposite sheets, the devices have a fairly large ideas.
state, the threshold switches to a dif- range. In addition, they likely have
ferent value, and the capacitor’s charg- some temperature dependence. These
ing current reverses direction. When uncertainties make it difficult to design teresis to let it overshoot the nominal
the capacitor’s voltage crosses the low- the circuit to have a predictable oscil- threshold, charges the capacitor to the
er threshold, the output and threshold lating frequency. threshold voltage and stops in its nar-
both toggle back to their original val- A simple inverter, without the hys- row linear region. At this point, the
negative feedback
TABLE 1 74VHC04 results from the invert-
Expected results Measured results ing output to the
Hysteresis Total Total input regulates
Timing ca- capaci- Hysteresis time Hysteresis time Total time the output to the
Resis- pacitance tance voltage period voltage period differential threshold voltage.
tance (kV) (pF) (pF) (V) (nsec) (V) (nsec) (%) Adding another
10 470 100 0.88 3462 0.75 2930 18 inverting stage in-
jects hysteresis of
10 470 220 1.59 6850 1.8 7340 17
a different form by
10 12,000 12,000 2.5 333,526 2.6 364,800 19 means of positive
0.3 220 220 2.5 221 1.75 240 18 feedback, which
1 12,000 12,000 2.5 34,086 2.5 36,000 15 external passive

R CAPACITOR VOLTAGE (V) OUTPUT VOLTAGE (V)

10k

A1 HYSTERESIS RANGE
VC
VOUT UPPER THRESHOLD

LOWER THRESHOLD
CT
100 pF

3.24 3.33 3.42 3.51 3.6 3.64 3.78 3.8

Figure 1 A basic astable multivibrator
TIME (�SEC)
uses a Schmitt trigger and an RC
network. Figure 2 A part’s hysteresis, in large part, determines switching thresholds.

edn090903di45261 DIANE EDN091022DI4526FIG2

(PLACED IN THE 9-3 FOLDER)
october 22, 2009 | EDN 43
designideas
parts determine (Figure 3). Thus, the relaxation time constant is diction then depends only on passive-
Whenever Stage 1 crosses its thresh- R(CT1CH) and the relaxation voltage component values and their toleranc-
old, the extra Stage 2 injects an addi- is either VCT5(VTHRESH1VHYST2VLOW) es, temperature, and aging coefficients.
tional charge through a feedback ca- exp(2t/R(CT1CH)) or VCT5(VHIGH The series combination of CT and CH,
pacitor to make the timing capacitor’s 2 ( V T H R E S H 2 V H Y S T ) ) e x p ( 2 t / however, presents a capacitive load to
voltage jump past the threshold. The R(CT1CH)), depending on which half- Stage 2. This load affects Stage 2’s rise
RC charging current reverses direction cycle is occurring. You calculate the time and fall times, the sum of which you
to get back to the threshold voltage. from VTHRESH1VHYST back to VTHRESH as must add to the total period, T.
When it gets there, the hysteresis-in- t152R(CT1CH)ln((VTHRESH2VLOW)/ In the case of CMOS parts, such as the
jection circuit again jumps the voltage (V THRESH1V HYST2V LOW)). For the 74VHC04 from Fairchild Semiconduc-
past the target so that the RC timing other half-cycle, t 252R(C T1C H) tor (www.fairchildsemi.com), rise and
circuit must again reverse the charg- l n ( ( V H I G H 2 V T H R E S H ) / ( V H I G H 2 fall times depend on the output resis-
ing current to seek the threshold volt- VTHRESH1VHYST)). tance of the part as well as on the exter-
age (Figure 4). This process continues You should add the total propagation nal components. If you model the Stage
endlessly at a fairly predictable rate. time (tPLH1tPHL) through stages 1 and 2 output as an RC circuit, you can esti-
In the equations, CT is the timing ca- 2 to the total period. Unless you want mate the 10 to 90% exponential rise and
pacitor, CH is the hysteresis capacitor, the circuit to operate at its maximum fall times as tRISE25tFALL252.2RO(CTCH/
VTHRESH is the threshold voltage, VLOW frequency, these propagation times be- (CT1CH))1tO, where tRISE2 is the rise
is the low output voltage, and VHIGH is come insignificant. The period pre- time, tFALL2 is the fall time, RO is the out­
the high output voltage. put resistance of the part—30V for
You can view the hysteresis-over- CH the 74VHC04—and tO is the no-load
shoot voltage, VHYST, as the result 100 pF rise time—in this case, 4.5 nsec for
of a capacitive voltage divider that the VHC04. Thus, the total period is
R
timing capacitor CT and hystere- VCH t11t212(tPLH1tPHL)1tRISE21tFALL2.
10k
sis capacitor CH form. When Stage Also note that the timing depends
1 toggles Stage 2, its output jumps VCT on inverter output voltages and the
from a low value to a high value or VSTAGE1 VSTAGE2 location of the threshold voltage
from a high value to a low value by within that range. For example, a
an amount of V HIGH2V LOW, and STAGE 1 STAGE 2 CMOS part whose outputs are close
CT
the voltage of the timing capacitor 470 pF
to the power rails is more predictable
jumps by VHYST5(VHIGH2VLOW)(CH/ than a TTL (transistor-transistor-log-
(CH1CT)). Second, the voltage of the ic) part, and a 74HC part with a mid-
timing capacitor relaxes back toward point threshold voltage has a more
Stage 1’s output voltage by drawing Figure 3 The addition of a positive- symmetric output than an HCT part
current through both the timing ca- feedback stage provides hysteresis to a whose threshold voltage is offset for
pacitor and the hysteresis capacitor. simple inverter stage. TTL interfacing.

edn090903di45262 DIANE
(PLACED IN THE 9-3 FOLDER)

Figure 4 Hysteresis results from a charge burst from Stage 2 that jumps the timing-capacitor voltage past the switching threshold
by a known, fixed amount.

44 EDN | october 22, 2009

 For higher frequencies, you must
use smaller resistor values, smaller
timing-capacitor values, or both. For
predictable results, the value of the
timing capacitor should be no less
than 10 times the inverter’s input ca-
pacitance, which ranges from 3 to 10
pF for a typical CMOS, and R should
not be so low that it significantly
loads down the output. As a precau-
tion, the value of the hysteresis ca-
pacitor should not exceed that of the
timing capacitor so that it does not
exceed the maximum input voltage
on Stage 1. If the value of the hyster-
esis capacitor were much greater than
that of the timing capacitor, then the
threshold voltage and the hyster-
esis voltage would approach 7.5 and
22.5V, respectively. The 74VHC04
part proves the calculations using 5%
resistors and 20% capacitors.
Table 1 summarizes the results,
which are within the component tol-
erances. Figure 5 shows a typical input
Figure 5 The circuit is well-behaved at low frequencies.
and output plot.EDN

Class B amplifier has automatic bias Q2, VBEQ3 is the base-to-emitter voltage
of Q3, and VBEQ1 is the base-to-emitter
Pierre Corbeil, Paradox Innovation, Montreal, PQ, Canada voltage of Q1. Q1 and Q2 mirror this
current because Q1 and Q3 share the


Class B amplifiers are prone nal. Emitter current for Q3 is (VCC2 same base current, as do Q2 and Q4.
to crossover distortion, which VBIAS2VBEQ32VBEQ1)/R1, where VCC is Assuming that the four transistors are
occurs in the output stage in which the power-supply voltage, VBIAS is the perfectly matched, all of them have the
conduction transfers from one transis- dc voltage on the emitters of Q1 and same base current and the same collec-
tor to the other. To prevent crossover
distortion, a bias current must flow in VCC VCC
both transistors simultaneously. The
bias current prevents both transistors
R1
from turning off in the transition re-
gion. Classic bias circuits keep a con-
stant dc polarization voltage between
the bases of the two transistors. Often Q3 Q1

manually adjusted, it keeps the two

C2
transistors on the edge of conduction
when there is no signal present. Such a R2 R3
C3 C1
circuit is sensitive to temperature and
needs some form of compensation to VBIAS
� Q4 Q2
prevent thermal runaway, which can IC1
lead to failure. Figure 1 shows an ap- �
proach in which automatic bias elimi-
nates the problem.
In this Class B amplifier, R1 sets the Figure 1 A bias current flows in the transistors that prevents Q1 and Q2 from
bias current at idle mode with no sig- being off simultaneously.

october 22, 2009 | EDN 45

edn090820di45361 DIANE
(PLACED IN 9-3 FOLDER)
designideas
VCC VCC VCC VCC

R1 R1

Q3 Q1 Q3 Q1

C2 C2

C3 R2 R3 C1 C3 R2 R3 C1
VBIAS VBIAS
� Q4 Q2 � Q4 Q2
IC1 IC1
� �
(a) (b)

Figure 2 On a positive half-cycle, current flows from Q1 through C1 to a load (a). On a negative half-cycle, current flows
through Q2 (b).

edn090820di45362
12V DIANE
(PLACED IN 9-3 FOLDER) tor current, so the emitters of Q1 and
Q2 precisely mirror the current in R1.
Transistor matching is unnecessary,
R1
1.5k however. With unmatched transistors,
2N2907A 2N2222A either Q3 or Q4 must operate in satura-
Q3 Q1 tion, and, because the mirror effect de-
R2 R3 C2 C1 pends on the transistors’ current gain,
100 �F 470 �F
20k 20k hFE, the difference between Q1/Q2 bias
IN C3 12V OUT current and the current in R1 can be
1 �F R4
7
2N2907A significant. This circuit automatically
20k 2 �
IC1
Q4 Q2 adjusts the voltage on C2 to compen-
6
3
TLV271
2N2222A
sate for temperature and the transis-
2V �
4 tors’ characteristics.
When a signal is present, the cur-
rent gain is the hFE of output transistor
Figure 3 A typical application of this Class B circuit is a headphone amplifier.
Q1 or Q2 (the same as for a classic Class
B amplifier). On the positive part of
the signal, Q1 carries the load current.
Because the base current increases, Q3
0.25 edn090820di45363 DIANE
(PLACED IN 9-3 FOLDER)
enters saturation. On the negative part
0.2
of the signal, Q2 carries the load cur-
rent and Q4 saturates.
0.15 Figure 2 shows the ac-current path.
DISTORTION The maximum average load current is
(%) 0.1 the idle current in R1 times the current
gain of Q1 times two. The op amp must
0.05 be able to sink the base current of Q2
(load current/hFE)1((VCC2VBE34)/
0
10 100 1000 10,000 100,000
R1). A typical application of this Class
FREQUENCY (Hz) B amplifier delivers 0.25W into 8V
(Figure 3). Figure 4 shows the total
harmonic distortion over the 45-Hz
to 50-kHz band—that is, 1V rms into
Figure 4 This graph shows distortion as measured on the circuit of Figure 3. 8V.EDN
EDN091022DI4536FIG4 MIKE

46 EDN | october 22, 2009

designideas
Cable tester uses LEDs to find faults
Pavel Šádek, Apri, Rožnov pod Radhoštěm, Czech Republic


This Design Idea describes a binary number from zero to 15 (0000
simple cable-test machine that to 1111). You can generate the num-
visually shows continuity issues on a bers with a 555 timer and a binary
16-wire cable harness for ultrasonic- counter, but this circuit uses a tiny,
parking-aid systems. A subcontractor eight-pin microcontroller. A four-
produces the harness in low volumes, wire bus sends the digits to two four-
making it impractical to use an auto- to 16-line 74HC154 decoders, which
mated tester. For simplicity, the test generate active-low signals on their Figure 2 The cable-harness tester
signal drives LEDs for a visual indica- 16 lines. Inverting the outputs of the uses LEDs to indicate good
tion of continuity. driver decoder with a 74HC04 invert- connections.
The circuit in Figure 1 generates a er provides a drive signal for an LED
and current-limiting resistor on each
harness wire.
MICROCONTROLLER- OR 555-TIMER-
DRIVEN BINARY-NUMBER-ZERO-TO-15 The tester should produce one and
GENERATOR only one illuminated LED for a good
wire as the circuit scans the harness. If
4 the scan is fast enough, all LEDs will
4 all appear to be on, although each is
4 on for just one-sixteenth of the time.
16 LEDs Figure 2 shows the completed circuit
with eight LEDs, but it has room for
74HC04 16 LEDs.
INVERTER
Broken wires in a harness, wrong
wire positions, or other continuity
74HC154
CABLE UNDER
74HC154 failures lead directly to the turn-off
FOUR- TO FOUR- TO
16-LINE TEST 16-LINE of the corresponding LED. Swapped
DECODER/ DECODER/ wires can also lead to the turn-off of
DEMULTIPLEXER 74HC04 DEMULTIPLEXER
INVERTER two LEDs. Meanwhile, only one cath-
ode is driven high, whereas the others
are driven low, and only the cathode’s
anode is driven low, whereas the others
74HC04
are driven high. So only correctly con-
INVERTER nected wires could pass this test.
If you need to test harnesses with
more that 16 wires, you can cascade
Figure 1 A pair of four- to 16-line demultiplexers selects cable-harness wires additional decoders. You can also use a
for testing. high-pin-count microcontroller in the
same way.EDN

pulse to the coils is sufficient for oper-

Dual-coil relay driver uses
edn090820di44731 DIANE
(PLACED IN THE 9-3 FOLDER)
ating the relay. Many relays can oper-

only two MOSFETs ate with a continuous coil current, and

some dual-coil relays have internal
Mehmet Efe Ozbek, PhD, Atlim University, Ankara, Turkey contacts that interrupt the coil current
after it completes a state change. Con-


Latching relays change their
states when you apply a short
voltage pulse to their coils. Because
these relays require no continuous coil
currents to keep their states, you can
save considerable power in the driver
circuit. In one type of latching relays,
you can alternately energize dual coils
to change the relay state. Simply apply
voltage to one coil for the set state and
to the other coil for the reset state. Ap-
plying a 25- to 50-msec-wide voltage
tinuous coil voltages can drive such
relays if energy efficiency is not a big
concern.
The need to differentially drive the
coils results in crowded drive circuits
for dual-coil relays. Drivers usually in-

48 EDN | october 22, 2009

designideas
clude logic elements to make sure to
VDD
energize only one coil at a time. The 24V DC
design in Figure 1 uses only two MOS-
FETs to drive a dual-coil RF relay. The
Agilent Technologies (www.agilent.
com) N1810UL RF switch has dual
24V coils and internal current-inter- L1 L2

rupting contacts. R1
When logic input is high, Q1 con- 10k
ducts and changes the relay state by N1810UL
activating L1. The states of the cur-
rent-interrupting contacts also change.
Meanwhile, Q2 is off because Q1 pulls
down its gate, which avoids fighting 1N4007 1N4007
between the coils. If you then apply a VDD
low signal to the logic input, Q1 turns
off and keeps the L1 coil inactive. Be-
cause R1 pulls up Q2’s gate, Q2 turns on LOGIC
and energizes L2. The 1N4007 diodes INPUT
prevent inductive kickback. The idea Q1 Q2
is applicable to dual-coil relays with
BS107 BS107
continuously rated coils or with cur-
rent-interrupting contacts. In the ab-
sence of current-interruption contacts,
L1 can serve as a pullup, and R1 there- Figure 1 Using two MOSFETs to differentially drive a dual-coil latching relay
fore becomes redundant.EDN eliminates the need for any logic components.

edn091022di44901 DIANE
(PLACED IN THE 10-22 FOLDER)

50 EDN | october 22, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Negative-to-negative switch-mode
converter offers high current and D Is Inside
high efficiency 46 ADC for programmable logic
uses one capacitor
Budge Ing, Maxim Integrated Products Inc, Sunnyvale, CA


When converting a negative-
output power supply to one with
less-negative output, you must ensure
that variations in input voltage don’t
affect the output voltage. All such sup-
plies include an internal reference volt-
age that enables output-voltage regula-
tion. You usually refer this reference to
the most negative rail, which is ground.
Thus, the output voltage of such a con-
verter depends on the accuracy of its 51 Use two phases to cut current
negative input supply voltage. The cir- and improve EMI
cuit in Figure 1 lacks that limitation. 52 Fader switch uses
Delivering output currents as high as inexpensive controller
4A with efficiencies better than 90%,
it generates a negative output with the ETo see all of EDN’s Design
help of an op amp and a switch-mode Ideas, visit www.edn.com/design
boost converter. Closed-loop feedback ideas.
regulates the output voltage with re-
spect to ground, the most positive rail,

0V
�3.86V

C7
R4 R5 0.1 �F
D1 C5 5.76k 1.96k
EC31QS03L 10 �F
L1
2.2 �H � C6 3 5 �5.2V
� MAX4322
NEC/TOKIN 220 �F IC2
MPLC0730 4 1
�
2 �3.95V
R6
R1 OR 1.25V
5.76k R7
10 ABOVE
1.96k �5.2V
�3.6V �3.6V
Q1 4A
8
FDMS8690
C1 9 EXT
� VCC �3.86V
47 �F 6
10 SHDN CS+

IC1 R3
C2 MAX668 0.02
10 �F 7 R8
PGND
1 LDO 2k
5
FB
4
REF
3
GND C8
FREQ 0.47 �F
C3 2
1 �F C4 R2
0.22 �F 100k
500 kHz
�5.2V INPUT

Figure 1 A switch-mode converter generates a regulated negative supply voltage from a more-negative input voltage.

november 12, 2009 | EDN 45

designideas

Figure 2 Output voltage for the circuit in Figure 1 varies with Figure 3 Conversion efficiency for the circuit in
output current. Figure 1 varies with output current.

which is also the node from which cur-
rent is delivered to the load.
The circuit converts a 25.2V sup-
ply voltage to 23.6V. The boost con-
verter, IC1, regulates its output volt-
age to maintain its feedback voltage
at 23.95V—1.25V above 25.2V. Re-
sistor R8 and capacitor C8 form a low-
pass filter that stabilizes the voltage at
FB. You must then select the R4/R6 and
R5/R7 pairs to produce the desired out-
put voltage. Making R4 and R5 equal
and making R6 and R7 equal improves
the common-mode performance. The
ratio of R4 to R5 determines the voltage
level at the positive input of op amp
IC2, whose closed-loop configuration
ensures that the same voltage appears
at its negative input. Knowing IC2’s
output voltage, 23.95V, and its nega-
tive input voltage lets you determine
the output voltage using the values of
R6 and R7: VOUT52VREF(R6/R7), where
VREF is the 1.25V nominal reference
voltage of IC1, R45R6, and R55R7.
The component values in Figure
1—for example, 1.96 kV for R5 and R7
and 5.76 kV for R4 and R6—produce
an output voltage of 23.76V. Graphs
of output voltage versus output current
(Figure 2) and efficiency versus out-
put current (Figure 3) illustrate this
circuit’s performance.EDN

ADC for programmable logic


Many electronic devices require
uses one capacitor user input for setting the appli-
cation properties. Typical input devices
Jef Thoné and Robert Puers, include pushbuttons, potentiometers,
Katholieke Universiteit Leuven, Leuven, Belgium and touchscreens. To minimize over-
all project cost, you may have to select
fCLK
low-range microcontrollers, FPGAs
VDD (field-programmable gate arrays), or
CLK_IN
PLDs (programmable-logic devices).
R
These devices don’t provide a wide
range of peripherals and often lack an-
I/O alog-to-digital-conversion capability,
which can prove annoying when try-
COUNTER
AND LOGIC
ing to acquire user input. This Design
Idea describes a method for adding a
C LED1 LED2 LED8 low-end ADC to a single programma-
ble-logic I/O pin. The circuit charges
a capacitor through a resistor while
measuring the time to charge the ca-
CPLD/FPGA/MICROCONTROLLER pacitor to a certain voltage.
Before each measurement, the ca-
Figure 1 This circuit charges a capacitor through a resistor while measuring the
pacitor discharges to 0V. A single
time to charge the capacitor to a certain voltage.
I/O pin can perform both the dis-

edn090903di45291 DIANE
46 EDN | november 12, 2009
(PLACED IN THE 9-17 FOLDER)
 designideas Equations for DI4529 ( placed in the 9 − 3 folder )

charging and the timing. For an Equation 1

FPGA or a PLD, you can per-
form a discharge by setting the
I/O as an output pin and forc-  t 
ing a zero at that pin. You can VTH = VDD × 1e ×C 
 R
   V 
charge the capacitor by setting   COUNTERVALUE =fCLK × R × C × ln  1 TH  .
the I/O as an input pin, which COUNTERVALUE  VDD 
gives it a high impedance. The T=
fCLK
capacitor charges through the
potentiometer (Figure 1).
Meanwhile, a counter starts,
and the CPLD monitors the Figure 3 In this application, a 10-kV potentiom-
input voltage. As soon as the FigureEquation
2 The application
2 uses a eter in series with a 1-kV resistor charges a
capacitor voltage reaches the Xilinx XC9500 XL CPLD. 22-nF capacitor.
threshold, the counter stops at
a value that is a measure of the charg- C trollers is temperature measurement.
Equations for DI4529 ( placed in the 9 − 3 folder )
ing time. The charging time or coun- t DISCMIN = VTHRESHOLD × I . By replacing the pullup resistor with
SHORT
ter value relates to the clock frequen- a PTC (positive-temperature-coef-
cy, the value of the resistor, the value The discharge delay can be real- ficient) or an NTC (negative-tem-
of theinEquation
capacitor,1
s for DI4529 ( placed the 9 − 3 and
folderthe
) input thresh- ized with a small counter. After the perature-coefficient) resistor, you
old voltage: discharge time, the I/O pin acts as an can derive the temperature from the
e 9 − 3 folder )
input, which causes the capacitor to charging time after calibration. You
 t  charge through a pullup potentiom- can also use these devices to make
1
VTH = VDD ×  1e R×C  eter. Meanwhile, the internal coun- true analog-to-digital measurements.
  ter starts. When the capacitor  VTH By
voltage  replacing the pullup resistor with
  COUNTERVALUE =fCLK × R × C × ln  1 .
reaches the input threshold voltage,  V DD a voltage-controlled current source,
COUNTERVALUE
 t  T= the counter stops. Eight LEDs show an input-voltage change causes a
 R× C  fCLK the 8-bit value. In this application, a linear change in the charging time,
DD ×  1e 
  VTH 
  COUNTERVALUE =fCLK × R × C ×10-kV ln  1 potentiometer
. in series with a providing a real analog-to-digital
1-kV VDD  charges a 22-nF capaci- conversion.EDN
 resistor
UNTERVALUE  V 
NTERVALUE =fCLK × R × C × ln  1 TH  . tor. The input clock of the PLD is
fCLK
Equation 2  VDD  1.8432 MHz. The input threshold is R e f e r e n c e s
1.5V at a supply of 3.3V. This arrange- 1 Eggers, Torsten, and Thomas
If you assume that the capacitor ment allows a measurement range be- Schmidt, “AN10187 Low-cost A/D-
value, the input threshold voltage, C tween a counter value of 25 and 270, Conversion with Philips LPC Micro-
2 and the t DISCMIN = VTHRESHOLD
clock frequency remain× fair- equivalent
. to a resolution of almost controllers,” Philips Semiconductors,
I SHORT
ly constant over the operating range, 8 bits. Figure 3 shows the capacitor Oct 4, 2002, www.nxp.com/acrobat_
the charging time is linearly depend- charging/discharging waveform. download/applicationnotes/
ent on C the value of the resistor. If you Every IC’s I/O pin has a certain bias AN10187_1.pdf.
N = VTHRESHOLD ×
replace .
the resistor with a potentiom- sink or source current, causing a volt- 2 “Using an I/O Port Pin as an
I SHORT
eter, a counter value depends on the age drop over the charging resistor. A/D Converter Input,” Holtek, www.
. poten­tiometer position. The applica- This situation limits the charge volt- holtek.com.tw/english/tech/appnote/
T
tion uses a Xilinx (www.xilinx.com) age to VDD2RCHARGE3IBIAS. In other uc/pdf/ha0128e.pdf.
XC9500 XL CPLD (Figure 2). The words, if the charging resistance is 3 “AVR400: Low Cost A/D Convert-
I/O, which VHDL (very-high-speed- too large, the capacitor doesn’t charge er,” Atmel, www.atmel.com/dyn/
IC hardware-description language) above the input-pin threshold volt- resources/prod_documents/
declares as a tristate buffer, first shorts age, stopping the circuit’s operation. doc0942.pdf.
the capacitor. Hardware limits the Similar applications for microcontrol- 4 Quiring, Keith, “Implementing An
output short-circuit current of the lers or PLDs (references 1 through Ultralow-Power Thermostat With
I/O pins to 610 mA, so the capaci- 5) include adding multiple inputs to Slope A/D Conversion,” Texas Instru-
tor’s shorting should last long enough a single I/O pin and using a different ments, Jan 2006, http://focus.ti.com/
to guarantee a full discharge. You can pullup-resistor value for each input. lit/an/slaa129b/slaa129b.pdf.
calculate the minimum shorting time By discriminating the charging times 5 “CoolRunner-II Low Cost, Low
using the capacitor value, short-cir- for each resistor, the PLD can decide Power Thermometer for Embedded
cuit current, and discharge voltage, which resistor or combination of resis- Designs,” Xilinx, Nov 29, 2004, www.
assuming that the threshold voltage tors the user has actuated. xilinx.com/support/documentation/
must discharge from the capacitor: Another application for microcon- application_notes/xapp438.pdf.

48 EDN | november 12, 2009

designideas
Use two phases to cut current of 14A. Even though the circuit uses
four low ESR (equivalent-series-re-
and improve EMI sistance) output capacitors, output-
voltage ripple is still 110 mV p-p. The
Goran Perica, Linear Technology, Milpitas, CA aluminum output capacitor, COUT2,
doesn’t help much in reducing the
5 TO 20V output ripple due to its much higher
VIN ESR. COUT2 mainly helps reduce load
transients by adding bulk capacitance
L1
R1 CIN DRQ127-4R7 to the output rail.
66 �F
R5
274k
25V
L1A D1 Figure 3 (pg 52) shows a two-phase
PDS1040
133k
1 10 12V
converter, which is similar to the sin-
RUN SENSE
RC1
CDC
AT 3A gle-phase converter in Figure 1 except
33k 2 IC1
ITH LTC1871-1 VIN 9
CVCC
20 �F COUT1 for the addition of an identical second-
25V 132 �F
CC1
3 4.7 �F phase power stage. The second phase
1 nF VFB INTVCC 8 Q1
RT HAT2169 L1B
COUT2 �
halves the peak inductor, MOSFET,
80.6k 4
FREQ G
7 150 �F and output-diode currents. The 50%
5 6
R8
0.005
lower peak output-diode currents pro-
MODE GND
duce 50% lower output ripple (Figure
4, pg 52). Also, the output-ripple-cur-
R3 R4
rent frequency doubles, thus making it
12.4k 110k easier to filter out with an additional
LC filter if necessary.
Figure 1 A single-phase SEPIC has low input ripple currents and is suitable The benefits of using a dual-phase
for power levels of 5 to 50W. converter become clear when you con-
sider output-capacitor ripple current


In dc/dc-converter applications the same power components, resulting (Figure 5, pg 52). The two-phase con-
in which the input voltage may in
edn090625di45121 twice the output power in the two- verter’s output-capacitor ripple current
DIANE
be lower or higher than (PLACED the output phase design.
IN THE 7-9 FOLDER) is always lower than that of an equiva-
voltage, you can use either a flyback The single-phase SEPIC circuit can lent single-phase converter. Depending
converter or a SEPIC (single-ended- generate 3A of output current (Fig- on the duty cycle, the two-phase con-
primary-inductor converter). SEPICs ure 1). SEPICs are typically 1 to 2% verter’s output-capacitor ripple current
offer lower input-current ripple and more efficient than flyback convert- can approach 0A at a 50% duty cycle.
higher efficiency than do flyback de- ers. Figure 2 shows the output diode’s Inductor ripple current is still present,
signs. Both converters suffer from rela- current (bottom trace) at minimum and you can reduce it by using larger
tively high output-current ripple, espe- input voltage and maximum load and inductors.
cially at high load currents and low in- the output-voltage ripple (top trace). Using a two-phase converter means
put voltages. As output-current ripple The circuit’s output capacitors must that you can use smaller inductors,
increases, so does the circuit’s output- handle the peak output-diode current MOSFETs, output diodes, and output
filter-capacitance require- capacitors than you can use
ment, which increases size in an equivalent single-phase
and cost. You can reduce converter. Because high-
output-current and -volt- power designs may need to
age ripple without increas- use more than one MOSFET
ing the application size and anyway, a dual-phase design
cost by using a multi­phase may need only one addition-
SEPIC or flyback converter. al smaller inductor and one
Using a multiphase flyback smaller diode. Output LC
circuit also greatly reduces filters can also be smaller be-
the input-current ripple. cause of the doubling of the
To evaluate the benefits of output ripple frequency. Fi-
a dual-phase versus a single- nally, the EMI performance
phase SEPIC, this Design of a dual-phase SEPIC should
Idea compares two designs be better than that of a single-
running at 300-kHz switch- Figure 2 The single-phase circuit in Figure 1 has a peak phase converter because of
ing frequency. For consis- capacitor output current of about 14A (bottom trace). lower current slew rates and
tency, both examples use smaller current loops.EDN

november 12, 2009 | EDN 51

designideas
5 TO 20V
INPUT

T2A T2B
DRQ127-4R7 DRQ127-4R7

CS1
1 nF HAT2169 20 �F
1 D 24
MAX 3V8
2 10
SLOPE SENSE1� 23
10 nF D1
3 BLANK SENSE1� 22
24.9k PDS1040
4
PHASEMODE RUN 21 0.006k
66.5k 84.5k 66 �F 132 �F
5
FREQ VIN 20 12V
10 nF 4.7 �F 1 �F 6A OUTPUT
6 SS INTVCC 19
IC1 � COUT2
6.8k 7 I LTC3862 0.006k
G1 18 150 �F
TH
8
10 nF 100 nF FB PGND 17
9 HAT2169 D2
SGND G2 16
10 PDS1040
12.4k CS2
CLKOUT NC 15
20 �F
11
107k SYNC SENSE2� 14
VOUT 12 10 nF
PLLFLTR SENSE2� 13
10
T1A T1B
DRQ127-4R7 DRQ127-4R7

Figure 3 By adding second power stage and shifting the phase by 1808, you can reduce the output ripple currents by
more than 50%.

edn090625di44123 DIANE
(PLACED IN THE 7-9 FOLDER)

Figure 4 The output ripple current is 50% lower for a two-phase Figure 5 The normalized output-capacitor ripple
SEPIC. The output ripple voltage is 50% lower than that of a current for single- and dual-phase SEPICs shows
single-phase design with the same output capacitors. lower output ripple with a two-phase design.

Fader switch uses multiple-cycle, 470-Hz, PWM (pulse-

width-modulated) output to drive
inexpensive controller LEDs or incandescent lamps. The
circuit includes a MAX16823 (www.
William Grill, Lenexa, KS maxim-ic.com) IC that drives multi-


Customizing a model or a simu-
lator with a bit of illumination
is a nice touch. Rather than a simple
on or off, you can add a touch of both
refinement and control to your display
with fading light. Employing a Micro-
chip (www.microchip.com) 10F20x
microcontroller, the circuit in Figure
1 provides dual-rate fader control for
a push-on/push-off switch, a momen-
tary pushbutton switch, or a simple on/
off SPST (single-pole/single-throw)
switch. The circuit monitors and de-
bounces the switch and generates a
ple LEDs.
The microcontroller produces 64
linear steps of a PWM signal between
0 and 100% duty cycle. The control-
ler maintains each pulse width for a
variable number of cycles employing a
table in the assembly code (Listing 1,

52 EDN | november 12, 2009

designideas
VIN
MAX16823
7 2
IN OUT1
8
IN 1
9 OUT2
2
IN
8 3 5 16
DIM2 OUT3
4 10F200 3 DIM1
5 4 DIM3
6
7 LEDGOOD
15
10 CS1
LGC 14
11 CS2
REG 13
CS3
22 �F GND R1 R2 R3
12

Figure 1 A microcontroller provides pulses with adjust- Figure 2 A table in the microcontroller code lets you run
able widths to create fading in LEDs. fast- or slow-fading profiles.

which you can download at the online
version of this Design Idea at www.
edn.com/091112dia). You can modi-
edn090917di44961 DIANE
fy the code to build profiles
(PLACED of FOLDER)
IN THE 10-8 LEDs
or incandescent lamps by applying
a settable dwell time to each PWM
step. The code contains two tables
to set fast- and slow-fade characteris-
tics. The fade values provide a cubed
index that produces a 3-to-1 fade ratio
(Figure 2). Using the final state of the
output at Pin 3 of the 10F200, you ac-
cess the tabled number of dwell cycles
from the first table entry to the last
for a high final state or from the last
entry to the first to arrive at the final
low state.
Fade-transition timing is user-se-
lectable for either a 3- or a 9-second
period. The circuit periodically sam-
ples both the fade rate and button or
switch mode, allowing you to multi-
plex the design or use it in multiple
configurations. The mode control is
on Pin 5 of the controller, and the
rate control is on Pin 4. The applica-
tion exploits the controller’s internal
4-MHz clock and the configurable
pullup resistors on the monitored in-
puts. A prototype of the circuit uses a
10F20x in an eight-pin DIP, but the
controller is also available in a smaller
SOT-23 package.EDN

54 EDN | november 12, 2009

 designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Inspect solar cells D Is Inside

without a microscope 43 Solar-powered sensor
Chun-Fu Lin and Tai-Shan Liao, controls traffic
National Applied Research Laboratories, Hsinchu, Taiwan 46 Self-oscillating H bridge lights


Solar cells convert light energy cell’s electroluminescence signature
into electricity, making them to find defects on a solar cell. A cell’s
a renewable energy source. Solar-cell light has a wavelength of about 1.1 mi-
manufacturers often use SEMs (scan- cron, which results when you apply a
ning electron microscopes) to detect forward bias voltage and forward op-
defects in solar cells while they’re still erating current of at least 7A to the
in wafer form. Although SEMs can see cell. An SWIR sensor can provide an
down to a solar cell’s grain structure, image of an entire wafer, eliminating
they can be slow because their scan ar- the need to scan the wafer. The sensor
ea is small. A SEM must scan a wafer identifies defects by detecting a wafer’s
many times to cover it. electroluminescence.
Instead of using a SEM, you can use Figure 1 shows the system, which
an SWIR (shortwave-infrared) cam- uses an SWIR sensor that converts an
era system to detect defective cells. image into an analog voltage. A pre-
You can take advantage of a solar amplifer boosts the signal to a level suf-
5 AND 3.3V
PREAMPLIFIER
POWER-SUPPLY
CIRCUIT
CIRCUIT
900- TO 1700-NM
SWIR AREA
CHARGE-COUPLED
DEVICE IMAGE-DATA GRAB
IMAGE-GRABBING
ADC CARD
TIMING-DRIVER (LVDS INTERFACE)
CIRCUIT
FOUR-PIN INTEGRATION-TIME
COMMAND PORT CONTROL
white LED from one cell
48 Low-cost LCD-bias genera-
tor uses main microcontroller
as control IC
ETo see all of EDN’s Design
Ideas, visit www.edn.com/
designideas.
ficient for an ADC in a digital-process-
ing module to digitize the analog signal
at 10M samples/sec.
The ADC’s digital output travels
through an LVDS (low-voltage-dif-
ferential-signaling) data interface to a
Dalsa (www.dalsa.com) frame-grabber
card in a computer. Custom image-
processing software, written in C11,
processes the data, producing an image
of the entire wafer on the computer’s
screen.
The board containing the sensor,
preamplifier, and ADC also has a mi-
crocontroller, which generates a clock
signal for the timing of the sensor and
the ADC. An RS-232 communica-

TIMING-GENERATOR MAIN CLOCK MICROCONTROLLER

CIRCUIT CIRCUIT (RS-232 INTERFACE)

CHARGE-COUPLED-DEVICE FOCAL-PLANE ARRAY

DIGITAL PROCESSING

POWER
Figure 2 An electroluminescence
Figure 1 An ADC digitizes an analog signal from an SWIR sensor and sends image of solar cells shows dark
the signal to a frame grabber for processing. areas that indicate failed cells.

42 EDN | november 26, 2009

tions port on the Atmel (www.atmel.
com) microcontroller allows it to com-
municate with a PC to get commands
from the user who set parameters
such as the SWIR sensor’s operating
mode. A timing-driver circuit sends
the clock signal to the SWIR sensor.
Figure 2 shows the image from the
SWIR camera circuit. This image
shows the intensity distribution of the
cell’s light output. A homogenous in-
tensity-distribution image is essential
for a high-quality solar cell, but solar
cells always show some inconsistencies.
All defects resulting in a local reduc-
tion of the carrier concentration are
visible on the electroluminescence im-
age as dark bars.EDN

Solar-powered sensor controls traffic

Larry K Baxter, Capsense, Lexington, MA


Th is de
s ig n w
as
Have you ever sat in your car dumb, with relays, cams, and switch- winning
ent r
waiting for the light to turn es, although they now may include EDN’s rec
ent onli
y in
green when nobody’s using the cross software that accepts data from local IRon ne
Designe Circuit
r
street? This wait is due to the fact sensors, automobile-sized inductive see the contest;
that the sensors controlling these traf- loops buried in the asphalt. Modern design at complete
w
com/091 ww.edn.
fic signals—in one large-suitcase-sized controllers have gained some intel- 126dia
box per intersection—are classically ligence. For example, they may share

6V, 900-mA BQ24083R 3V, 19-AHR LOW-DROPOUT

SOLAR CELL BATTERY CHARGER LITHIUM BATTERY REGULATOR, SWITCH

MEASURE VOLTAGES SWITCHED

3V
3V
TWO
STRIP-DETECTOR INSTRUMENTATION
PRESSURE 2.4-GHz
PNEUMATIC AMP INA333
SENSORS CC2500
MOVING WIRELESS
WEIGHT TMP102 TRANSCEIVER
1.5V OPA333
TEMPERATURE
GENERATOR
SENSOR

WEIGHT
WIM-DETECTOR
CAPACITIVE CAPACITIVE
DRIVE
CAP PAD SENSOR

IR-BEAM
INTERRUPT
940-nm LED FET MSP430
F248
DAC6311 MICROCONTROLLER
SWITCH,
PIN OPA364 DAC LED
PHOTODIODE AMP

PGA112
PROGRAMMABLE-
GAIN AMP

PASSIVE- OPA364
INFRARED AMP
DETECTOR MOVING IR

NOTE: ITEMS IN BOLDFACE ARE ON THE IRON CIRCUIT DESIGNER

CONTEST APPROVED-PARTS LIST.

Figure 1 Most of the circuit amplifies outputs from four sensors, digitizes them with the MSP430’s 12-bit ADC, does some
preprocessing, and messages the controller.

november 26, 2009 | EDN 43

designideas
data with nearby inter-
P3
sections, respond to radio
requests from emergency CAP PAD RC=100 �SEC
R14
J4
vehicles, and sometimes 100k
R15
2k CAP PAD
4
take commands from a
traffic-control center. This 3
D1
C13
T=R�CP
220 pF EMS
Design Idea describes the CP 2 1N5333
D
24 nF
TSP (traffic-sensor post), 1
Q1
G CAP DRIVE
a more accurate, effective, ESD
S QMN-2N7002
inexpensive, and easy-to-
install approach to moni­ 10-mSEC MINIMUM PULSE
863-1N5228BG

t­oring traffic flow. These 30-mV CAPACITIVE SENSOR

sensors measure vehicle lo-
cation and speed in four or Figure 2 The Cap Pad sensor has a nominal capacitance of about 24 nF at rest, with a
more streets at an intersec- change of about 7% full-scale when a truck passes.
tion or at a distance from
the intersection for early warning. A the deep-IR band for moving IR sourc- tion. You use multiple pads to handle
second application of this technology, es. This technology finds use in inex- multilane roads. The Cap Pad can be
the WIM (weight-in-motion) sensor, pensive motion-detecting lamp con- fastened to the asphalt with adhesive
edn091126newone DIANE
weighs moving trucks. trols and senses vehicles from 30 feet or pavement tape or buried under as
(PLACED IN THE 11-26 FOLDER)
The circuit comprises a wireless, away. The detection range is good, the much as an inch of asphalt for protec-
solar-powered sensor array that handles parts are cheap, and the beam can see tion. Its materials cost is only a couple
all the data collection at an intersec- through a layer of dirt. It can’t measure hundred dollars, a huge saving over the
tion (Figure 1). Cities can install these speed, distance, or direction. piezoelectric WIM sensors currently in
sensors at each of the four corners of The TSP also uses conventional use.
an intersection for full coverage. The pneumatic tubes. Rubber tubes are sta- The TSP also uses a near-IR trans-
sensors send data to the single control- pled to the asphalt and feed two pres- mitter/receiver using a pulsed LED for
ler box over IEEE 802.15.4 in a star sure sensors. This approach accurately transmission and a PIN (positive-in-
network. The approach combines four measures speed, but permanent instal- trinsic-negative) photodiode for re-
sensors in an inexpensive, low-mainte- lations cannot use it because it gets ception. Both need cylindrical lenses
nance, 6-in.-diameter, 6-foot-tall post. damaged easily. Municipalities often to focus the beam to a 28-wide, 58-high
You can build the circuit into the post deploy pneumatic tubes to measure ellipse that covers a remote retrore-
that holds the traffic lights, or you can traffic volume in road construction. flective screen, as in highway signs, or
use it stand-alone. Not all TSPs require The Cap Pad comprises a 10-in.312- to the IR sensors on another TSP. A
all four sensors; you can select those foot sandwich of three 0.05-in.-thick multilayer optical bandpass filter that
that your application needs based on stainless-steel sheets separated by two removes visible light further improves
usage. The TSP is the first wireless ap- 0.05-in.-diameter closed-cell urethane- the range.
proach to this problem, and one of the foam layers (Figure 3). You capacitive- Precision capacitive sensors can mea-
sensors, the Cap Pad, provides a huge ly measure the 0.025-in. deflection of sure an air gap between adjacent metal
advantage over current expensive and the pad under a truck’s tire to weigh plates to subnanometer accuracy. Un-
inaccurate WIM sensors (Figure 2). the axle. One Cap Pad can handle fortunately, accuracy in the WIM appli-
The TSP uses a PIR (passive-infra- the WIM requirements, and using two cation requires flat and parallel surfaces,
red) sensor that looks 10 microns into can add speed and direction informa- and the Cap Pad has neither. Capaci-
tive sensors can also accurately measure
STEEL a force on adjacent flat plates with a re-
storing spring, but flatness and parallel-
ism are still requirements. Maintaining
parallelism over a 10-in. pad would be
0.25 IN.
difficult, and roads are seldom flat.
If compression of the air pockets in
closed-cell foam provides the restor-
CLOSED-CELL
URETHANE FOAM ing force, however, the resulting spring
constant changes from the convention-
Figure 3 The Cap Pad sensor is a 10-in.312-foot sandwich of three 0.05-in.- al F5K3x of springs or cantilevered
thick stainless-steel sheets separated by two 0.05-in.-diameter closed-cell beams to F5P03H/(H2x), where F
urethane-foam layers. is force, P0 is atmospheric pressure,
H is the starting gap, and x is the dis-

44 EDN | november 26, 2009

designideas
placement. The result of this equation
is that the capacitance of the pad var-
ies linearly with applied force, and the
surfaces of the Cap Pad no longer need
to be parallel or flat. It accurately mea-
sures a force regardless of its size.
Most of the circuit amplifies out-
puts from the four sensors, digitizes
them with the MSP430’s 12 bit-ADC,
does some preprocessing, and messag-
es the controller. The 6V solar panel,
40 IXYS (www.ixys.com) solar cells in
series, charges a 19-Ahr, 3V, lithium-
polymer battery through IC1. Low-
dropout regulator/switch IC2 regulates
battery output at 3V. The battery gen-
erates more than 4V at full charge and
3.2V at the end of charge, and the
low-dropout regulator at 42 mA gen-
erates only 50 mV. IC2 also switches
active-mode 3V power.
The road-strip sensor senses the 0.1-
to 1-psi pulse when a car drives over
the pneumatic tubes. A 400V silicon
bridge sensor differentially outputs ap-
proximately 50 mV. Instrumentation
amplifiers IC3 and IC4 boost the out-
put to a few volts. The pressure sensor,
Self-oscillating
H bridge lights
white LED from
one cell
Luca Bruno, ITIS Hensemberger
Monza, Lissone, Italy

You can build a self-oscillating
H bridge by replacing the pull­
up collector resistors of a classical BJT
(bipolar-junction-transistor) astable
multivibrator with PNP BJTs (Fig-
ure 1). Because this circuit oscillates
at supply voltages as low as 0.6V, you
can use it in general low-voltage, low-
power push-pull applications. You can,
for example, drive a diode-capacitor
charge pump to generate negative sup-
ply voltage in battery-powered systems.
This Design Idea shows how to use it to
light a white LED from one cell with-
out an inductor.
46 EDN | november 26, 2009
as well as the Cap Pad and the PIN
sensor, has a quiescent level with no
traffic. A timer detects the no-traffic
state and stores this level in RAM, up-
dating every second to follow slow off-
set drifts from environmental factors,
so sensor offset accuracy is not critical.
The pressure sensor’s scale accuracy—
at approximately 30%—is relative-
ly uncritical, but the Cap Pad’s scale
accuracy should be a few percentage
points or less. All sensors must have
good resolution.
IC5 handles accurate temperature
measurements, which are necessary
for the Cap Pad, whose temperature
dependence results from the elastic
modulus change of polyurethane. The
Cap Pad has a nominal capacitance of
about 24 nF at rest, with a change of
approximately 7% full-scale when a
truck passes. The Cap Drive pulse dis-
charges this capacitance at a 700-Hz
rate, and a 100-kV resistor charges it
to 3V with a 240-msec time constant.
A timer times the number of pulses it
takes to cross the internal VDD/2 ref-
erence using the internal comparator,
VBAT
R4
Q4
3.9k 3.9k
BC557C
VBAT VBAT
R5
15 R1 R2
C1 5.6k 5.6k
1.5 nF
Q1
BC550C BC550C
Figure 1 Resistors R1 and R2 and capacitors C1 and C2 set the oscillation fre-
quency.
and, because you can clock the timer at
12 MHz, the resolution is 1%. You can
get increased resolution by timing out
the nominal quiescent pulse width and
capturing the pulse’s level at that point
with the 12-bit ADC.
The Cap Pad’s sandwich construc-
tion shields the active element from
electromagnetic interference, but a
3W zener diode cleans up any remnant
lightning strokes. The IR LED drive is
a 20-to-1 current mirror to handle LED
voltage variation. A DAC handles the
PIN photodetector’s offset because the
extreme night-to-day dynamic range
would overrange the 12-bit DAC. The
PIR sensor turns moving deep-IR tar-
gets into bipolar millivolt voltage puls-
es with its special segmented lens and
dual-element pyroelectric detector. A
PGA (programmable-gain amplifier)
selects and variably amplifies the PIR
sensor’s signal and the PIN signal. The
timer uses standard connections.
For a power budget, more schemat-
ics, and more details of this circuit, see
the Web version of this article at www.
edn.com/091126dia.EDN
S1
R3 ON/OFF � BT1
Q3
1.5V
SINGLE
CELL
BC557C
D1
BYV1030
R6
15
C2
C3 C4
1.5 nF 1 �F D3 1 �F
WHITE LED D2
BYV1030
Q2
 designideas
Transistors Q1, Q2, Q3, and Q4 form
the H bridge, which acts as a simple
charge-pump converter and requires
only two small, inexpensive ceramic
capacitors, C3 and C4, to perform its
function. When Q2 and Q4 are on, ca-
pacitors C3 and C4 charge to the bat-
tery voltage through forward-biased
Schottky diodes D1 and D2. When Q1
and Q3 are on, they discharge the ca-
pacitors through resistors R5 and R6
and the LED. Because this process re-
peats at a high rate of speed, the LED
appears always on.
The circuit oscillates with a frequen-
cy based on time constants R1C1 and
R2C2. During discharge, the voltage
that develops across resistors R5 and R6
and the LED remains approximately
constant because of the high switch-
ing frequency. The measured value,
for a nominal 1.5V battery voltage, is
3.8V—enough to drive a white LED
with a forward voltage of 3 to 3.5V.
Resistors R5 and R6 set the LED’s peak
current and limit the possible current
Low-cost LCD-bias generator uses
main microcontroller as control IC
Tom Hughes, Dannemora, Auckland, New Zealand

LCD circuits often require a
210V voltage at 2 to 15 mA to
bias a graphics-LCD-driver IC. You can
usually accomplish this task with an ex-
ternal charge-pump IC, such as Max-
im’s (www.maxim-ic.com) ICL7660,
but that approach adds cost to the de-
sign. Instead, you can control a buck-
boost switch-mode regulator using the
same microcontroller that sends data
to the LCD. In addition, you can se-
quence the power rails under software
control, as some types of LCD control-
lers require.
The circuit includes IC1, an Atmel
(www.atmel.com) Attiny15 micro-
controller (Figure 1), which provides
regulation with 200-mV-p-p ripple at
a 30-mA load current when supplying
210V. Listing 1, which is available
in the online version of this Design
Idea at www.edn.com/091126dib, lets
48 EDN | november 26, 2009
spikes that a push-pull output stage can
produce.
Choosing the astable oscillator’s fre-
quency involves a trade-off between
the time necessary to charge capacitors
C3 and C4 and the need to reduce their
discharge. For a given capacitance val-
ue of C3 and C4, you must experiment
to find the optimum frequency. With
the component values in Figure 1, the
frequency and the duty cycle are about
66 kHz and 50%, respectively, and the
LED’s drive current is a square-wave
signal with 20-mA peak value and 10-
mA average value. The LED dims grad-
ually as the battery voltage decreases,
and the LED is off when the battery
voltage falls below 0.9V. For high effi-
ciency, use small-signal transistors with
high dc current gain and low collector-
to-emitter saturation voltage. Note
that the circuit can drive any type of
LED; in this case, you should increase
current-limiting resistors R6 and R5 to
achieve the LED-drive current your
application requires.EDN
you download the source code, which
uses only 4.8% of the total CPU time
to achieve the stated regulation, even
with a relatively low-speed clock fre-
quency of 1.6 MHz.
To minimize CPU time, the soft-
ware uses the 8-bit on-chip PWM
(pulse-width modulator) to drive Q1.
With the on-chip ADC in free-run-
ning mode, the microcontroller gener-
ates a hardware interrupt with a period
of 7.69 kHz. The interrupts have one
drawback: If they stop, the circuit can
go out of regulation. Thus, you must
take care when using interrupts with
long processing times. The Attiny15
uses an on-chip, 163 PLL (phase-
locked loop) to drive the PWM timer.
You can achieve a PWM carrier fre-
quency of 100 kHz, which allows the
use of a relatively low-capacitance fil-
ter capacitor, C1.
 Two constants in the source code let (R41R5)]R5}, where VMAX is the maxi- VOUT and V IN are the output and
you alter the bias voltage of the circuit’s mum desired output voltage and VCC input voltages, respectively. In prac-
output voltage. These constants em- is the supply voltage. To achieve opti- tice, however, if you keep the current
ploy basic buck-boost-converter theory mum operation, increase the PWM sig- at less than 2 mA, this requirement is
(Reference 1). The following equation nal’s duty cycle when you need higher less important.
defines the maximum 8-bit constant, voltages. Use the following equation The circuit can deliver currents that
or threshold, that the ADC reads on to determine the 8-bit PWM’s value: Q1’s collector current predominantly
the chip: 51.23{VCC2[(VCC2VMAX)/ 2552VOUT/(VOUT2VIN)3255, where delivers. This current is the peak output
VCC
current that the circuit can safely de-
5V liver. The following equation calculates
the current: IOUTMAX5(VIN30.08)/VOUT,
R5
where IOUTMAX is the maximum output
C4 R1
10k current. If your design needs higher cur-
100 nF 10k
rent, then substitute a BC327 for Q1.
Q1
D2 R4 Additionally, the inductor should have
R2 BAS70 33k
2.2k BC858ASMD
VOUT a maximum rms (root-mean-square)
�10V current value of at least twice the peak
VCC 1
(ADC0)PB5 output current and preferably be a low-
5V 2 L1 C1
(ADC3)PB4
330 �H 22 �F
ESR (equivalent-series-resistance) type
IC1 3
ATTINY15
(ADC2)PB3
7
to maximize circuit efficiency.EDN
(ADC1)PB2
C3 8 6
100 nF VCC (OCP)PB1
5
R e fe r e nce
4 (AREF)PB0
GND 1 Hart, Daniel W, Introduction to
Power Electronics, First Edition, pg
202, Prentice Hall, Oct 25, 1996,
Figure 1 An Attiny15 microcontroller provides regulation with 200-mV-p-p ISBN-10: 0023511826, ISBN-13:
ripple at a 30-mA load current when supplying 210V. 978-0023511820.

edn091112di45771 DIANE
(PLACED IN THE 11-26 FOLDER)

november 26, 2009 | EDN 49

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Precision tilt/fall detector

D Is Inside
consumes less than 1.5 mW 40 Reset an SOC
Marián Štofka, Slovak University of Technology, Bratislava, Slovakia only when power is ready


When you need to detect an-
gular position related to Earth’s
gravity, you can use an Analog Devices
(www.analog.com) three-axis MEMS
(micro­electromechanical-system) ac-
celerometer. The ADXL335 has three
analog outputs that correspond to the
X, Y, and Z axes of an orthogonal coor-
dinate system (Reference 1). Because
the Z axis is perpendicular to the foot-
print, or base, of the MEMS IC’s pack-
age surface, you can use the accelerom-
eter to detect tilt if you mount it on a
PCB (printed-circuit board) that’s par-
allel to your product’s base. The circuit
in Figure 1 lets you detect whether
3V
the tilt exceeds a preset limit. A digital
output, in this example, drives an LED,
but you can connect the signal to a
microcontroller or another device.
When you orient the accelerometer
IC horizontally relative to Earth, the
LED is on. Whenever the Z axis of the
device declines by a specific value, aT,
of the angle, a, from the vertical di-
rection, the LED turns off. The voltage
difference at the Z-axis output, ZOUT,
of the accelerometer, referenced to
the power supply’s midvoltage, VS/2, is
VGZ5VGcosa, where VS is the power-
supply voltage, VGZ is the voltage at
the ZOUT pin, and VG is the terrestri-
44 Circuit provides simpler
power-supply-sequence testing
46 Inexpensive power switch includes
submicrosecond circuit breaker
48 Create a DAC
from a microcontroller’s ADC
ETo see all of EDN’s Design Ideas,
visit www.edn.com/designideas.
al full-scale voltage. When the pow-
er-supply voltage is 3V, the terrestrial
full-scale voltage is either 300 or 2300
mV, depending on whether you ori-

V�
RS AD8603,
16 15 14 13 100k ½AD8607, OR
NC VS VS NC 0.2% ¼AD8609
470 nF 1 VREF
NC �32k XOUT 12 �
RR IC2A
2 11 10k
NC ST NC
IC1 10 nF 0.2% �
3 ADXL335
COM �32k YOUT OUT
10 VS
4 6.2k
2
NC NC 9 10 nF AD8603,
Y ½AD8607, OR
Z IC3
¼AD8609
RR SN74AHC132
10k �
X �32k
0.2% IC2B
�VREF �
COM COM COM ZOUT RS
100k LED
5 6 7 8 0.2% HLMP-EG3A
VGZ V�

10 nF

0V
Figure 1 The tilt on MEMS accelerometer IC1 produces a voltage, VGZ. When compared with VREF and 2VREF, VGZ
produces a digital output at the NAND gate.

December 3, 2009 | EDN 39

designideas
ent the detector from the top down or
from the bottom up. Op amp IC2 com-
pares the voltage at the ZOUT pin to the
reference voltage, VREF . If the positive
voltage at the ZOUT pin is equal to or
lower than the reference voltage, the
output of IC2A goes high, and the out-
put of IC2B remains high (Reference
2). Thus, the output of NAND gate
IC3 becomes low, and the LED turns
off. You can calculate the threshold tilt
angle, aT, at which this action occurs
from the equation cosaT5(VREF/VG).
Resistors RS and RR set the voltage
reference to 136.36 mV. Thus, the
threshold tilt angle is 62.968. Similarly,
when the negative voltage at the ZOUT
pin becomes lower in magnitude than
the negative reference voltage, it indi-
cates a tilt of 62.968 or more, the output
of IC2B goes high, and the LED (Ref-
erence 3) also turns off. Theoretically,
you can choose any other threshold an-
gle within the interval of 0 to 908. The
practical limits with the 10-nF filter-
ing capacitor, however, are 21.23 and
86.108. The probability of a short-term
false detection is 831025. From the
properties of the cosine function, the
sensitivity of the tilt detector rises with
rising tilt angle. To select another value
of tilt within this interval, you calcu-
late the appropriate reference voltage
from the equation cosaT5(VREF/VG)
and then change the value of the RR
resistors as necessary.
Gravity causes a voltage difference at
the ZOUT pin of IC1. The circuit detects
Reset an SOC
only when power is ready
Goh Ban Hok, Lantiq Asia Pacific Pte Ltd, Singapore

An SOC (system on chip) nor-
mally requires two power sup-
plies—one for the core supply and the
other for the I/O. To properly power
up the chip, you need to get one of
the power supplies ready before the
other, according to the SOC’s power-
sequence requirement. Normally, the
core voltage must power up first, and
the I/O voltage powers up second. In-
40 EDN | December 3, 2009
the detector’s
operation is
virtually insensitive
to power-supply
variations.
fall on the loss of this gravity-induced
voltage difference within “free fall”—
moving bodies with no acceleration
other than that provided by gravity. If
the circuit is fixed to such a body while
the Z axis of IC1 is pointing roughly ver-
tically, the free fall manifests itself as al-
most fully disappearing within the 300-
or 2300-mV voltage excursion at ZOUT.
When the voltage remains close to the
power supply’s midvoltage, the voltage
at ZOUT is 1.5V. The threshold of detect-
ing the free fall in this case is an appar-
ent decrease in gravity to 0.4545g.
The probability that the noise’s peak
value will achieve this threshold value
is practically zero for “heavy” bodies.
The probability that the noise’s peak
value will achieve 0.0679g is fairly low,
and it decreases vastly when you ele-
vate the decision level. An apparent
decrease in gravity within the free fall
causes a low-to-high transition at the
output of either IC2A or IC2B, depend-
ing on whether the Z axis is close to
parallel or antiparallel to vertical. The
outputs of both IC2A and IC2B remain
at a high state. Thus, in both orienta-
tions, the output of the NAND gate
stead of direct control of the power
supplies, you can control the system
reset to achieve a similar goal. Figure
1 shows the reset-conditioning circuit
that can accomplish this task. In this
circuit, the core voltage is 1.8V, and
the I/O voltage is 3.3V. The reset-SOC
signal produces a logic high when the
core voltage gets ready before the I/O
voltage. When the I/O voltage pow-
goes low, and the LED turns off.
The sensitivity of IC1 is essentially ra-
tiometric. The resistive voltage divider
RS/RR derives the positive and the neg-
ative reference voltages, which are in-
herently ratiometric. Thus, the detec-
tor’s operation is virtually insensitive to
power-supply variations. Note that the
NAND gate has an internal Schmitt
trigger at its inputs, and its logic out-
put therefore fulfills industrial-grade re-
quirements, including duration of the
logic-state transitions of no more than
10 nsec regardless of the slope of the de-
tected signal when crossing the thresh-
old. If you need a complementary on/
off indication, you can reconfigure the
circuit by another position of the LED
(dashed lines in Figure 1).EDN
R e fe r e nce s
1 “ADXL335: Small, Low Power, 3-
Axis 63 g Accelerometer,” Analog
Devices, 2009, www.analog.com/
en/sensors/inertial-sensors/adxl335/
products/product.html.
2 “Precision Micropower, Low Noise
CMOS, Rail-to-Rail Input/Output
Operational Amplifiers, AD8603/
AD8607/AD8609,” Analog Devices,
2003 to 2008, www.farnell.com/
datasheets/81525.pdf.
3 “HLMP-EGxx, HLMP-EHxx, HLMP-
ELxx New T-1¾ (5mm) Extra High
Brightness AlInGaP LED Lamps,”
Avago Technologies, www.avagotech
lighting.com/signageandsigns/signs/
si_new_products.
ers up first, the reset signal resets the
SOC chip only after the core voltage
powers up.
Comparator IC1 monitors both volt-
ages. It operates on the 3.3V I/O-sup-
ply voltage. Resistor R2 and variable re-
sistor R1 form a voltage divider that lets
you set the required voltage based on
the core voltage. In this case, the refer-
ence voltage is 1.65V at Pin 3. Push-
button switch S1 provides a hard reset
of the SOC.
In Figure 2, the core voltage
(Trace A) powers up first, and the
I/O voltage (Trace B) follows. Com-
designideas
parator IC 1 remains inactive until
the I/O voltage activates. When the
I/O voltage turns on, comparator IC1
and AND gate IC2A operate. As the
voltage at IC1’s Pin 2 is higher than
that of Pin 3, the comparator pro-
duces a high at Pin 7, which pulls up
through R5.
The reset signal at IC2A’s Pin 1
(Trace C) initially remains at zero and
starts to charge capacitor C1 to the I/O
voltage through R6. Depending on
your application, you can adjust the
RC time constant to suit your needs.
The reset-in signal goes high after C1
charges to the logic-high level, which
produces a logic-high signal at Pin 3
(Trace D), resetting the SOC.
In Figure 3, the I/O voltage (Trace
B) powers up first, and the core volt-
age (Trace A) follows. The core volt-
The reset-out signal
remains at zero
state because the
core voltage is
not yet present.
age powers up after the R6/C1 time
constant. When the core voltage is
0V, the comparator voltage at Pin 3
is higher than it is at Pin 2. Thus, the
comparator produces a logic low at
Pin 7. Pin 1 of AND gate IC2A remains
high after the I/O voltage charges ca-
pacitor C1. The reset-out signal re-
mains at zero state because the core
voltage is not yet present. When the
core voltage comes up, the voltage at
comparator IC1’s Pin 2 is higher than
that of the threshold voltage at Pin 3.
Thus, the comparator output’s Pin 7
goes high. As reset remains high, the
reset SOC of AND gate IC2 goes high
after a propagation delay. This action
resets the SOC.
In Figure 4, the I/O voltage (Trace
B) powers on first, and the core volt-
age (Trace A) follows. This case is sim-
ilar to that in Figure 3 except that the
core voltage powers up faster than the
R6/C1 time constant. The comparator’s
IC1 output, Pin 7, goes high when the
core voltage turns on, and the voltage
at Pin 2 crosses the threshold of 1.65V
that resistor divider R1/R2 sets. How-
ever, the output reset’s SOC signal goes
high only when capacitor C1 charges
to the logic-high level. AND gate IC2A
then produces a high signal to reset the
SOC.EDN

3.3V I/O
VOLTAGE
1.8V
CORE
VOLTAGE

R5 R6 R4
R2 10k 10k 5k
5k 8
5 2
2 IC2A
� IC 6 RESET IN 3 RESET
E 1 7 1 74LS08N SOC
LM311N
3 �
R1 1.65V
1
10k S REFERENCE 4 C1 �
A VOLTAGE 10 �F S1
2

Figure 2 When the core voltage (Trace A) powers up before

Figure 1 This circuit for reset conditioning uses a comparator the I/O voltage (Trace B), the reset signal (Trace D) waits for
and an AND gate. the capacitor to charge.

edn091022di45521 DIANE
(PLACED IN THE 10-22 FOLDER)

Figure 3 When the core voltage (Trace A) is late, the reset- Figure 4 The reset signal (Trace D) goes high after both
SOC signal (Trace D) remains low. voltages come up and the capacitor charges.

December 3, 2009 | EDN 43

designideas
Circuit provides simpler ming interface). You can download
the easy-to-use, free PonyProg soft-

power-supply-sequence testing ware from Lancos (www.lancos.com/

prog.html) and also obtain the sche-
Dan Karmann, DLK Engineering, Thornton, CO matics for the programming circuits.
The circuit in Figure 1, like the


A previous Design Idea (Ref-
erence 1) describes a three-IC
control circuit for testing the power se-
quencing of an SOC (system on chip).
Although that circuit lets you control
the power-on sequence of two linear
power supplies, it uses one eight-pin
IC, two 14-pin ICs, several discrete
components, and a DPDT (double-
pole/double-throw) switch for the con-
trol. Replacing most of those compo-
nents with an inexpensive, eight-pin
microcontroller simplifies power-sup-
ply-sequencing control because the ap-
proach requires less wiring for compo-
nent interconnections. The approach
is also more versatile because it in-
volves only simple changes to the con-
trolling firmware. The simplicity and
versatility come at approximately the
same component cost.
A disadvantage of this circuit com-
pared with the original is that it re-
quires the appropriate firmware for the
microcontroller, an Atmel (www.atmel.
com) ATtiny13. However, free tools
are available that let you develop and
program the microcontroller. This De-
sign Idea includes the source code for
the operation of the sequencer in both
Basic and C. You can download List-
ing 1, the code, from the online ver-
sion of this Design Idea at www.edn.
com/091203dia.
The demo version of the Bascom-
AVR Basic compiler is fully func-
tional and code-limited to 4 kbytes—
four times the code space in the AT­
tiny13—and is freely downloadable
for noncommercial development from
MCS Electronics (www.mcselec.com).
The WinAVR (winavr.sourceforge.
net) tools used in this Design Idea use
the GNU GCC C/C11, a fully func-
tional, free open-source GNU GCC
compiler. You can easily integrate the
WinAVR compiler into the free IDE
(integrated development) AVR Stu-
dio from Atmel. To program the Atmel
microcontrollers, you can use free soft-
ware tools through the microcon-
troller’s six-pin SPI (serial-program-
circuit in Reference 1, includes two
TPS75501 regulators, IC2 and IC3. This
new circuit needs only IC1, an eight-pin
microcontroller; S1, an SPST (single-
pole/single throw) pushbutton switch
to start the sequence; S2, an SPST tog-
gle switch, or a two-pin header with a
jumper, to control the sequence order;
and potentiometer R3 to control the
sequence delay. According to the firm-
ware in Listing 1, pressing S1 when S2
is open causes the micro­controller to
first turn on the 1.5V power supply and
then turn on the 3.3V power supply
following a delay that potentiometer
R3 controls. Pressing S1 when switch
S2 is closed causes the microcontroller
to first turn on the 3.3V power sup-
ply and then turn on the 1.5V power
supply following a delay that potenti-
ometer R3 controls. As with the origi-
nal Design Idea, a second press of S1
causes the power supplies’ turn-off to
take place in the same sequence and
with the same delay as their turn-on.
This scenario provides an opportunity

VIN
5V

IC2
TPS75501
2 4 VOUT1
IN OUT 1.5V
1 5
EN FB R4
IC1 3 D1
GND 10k
ATTINY13 R3 RED
1 8
PB5/RST VCC 10k C5 � R5
DELAY 47 �F R8
2 PB3 7 30k
PB2 1k
3 6 PS1 EN
PB4 PB1
5 PS2 EN
4 GND PB0 IC3
TPS75501
2 4 VOUT2
C1 IN OUT 3.3V
SEQUENCE 1 5
0.1 �F EN FB R6 D2
S2 3
TRIGGER S1 GND 50k GREEN
OPEN=PS1, PS2
CLOSED=PS2, PS1
C6 � R7 R9
47 �F 30k

Figure 1 This circuit needs only an eight-pin microcontroller, an SPST pushbutton switch, an SPST toggle switch, and a
potentiometer to control the sequence delay.

44 EDN | December 3, 2009

designideas
for an easy enhancement or change in
operation.
The voltage level on Pin 7 of IC1
determines the delay, under firmware
control, between turning on or off the
first and the second power supply. The
microcontroller reads this delay voltage
with its 10-bit ADC and uses the value
to determine the delay according to the
following equation: Delay5(VDELAY/
VCC)3102431 msec, where VDELAY is
the delay voltage. This equation yields
a delay range from a few microseconds
to a bit more than 1 second. As an ex-
ample, if the delay-voltage value from
R3 is the midwiper value of 2.5V, the
sequencing delay is approximately 512
msec: (2.5/5V)3102431 msec. The
delay value is approximate because the
micro­controller uses its internal 9.6-
TRIGGER
SEQUENCE
PS1_EN
PS2_EN -- DELAY --
(a)
TRIGGER
SEQUENCE
PS1_EN
-- DELAY --
PS2_EN
(b)
Figure 2 The timing sequence shows the power sequence for S1 (a) and S2 (b).
EDN091203DI4573FIG2
Inexpensive power switch includes
submicrosecond circuit breaker
Anthony H Smith, Scitech, Bedfordshire, England

The circuit in Figure 1 lets
you switch high-voltage power
to a grounded load with a low-volt-
age control signal. The circuit also
functions as a submicrosecond circuit
breaker that protects the power source
against load faults. Power switches to
the load when you apply a logic-level
signal to the output control terminal.
When the signal is lower than 0.7V,
transistor Q3 is off and the gate of P-
channel MOSFET Q4 pulls up to the
46 EDN | December 3, 2009
MHz RC oscillator to generate the tim-
ing with a simple firmware delay loop.
The code in Listing 1 follows the
original Design Idea in that a sec-
ond press of trigger switch S1 causes
the power supplies to turn off in the
same sequence and with the same
delay with which they turn on. The
listing includes a constant off_se-
quence that you can change to
change the turn-off sequence with
the second press of S1 (Figure 2). This
constant OFF_sequence is cur-
rently sequence_same to operate
as the original Design Idea did, but if
you set the OFF_sequence to se-
quence_reverse, the turn-off se-
quence will be in the opposite order of
the turn-on sequence. Alternatively, if
you set the constant off_sequence
MIKE
positive supply through R6, thus hold-
ing Q4 off. During this off condition,
the circuit’s quiescent-current drain
is 0A.
A 3 to 5V signal at the control termi-
nal turns on Q3, which pulls R7 to 0V,
providing gate drive for Q4. The MOS-
FET now turns on and sources the load
current, IL, through sense resistor R3 to
the load. If R3’s and Q4’s on-resistanc-
es are smaller than the load resistance,
the magnitude of the supply voltage,
to sequence_none, both power
supplies will turn off at once. This fea-
ture exemplifies the versatility of this
follow-on Design Idea with a simple
firmware change. Because the circuit
uses only about half the code space
in the ATtiny13, you could easily add
other desired changes. Although this
circuit uses an Atmel micro­controller,
you can use almost any low-pin-count
microcontroller with a built-in ADC.
However, other brands may not have
the readily available free development
tools that exist for Atmel devices.EDN
R e fe r e nce
1 Ban Hok, Goh, “Circuit eases
power-sequence testing,” EDN, July
9, 2009, pg 50, www.edn.com/
article/CA6668618.
VS, and the load resistance mainly de-
termine the load current.
Under normal load conditions, the
sense voltage developed across R3 is
too small to bias Q1 on; thus, Q1 and
Q2 are both off. If, however, the load
current increases, the voltage across R3
may become large enough to turn on
Q1. At that point, base current flows
through R4 to Q1, and Q1’s collector
current in turn provides base current
for Q2. As Q2 turns on, it provides extra
base drive for Q1, and the two transis-
tors rapidly latch in the on-state.
With Q1 saturated, its collector
pulls D2’s anode to the positive sup-
ply, which clamps Q4’s gate voltage to
a diode drop below VS. Without gate
designideas
drive, the MOSFET turns off, �VE SUPPLY R3
Q4 test circuit using the values
OUTPUT
and IL falls to 0A. With Q1 in Figure 1 trips at a load
and Q2 both latched on, Q4 re- R4 current of 70 mA. The actual
mains off, which protects the 1k
R6 trip point varies slightly with
power source from excessive Q1 100k temperature and depends on
IL
load currents. You can reset D2 the device you use for Q1,
the circuit breaker simply by so be prepared to adjust the
taking the control signal low R1 R5 value of R3 to achieve the de-
� 10k
or by cycling the power. The SUPPLY 10k sired trip current.
VOLTAGE
resistance values in Figure 1 VS
�
R7 In addition to providing a
Q2
are suitable for operation at 100k latching function, the posi-
supply voltages of 20 to 30V. D1
LOAD tive feedback loop around
Assuming that the transistors R2 Q1 and Q2 ensures that the
are suitably rated, the circuit 100k OUTPUT
R8 CONTROL ON circuit breaker responds
can operate at much higher Q3
10k quickly to an overload cur-
voltages, but you must scale rent. The actual trip time
OFF
the resistor values accordingly. depends somewhat on the
Operation at a voltage as low 0V magnitude of the fault cur-
as approximately 5V is also rent. With a supply voltage
possible, but you may need to Figure 1 This inexpensive power switch incorporates a of 24V and with R3 having a
reduce the values of R1 and submicrosecond circuit breaker. value of 6.8V, the test circuit
R5 to ensure proper drive for takes 6 msec to trip at a fault
Q1 and Q2. Resistors R6 and R7 form a cause avalanche breakdown. current of 80 mA. However, increasing
potential divider, which sets Q4’s gate- When selecting components, choose the fault current to 200 mA results in a
to-source voltage, VGS, to a value large high-gain devices for the bipolar tran- trip time of just 500 nsec.
enough to enhance the MOSFET fully sistors and ensure that D2 has low re- Capacitive loads, filament bulbs, and
when Q3 is turned on. verse-leakage current; avoid using a motors exhibit a large inrush current
At low supply voltages, you may Schottky diode. In the off-state, each and could cause the circuit breaker to
need to change the ratio of R6 to R7 transistor has the full DIANE
edn091022di45641 supply voltage trip when the control signal goes high
(PLACED IN THE 10-22 FOLDER)
to ensure that the gate-to-source volt- across its collector-to-emitter or drain- even though the normal, steady-state
age is large enough to provide adequate to-source terminals, so ensure the max- load current is below the trip thresh-
gate drive for Q4. When the circuit is imum voltage ratings across these ter- old. If this scenario is likely to be a
operating at high voltages, you may minals are greater than the maximum problem, consider connecting R7 to a
need small-signal diode D1 to prevent supply voltage. separate transistor so that you can in-
reverse avalanche breakdown of Q2’s The circuit breaker trips at a load- dependently control the circuit breaker
base-to-emitter junction when Q3 is current threshold: IL(TRIP)Q0.5V/R3. For and the power switch. This approach
off. However, you can omit D1 at low example, with a supply voltage of 24V lets inrush current subside before en-
supply voltages, which are too small to and with R3 having a value of 6.8V, a abling the circuit breaker.EDN

Create a DAC compare the output voltage with the

desired value and calculate the error.
from a microcontroller’s ADC If the error value is zero, then the I/O
control block tristates the GPIO pin. If
Vardan Antonyan, Glendale, CA
the error signal is positive or negative,


Few microcontrollers include a
DAC. Although you can easily
find an inexpensive DAC to control
from your microcontroller, you can use
unused peripherals instead of adding
parts. Fortunately, you can convert a
microcontroller’s ADC channel along
with a GPIO (general-purpose input/
output) pin into a DAC. You can
make a DAC by charging a capacitor
to an analog level by driving it high.
You can also discharge the capacitor
by driving it low, or you can hold its
voltage by tristating it (Figure 1). At
first glance, this approach seems like a
crude way to make a DAC. The tech-
nique becomes more plausible, how-
ever, when you use a PID (proportion-
al-integral-derivative) algorithm and
monitor the voltage with the micro-
controller’s ADC.
You can use the PID algorithm to
then the I/O control block turns the I/
O pin to a high state to charge the ca-
pacitor or to a low state to discharge it.
Your microcontroller code should load
the error value into a timer to gener-
ate a timed pulse. The error-value sign
determines the charge/discharge cycle,
and its magnitude determines the du-
ration of the pulse. Once the cycle is
complete, you can set the I/O pin to a
tristate mode, which holds the value.

48 EDN | December 3, 2009

designideas
MICROCONTROLLER
The algorithm can run as a software
DESIRED OUTPUT VALUE
loop. You can call it based on another PID
timer interrupt. To minimize the re- ALGORITHM
sponse time, make sure that this algo- ADC MEASUREMENT
ERROR
rithm runs at the desired output value
slightly longer than 2.2RC. You need I/O
the extra time to completely charge R1 HIGH CONTROL
LOW
or discharge the capacitor through DAC OUTPUT Z
resistor R1. C1 TIMER
The DAC’s resolution depends on DELAY

several factors, the foremost of which

is ADC resolution. The DAC’s resolu-
tion never exceeds that of the ADC.
Variable selection and timer resolution
also affect DAC resolution. To imple-
ment a 10-bit DAC, you need a 16-bit
timer and 16-bit variables for the PID
algorithm. You can use a lower-reso-
lution timer, but you must more fre-
quently call the algorithm. That ac-
tion results in longer settling times and
higher CPU usage.
By adjusting the algorithm’s PID
variables, you can achieve surprising-
ly good output settling times with lit-
tle change to the DAC’s output after
settling. The stability of the ADC’s
I/O
TRISTATE
Figure 1 You can develop a PID algorithm to control pulse width and time, thus
creating a DAC from a general-purpose I/O pin. Use the ADC as part of the
feedback loop.
voltage reference limits temperature rate by running the algorithm faster
stability. Neither the temperature sta- than the 2.2RC period and using an
bility of R1 and C1 nor the leakage of 8-bit timer. To buffer the DAC out-
C1 has an adverse effect on the DAC’s put, use an op amp as a voltage follow-
EDN091203DI4593FIG1 MIKE
stability. The selection of R1 and C1 er or use a common emitter follower.
depends on the application, and you You can use a noninverting amplifier
should select them based on set- to amplify the output and feed just a
tling time. For relatively slow-acting portion of it to the ADC through a
DACs, you can increase the update voltage divider.EDN

50 EDN | December 3, 2009

designideas
Edited By Martin Rowe
and Fran Granville

readerS SOLVE DESIGN PROBLEMS

Compact, four-quadrant D Is Inside

lock-in amplifier generates 47 Eight-function remote uses

two analog outputs one button, no microcode

48 Doorbell transformer acts as
Stefano Salvatori and Marco Girolami, simple water-leak detector
Universitã Degli Studi Roma Tre, Rome, Italy
49 Inverted regulator increases


The circuit in this Design Idea use in sophisticated signal-processing choice and reduces complexity
realizes a simple, low-cost lock- applications, including synchronous
in amplifier employing an Analog De- detection. The amplifier can detect a 50 Debug a microcontroller-to-FPGA
vices (www.analog.com) AD630 bal- weak ac signal even in the presence of interface from the FPGA side
anced modulator-demodulator IC noise sources of much greater ampli- ETo see all of EDN’s Design Ideas,
(Reference 1). The device uses laser- tude when you know the signal’s fre- visit www.edn.com/designideas.
trimmed thin-film resistors, yielding quency and phase.
accuracy and stability and, thus, a flex- As an analog multiplier, the AD630
ible commutation architecture. It finds reveals the component of the input- voltage signal in a narrow band around
the frequency of the reference signal.
IC1 The lowpass filter at the AD630’s out-
16 5k
AD630
10k put allows you to gain information on
the weak signal amplitude, which the
1 2.5k 15 uncorrelated noise originally masked.
� �
20 � A
�
A1
19
13
�
When the input voltage and the refer-
17
2.5k �B
� 5V
�
OA2
ence voltage are in phase, the lowpass
VIN
14 10k filter’sEquations
output, Vfor , assumes the max-
OUT0922DI4553 Placed in the 10 − 22
VOUT 0� imum amplitude. Conversely, if the
0� REFERENCE 10
7
VA input voltage and the reference volt-
REF �
age are in quadrature, the output volt-
9 Equation 1
�
8
�5V
age would ideally be 0V. In this way, if
both in-phase and quadrature reference
signals are available,
Equations for 0922two balanced
DI4553 de-in the 10 − 22 fo
Placed
IC2 modulators
VOUT reveal
= Vthe 2 in-phase
+ V
2 output
AD630 OUT 08 OUT 908 ;
16 5k 10k
voltage to be 08 and the in-quadrature
output voltage to be 908. You can cal-
1 2.5k 15 Equation 1
�
A2
�
20 � A culate the module and phase shift as
13
�
2.5k
19 �
OA3
follows:
17
�B
� 5V
�
Equation 2
2 2
14 10k
VOUT 90�
VOUT = V OUT 08 + V OUT 908 ;
7
10
VMON
V 
VR2 � ∠ VOUT = tan1  OUT 908  .
VA
90� REFERENCE 9
�  VOUT 08 
� 8
�5V
OA1 Equation 2
VR1 � The two AD630s have a gain of 62
and receive the amplified signal, VIN,
Figure 1 OA1 integrates the bipolar VA signal and creates a triangular wave. through two identical amplifiers, A1
VR1 and VR2 obtain a 908-shifted reference voltage with respect to VA. and A2. At Pin 7   V, a bipolar
of IC  65V
∠ VOUT = tan 1  1 OUT 908  .
squared signal appears in phase
 VOUT 08 
with

December 15, 2009 | EDN 45

edn091022di45531 DIANE
designideas
the reference signal. OA1 integrates
the amplifier voltage, which generates
a triangular wave that IC2’s compara-
tor compares with the VR2 voltage. You
must regulate VR1 and VR2 to obtain a
perfect 908-shifted command for IC2.
You can monitor the voltage at IC2’s
Pin 7. Measurement accuracy and re-
peatability depend strongly on the RC
time constant of the integrator and the
values of VR1 and VR2.
You can use a different approach
to generate in-phase and in-quadra-
ture reference signals. Figure 2 shows
an all-digital circuit, which you can
implement in a small CPLD (com-
plex programmable-logic device) to
generate the 0 and 908 reference sig-
nals in Figure 1. Counter 1 measures
the reference-signal time in terms of
the N number of digital clock pulses,
where the reference time can be dif-
ferent from 50%. It receives a preset
command at the N151 value at each
positive front edge of the reference sig-
nal. D-type flip-flop IC1 generates such
pulses. At each positive edge of the
reference signal, IC2 acquires the N/4
value. Meanwhile, Counter 2 counts
the clock periods and receives a restart
an increase in the
number of bits
decreases the
maximum refer-
ence frequency.
command at the N251 value when its
value reaches the comparator-mea-
sured N/4 quantity.
To overcome the lack of the last
EQ signal when the reference time is
greater than approximately four times
the N/4 integer value, the OR combi-
nation of the two RST and EQ pulses
yields four almost-equidistant posi-
tive-edge commands in each refer-
ence-time period. The N/4 integer di-
vision, a logical right shift by 2 bits of
N1, gives a maximum error of three on
the last pulse position. These pulses
generate the in-phase and in-quadra-
ture signals, 0 and 908, respectively,
resulting from simple commutations
on the positive or negative edges of
the signal. T-type flip-flop IC3 gener-
ates a signal with twice the frequency
of the reference signal. In this way,
the accuracy is equal to 3/N1.
To maintain accuracy at least com-
parable with that of the AD630, the
N1 output of Counter 1 would be the
highest. However, an increase in the
number of bits decreases the maximum
reference frequency for a given digital-
clock frequency if you want N1 to reach
high values. For example, if N is 15
bits, the N1 output assumes the 32,767
maximum value with an accuracy of
approximately 0.01%. If the reference-
time period decreases, you can assume
a minimum value of 3277—that is,
one-tenth of the maximum value—for
N1, with a correspondingly lower accu-
racy of 0.1%, which is comparable to
the gain accuracy of the AD630. To in-
crease the reference frequency, divide
the digital clock’s frequency to select
low values when the reference time be-
comes too long.EDN
R e fe r e nce
1 “AD630 Balanced Modulator/
Demodulator,” Revision E, Analog
Devices, 2004, www.analog.com/
static/imported-files/data_sheets/
AD630.pdf.

REF

REFERENCE D Q VCC
IC1
Q VCC
COUNTER 1 T Q 0� REFERENCE
2�FREF
N-BIT N�2 N�2 N T Q
1 VCC
COUNTER D Q A IC3
Q1 IC2 A=B
RST Q0 T Q 90� REFERENCE
B

REGISTER COMPARATOR 4�FREF

COUNTER 2
N�2
N2

RST

FREF RANGE: 0.6�6 kHz 60�600 Hz 6�60 Hz 0.6�6 Hz

(N=15)

VCC 20 MHz 2 MHz 200 kHz 20 kHz

RCI RCO RCI RCO RCI RCO

MOD 10 MOD 10 MOD 10
CLK

Figure 2 You can implement this all-digital circuit in a small CPLD.

46 EDN | december 15, 2009

Eight-function remote uses Normally, the output of the NAND
gate is low because both inputs must
one button, no microcode be logic one to produce a logic-one
output to close one of the CMOS
Jay Davis, Boeing Integrated Defense Systems, Wichita, KS switches, IC5 and IC6.


Many people with significant
physical disabilities can’t operate
everyday mechanisms, such as TV re-
mote controls. To make matters worse,
adaptive technologies are often unaf-
fordable unless insurance covers them.
This Design Idea describes an interface
circuit that lets a disabled person con-
trol eight remote-control functions.
The design uses older, small-scale-inte-
gration ICs because of their simplicity,
low power requirements, affordability,
and availability at stores such as Radio
Shack (www.radioshack.com). Because
the circuit uses no micro­controller, you
need not do any programming.
Power for the circuit in Figure 1
comes from four 1.5V AA batteries
in series. Diodes D1 through D4 re-
duce the battery power from 6V to
approximately 3.4V, and they pro-
tect against accidental reverse polar-
ity of the batteries. IC1, a 555 timer,
and associated discrete components
form a repetitive-pulse generator.
Potentiometer R1 adjusts the pulse
speed. This pulse feeds directly into
decade counter, IC2, which causes in-
dicator LEDs LED1 through LED4 to
sequence on and off. Each output of
the decade counter feeds one input of
CMOS gate IC3 and AND gate IC4.
VCC
If the user presses the control switch
while the desired LED is lit, both in-
puts to one of IC3’s AND gates are at
logic one, causing the output to be logic
one and closing a 4066 switch, which
is effectively the same as pressing one
of the buttons on the remote control.
As long as the control switch remains
closed, the 555 pulses remain disabled
and LED1 through LED4 remain in
their current state. This characteristic
is important because a person can con-
tinue to hold the control switch closed
to continuously increment the chang-
ing of a channel or increase or decrease
the volume.EDN

REMOTE
VCC VCC CONTROL
R4
1k
8 4 16
4081 IC5
5 4066
4
3 6 IC3A 3
CH�
LED1 4
R2
1.8V 4081
15k 1 4066
2 mA
2 IC3B 3 1
2 CH�
7 IC1 3 14 IC2 LED2 2
TLC555 4017 1.8V 4081
9 4066
D5 D6 D7 2 mA 10 8
1N4001 1N4001 1N4001
4 8 IC3C VOL�
6 LED3 9
R3 R1 1.8V 4081
1k 5 4066
1M 2 mA 4
2 7 6 IC3D 3
VOL�
CLK ENB LED4 4
C1 1.8V
4.7 �F 8 13 6 5 1 10
2 mA
4081 IC6
9 4066
10
8 IC4A 8
VCR
LED5 9
1.8V 4081
D1 D2 D3 D4 13 4066
2 mA 11
1N4001 1N4001 1N4001 1N4001 12 IC4B 10
CABLE
3.4V
LED6 11
VCC 4081
1.8V 1
2 mA 3 4066
FOUR 2 IC4C 1
AA TV
LED7 2
BATTERIES 4081
1.8V 13
2 mA 11 4066
12 IC4D 10
POWER
LED8 11
1.8V
2 mA

R5
1k

Figure 1 This interface circuit allows a disabled person to control eight remote-control functions.

December 15, 2009 | EDN 47

edn090903di45351 DIANE
designideas
Doorbell transformer acts ever, if you only infrequently visit the
attic, you may not discover that your
as simple water-leak detector hot-water heater is leaking until it is
too late. By that time, it may cost you
Jeff Tregre, www.BuildingUltimateModels.com, Dallas, TX hundreds of dollars to repair the water
damage to ceilings and walls.


Shortly after installation, the
simple water-leak-detector cir-
cuit in this Design Idea saved the day
and hundreds of dollars. The average
life expectancy of a hot-water heater
is about 10 years. It’s not a question of
whether it will leak; it is simply a mat-
ter of when it will leak. The builders
of new homes in the Midsouth region
of the United States have been install-
ing hot-water heaters in attics. This
approach saves valuable space; how-
The circuit in Figure 1 detects hot-
water-heater leakage, and you can also
use it for detecting leaks in dishwashers,
garbage disposals, ice makers, swimming
pools, hot tubs, and waterbeds. Figure
2 shows the completed circuit.
Most doorbell transformers produce

DOORBELL TRANSFORMER D1 D2

� �
TO 120V AC 16V AC

D4 D3
26V DC

�
C1
R1
220 �F
5.1k
PUSH TO TEST 35V

S1 NO 6V DC
WATER PROBES
R5 R2 2N3906
R4 10k 2N2222A 10k
10k Q1
Q2
R3 �
10k

6V PIEZOELECTRIC
SPEAKER

Figure 1 A transformer and a bridge provide power for the

speaker. Figure 2 The circuit includes a push-to-test button.

edn090917di45581 DIANE
(PLACED IN THE 10-8 FOLDER)

Figure 4 The completed probe

with bare wire inside senses water
Figure 3 Use a sponge and copper wire to form a water probe. through a change in resistance.

48 EDN | december 15, 2009

16 to 20V ac. To drive the buzzer, you
must convert the ac voltage to dc: Mul-
tiply the ac voltage by 1.414 to yield
the dc-rms voltage. Connect the wires
to the secondary side of the transform-
er to a bridge rectifier and then into
a filtering electrolytic capacitor. Your
power supply should now be providing
about 26V dc. The 5.1-kV resistor, R1,
limits the current to the buzzer. When
the system detects water or when you
press the push-to-test switch, you have
about 6V dc to operate the circuit and
sound the piezoelectric speaker. Mount
the speaker so that you’ll hear it when
it sounds.
Transistors Q1 and Q2 can be any
general-purpose NPN and PNP types,
respectively. The water probes use cop-
per wires about 1 in. apart from each
other. You then pierce two holes, about
1 in. apart, into a sponge from a sol-
dering station. Insert bare copper wire
into these holes (Figure 3). Take some
of the remaining wire but leave the in-
sulation on it and wrap it around the
sponge so that the bare copper wire
does not come out (Figure 4).
You can now place this sponge in
the metal overflow tray underneath
the hot-water heater. When the hot
water leaks, the sponge absorbs it.
The resistance between the two bare
copper wires then drops to about 1
MV or less, which forward-biases the
two transistors and enables the piezo-
electric speaker. The cost for this cir-
cuit shouldn’t exceed $25. If you have
more than one hot-water heater in the
same area, you can make another water
probe and tie the two probes together
in parallel.EDN

Inverted regulator increases choice can detect a voltage increase indi-

cating overcurrent through a resistor
and reduces complexity that connects between the load and
ground. To do the same thing on the
David McCracken, Aptos, CA
high side, you typically select a dif-


Most circuits are referenced to control the low side of a load but not ferential amplifier that tolerates high
ground, where relatively low- the high side. For example, nearly any common-mode voltage. This approach
voltage components can monitor and low-voltage rail-to-rail-input op amp limits the component choices for the

AUTO-RESET 24V 23.5V 24V 24V

R8
TIMER
23.5V REFERENCE 100k
GENERATOR 24V �
12V
24V C1 R3 R10 R12
0.1 �F 178k 0.33 0.33
R13 D3 D4 9 16V 1% 1W 1W
1N4148 1N4148 � R2
435 IC1C
8 100k 6
1% TLV2374 10 �
23.5V 1% 7 IC2B
� TLV2374 5
R14
10k D1 �
1% 1N4148
R7 R1
R9 47k 10k 6
12V �
100k 1% 1% 7 IC1B
12V 12V TLV2374 5
12.4V REFERENCE
GENERATOR D2 �
24V R5 1N4148
12 R4 47k 24V
12.4V � 47k
R15 IC1D 14 Q2
10k TLV2374 FDC5614P
13 MOTOR
1% � 24V VDD
R6 12V 3 4 DRIVER
12.4V �
22k 2N2907 IC2A PH1 VS
R16 C3 1
345 R11 6.8 �F TLV2374
Q1 2
1% LED1 1k 16V �
11
OPTIONAL TANTALUM
GND
12V VISUAL
INDICATOR
24V 12V
24V
1 C2 Q3
GND 6.8 �F FDC5614P
IC3 VDD MOTOR
16V
3 4 DRIVER
2 LM320T-12 3 � PH2 VS
GND VI VO 12V C4 IC1A 1
6.8 �F TLV2374
2
16V � 11
TANTALUM
GND
NOTES:
THE VI PIN CONNECTS TO CIRCUIT GROUND, AND THE GROUND PIN CONNECTS TO THE 24V.
THE �24V REGULATOR GENERATES 12V REFERENCED TO 24V. 12V

Figure 1 Current-sense resistors turn off MOSFETs when current through them exceeds a limit.

December 15, 2009 | EDN 49

designideas
input amplifier and brings up the ques-
tion of how to respond to an overcur-
rent. The differential amp produces a
low ground-referenced signal from a
high-side event, but you can prevent a
high-side overcurrent resulting from a
short to ground only by turning off the
high-side power. In effect, the differen-
tial amp translates the high-side signal
into the low-side domain in which you
must then translate the response back
into the high-side domain.
A simpler approach for any high-side
overcurrent-protection circuit refer-
ences the entire circuit to the high-side
rail. Such circuits typically consume
little power, which a small, three-ter-
minal linear regulator can easily supply.
However, this approach requires an un-
usual configuration employing a nega-
tive regulator whose ground pin con-
nects to the high-side rail and whose
input connects to system ground.
There are no other connections to sys-
tem ground. All “ground” points of the
overcurrent-protection circuit connect
to the regulator’s out pin.
Figure 1 shows a two-phase-stepper-
motor, fast-acting, self-resetting high-
side circuit breaker with a 24V power
supply to the motor and a 12V power
supply to the circuit breaker that is ref-
erenced to 24V. The circuit breaker
sees the 24V motor’s power rail as 12V
referenced to its local ground, which
the regulator’s output provides. Like all
negative linear regulators, the circuit
requires a 6.8-mF tantalum capacitor.
R10 and R12, both 0.33V, 1W resis-
tors, provide current sensing for the
two phases. High-side power flows
through a sense resistor and a P-chan-
nel MOSFET to the high-side input of
an H bridge (not shown), which drives
one motor winding. Current in either
phase can cause the sense voltage to
increase to 0.5V, triggering the break-
er. The circuit responds by turning off
both MOSFETs. It then waits 20 msec
and turns them back on, automatically
clearing momentary shorts.EDN

Debug a microcontroller-to-FPGA data-capture circuit, the JTAG commu-

nication circuit, and the GUI (graphi-
interface from the FPGA side cal user interface). The data-capture
circuit uses standard HDL (hardware-
Bibo Yang, Sunrise Telecom, Beijing, China description language) and instantiates
a FIFO (first-in/first-out) buffer in the
 Microcontrollers and FPGAs write transactions on the microcon- FPGA. Whenever you read or write to
often work together in embed- troller/FPGA interface. This method a register, the debugging tool records
ded systems. As more functions move is nonintrusive because the circuit that the corresponding value of the address
into the FPGA, however, debugging captures transactions sits between the and data on the bus and stores it in the
the interface between the two devices microcontroller and the FPGA’s func- FIFO buffer. You can retrieve the data
becomes more difficult. The tradition- tioning logic and monitors the data through the JTAG’s download cable to
al debugging approach comes from the without interfering with it. It stores the PC (Listing 1, which is available
microcontroller side, which relies on the captured transaction in the FPGA’s in the online version of this Design
a serial-port printout. This approach RAM resources in real time. You can Idea at www.edn.com/091215dia).
adds overhead and may cause timing transfer the data to a PC through the Because the FPGA has limited on-
problems. Furthermore, this approach JTAG port’s download cable. chip RAM resources, you must keep
cannot guarantee uninterrupted and The debugging tool comprises the the FIFO buffer shallow. To efficient-
exclusive access to cer- ly use the FIFO buffer,
tain addresses because the design includes filter
of operating-system and trigger circuits. With
multitasking. Thus, TRANSACTION inclusive address filter-
FILTER
a serial-port printout FROM JTAG ing, the circuit monitors
doesn’t accurately de- TRANSACTION- TRANSACTION- only several discontinu-
CAPTURING
scribe the actions on LOGIC WITH
CAPTURING ous spans of addresses
FIFO BUFFER
the microcontroller/ FILTER AND TO JTAG instead of the whole ad-
TRIGGER
FPGA interface. TRANSACTION
dress space. Exclusive-ad-
Instead, you can ap- TRIGGER dress filters can filter out
proach the problem FROM JTAG several smaller address
from the FPGA side spans from the inclusive-
using a JTAG (Joint address spans, enabling
up_addr up_data up_cs up_wr up_rd
Test Action Group) finer control of the filter
FROM MICROCONTROLLER
interface as a commu- settings (Listing 2, which
nication port. This ap- is also available in the on-
proach uses the inter- Figure 1 The JTAG’s vendor-supplied, customizable communi- line version of this Design
nal logic of the FPGA cation circuit has two interfaces. Idea at www.edn.com/
to capture the read/ 091215dia).

50 EDN | December 15, 2009 edn091112di45601 DIANE

(PLACED IN THE 11-26 FOLDER)
designideas
With transaction triggering, the cir-
cuit starts when you read from or write
to a certain address. You can add cer-
tain data values to the triggering con-
dition (Listing 3, which is available in
the online version of this Design Idea
at www.edn.com/091215dia). You can
dynamically reconfigure the settings of
address filters and transaction triggers
through the JTAG’s vendor-supplied,
customizable communication circuit
without recompilation of the FPGA
design (Figure 1). The circuit has
two interfaces, one of which is written
in HDL to form a customized JTAG
chain. It communicates with the user
logic (listings 1, 2, and 3). The cir-
cuit is accessible through specific pro-
gramming interfaces on the PC and
communicates with the user program
or GUI (Listing 4, which is available
in the online version of this Design
Idea at www.edn.com/091215dia).
The FPGA-based circuit facilitates
writing and reading functions from PC
to FPGA logic, and it promotes the
52 EDN | December 15, 2009
JTAG interface to a general commu-
nication port attached to the FPGA.
FPGA manufacturers, including Actel
(www.actel.com), Altera (www.altera.
com), Lattice Semiconductor (www.
latticesemi.com), and Xilinx (www.
xilinx.com), respectively, call this
circuit UJTAG (user JTAG), Virtual
JTAG, ORCAstra, and BScan (refer-
ences 1 through 4).
The GUI for this circuit uses Tcl/Tk
(tool-command-language tool kit).
FPGA manufacturers provide ven-
dor-specific APIs (application-pro-
gramming interfaces) in Tcl for the
PC side of the JTAG-communication
circuit. The APIs include basic func-
tions, such as JTAG-chain initializa-
tion, selection, and data reading and
writing. With the data-read function,
you can check the capturing status
and get the transaction data from
the FIFO buffer. With the data-writ-
ing function, you can send the filter
and trigger configuration data to the
capturing circuit in the FPGA (List-
ing 4). The JTAG-based debugging
method provides dynamic visibility
and controllability into the micro-
controller-to-FPGA interface and the
FPGA’s internal logic without the
need to recompile and download
FPGA code.EDN
R e fe r e nce s
1 “How to Use UJTAG,” Applica-
tion Note AC227, Actel Corp, 2005,
www.actel.com/documents/Flash_
UJTAG_AN.pdf.
2 “Virtual JTAG (sld_virtual_jtag)
Megafunction User Guide,” Altera,
December 2008, www.altera.com/
literature/ug/ug_virtualjtag.pdf.
3 “ORCAstra FPGA Control Center,”
Lattice Semiconductor, www.lattices-
emi.com/products/designsoftware/
orcastra.cfm.
4 Wallace, Derek, “Using the JTAG
Interface as a General-Purpose Com-
munication Port,” Xilinx, 2009, www.
xilinx.com/publications/xcellonline/
xcell_53/xc_jtag53.htm.