CMOS IC Design from Schematic Level to Silicon
within IC Curricula Using Free CAD Software
Aleksandar Pajkanovic
Faculty of Electrical Engineering
University of Banja Luka
Banja Luka, Bosnia and Herzegovina
aleksandar.pajkanovic@etf.unibl.org
Abstract—In this paper we demonstrate the free and open-
source methodology used to design integrated circuits all the
way from schematic level simulation to silicon-ready GDS
fabrication files. This approach has been successfully
implemented in the IC design curricula at the Faculty of
Electrical Engineering, University of Banja Luka. The example
circuits are known designs of a low-dropout regulator and an
oscillator. The CMOS technology node is 180 nm process. Each
of the tools is briefly presented, and either of the two designs is
shown during different design phases.
Keywords—IC design, analog, LDO, oscillator, free and open-
source tools, ngspice, netgen, Magic
I. INTRODUCTION
Fabrication of monolithic integrated circuits (IC or chip)
on silicon represents one of five technologies crucial to
semiconductor industry and, therefore, human society in this,
21st, century [1]. Even though its performance rise due to
constant scaling has been significantly slowed down in
comparison to the previous half a century, it is still one of the
most sophisticated technology processes commercially
available in the world. This came to pass due to incredible
scale of integration, which, in return, allowed mass IC
production at negligible price per unit produced. Nevertheless,
contrary to the end product unit price, as low as several cents
for the most common chips, the cost of design, fabrication,
packaging and testing of an IC has been soaring all along. It is
first very costly to train an engineer, then it costs hundreds of
thousands to obtain a yearly license of an industry standard
software toolchain, whereas fabrication in the modern process
node may cost well into millions. Verification usually takes
up to 30% of the whole project cost.
The only phase in this process the community may
significantly reduce the price of, thanks to the free and open-
source movement and the copyleft philosophy behind it, is
obtaining the software licenses. The freely available IC tools
have been around for decades, but their quality has been
questionable all along and, thus, application in a real process
unfeasible. However, this idea of reducing the required CAD
software tools pricing to zero, with the purpose to enable
individuals or small teams to actually design their circuits all
the way to silicon has been gaining momentum in recent years
worldwide. An overview of these activities is out of scope of
this paper, so we note here the world’s first ever chip
successfully designed and fabricated using only free and open-
source tools, Raven [2].
In the past four years, at the Faculty of Electrical
Engineering, University of Banja Luka, we have been working
to introduce a free (of charge) integrated circuits design
software toolchain into the IC courses. The integrated
development environment, present with industrial standard
EDA/CAD toolchains does not exist yet, but every step of the
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process is covered with individual free and open-source
software tools. These tools, for the most part, we have utilized
in previous IC courses iterations, [3]-[4]. Still, every IC design
we presented up to now was simulated, laid out and extracted
using component models from academia [5]-[6] and an
SCMOS project design kit (PDK) [7]. This means that these
are not silicon-ready, meaning further that they have no
purpose outside the classroom. It is, of course, a valuable
practical experience for students, but it is not a real-world
hands-on example – a feature required for a serious, world-
class university level course.
In this paper, we present silicon-ready designs – simulated,
laid out and extracted using a silicon-ready PDK, i.e. a
commercially available, industry standard CMOS 180 nm
process node. Neither of the schematic level designs are novel,
one being presented in [8] and the other being a standard
topology [9], commercially available. The contribution of this
paper is the first ever design of silicon-ready CMOS ICs in
class as a collaboration between staff, students and industry
partners, using nothing but free and open source software
tools.
In section II, we elaborate in further detail on the
motivation behind this paper. In sections III and IV we provide
brief overview of the example designs and tools, respectively.
The next two sections, V and VI, present post-layout
simulation results and silicon ready layouts, respectively. A
conclusion follows as the final section of this paper.
II. MOTIVATION
Scaling down to deep submicron processes benefited the
digital applications, in terms of increasing performance and
integration scale, while reducing latency, supply voltage and
power consumption. The benefit, while present, is not so
direct for analog circuits. While the reduced device size
increases transit frequency, decreases leakage and power
consumption, there are additional topics that need special
attention, such as gain or noise. Furthermore, analog
applications require passive components, capacitors and
resistors, whereas RF applications add inductors and
transformers on top of the arsenal. Therefore, using a process
node below 45 nm for analog/RF ICs presents significant
challenges [10]-[11]. This is even more so in the case of GHz
frequencies and beyond, where specialized software tools
capable of electromagnetic field simulation must be utilized.
Tools provided by semiconductor industry standard
CAD/EDA companies (Cadence, Synopsys and Mentor) are
irreplaceable when cutting edge technology designs are in
question, such as 7 nm process node used for latest release of
AMD’s Zen 2 microarchitecture [12]. The same statement is
valid for analog/RF designs, with the slight change in the
meaning of the term “cutting edge”, since in this case that
would relate to 45 or 65 nm process nodes. However, there are
 still many cases where mature CMOS technology can perform
accordingly. The best examples are low noise amplifiers [13],
power amplifiers [14], operational amplifiers [15], voltage
regulators [16], bandgap reference [17], etc. In all these
examples, the circuits have been implemented in 180 nm
process node in 2020, even though this technology was
commercialized as early as 1998. It is, therefore, still justified
to both teach real-world silicon-ready examples and research Fig. 2. Crystal oscillator driver schematic [9]
novel topologies and applications in mature CMOS nodes.
IV. TOOLS
Having proved actuality of 180 nm CMOS standard
IC design process may be captured as shown in Fig. 3,
technology in today’s semiconductor industry, it is important
where each step of the process is paired with the appropriate
to actualize as well the free and open source software IC
tool we used in this work, following along the ASICone
toolchain – from schematic level design all the way down to
project. Since we are taking already designed circuits, this
silicon. We argue that this is of major importance, since
means we will be skipping topology selection, but rather focus
success in such enterprise, in many cases, would enable an
on schematic level design first. In papers [3]-[4] as the
absolute reduce in cost for both academia and individuals or
schematic entry tool XCircuit [21] has been suggested and this
chip startups, when IC software tooling is in question. Steps
practice remains. Schematic level simulation is performed by
of essence in that direction have been taken. To successfully
ngspice [22]. Even though we proposed to use python libraries
fabricate Raven [2], the authors used the efabless
for post-processing, in order to keep aligned with
platform [18], which represents a collection of free and open
collaborators leading this effort from project ASICone, within
source CAD tools. Another approach, ASICone, is presented
this paper Octave [23] is used for this purpose. The circuits
in [19] and demonstrated in [20]. ASICone is an experiment,
have been laid out using Magic [24]. Layout and schematic
with no commercial goals, devised with the purpose to prove
are kept consistent through LVS checks by netgen [25].
it is possible to build real silicon with open source tools only.
Finally, post-layout simulations are performed using ngspice
The main motivation for the work presented in this paper once again.
is to join the effort to first demonstrate real silicon examples
designed using only open source tools, and, then, to popularize
these tools, the technology and electronics in general, by using
this methodology to build world class, university level IC
courses that can fuel both research and chip startups in years
to come.
III. EXAMPLE DESIGNS
As the main focus in this work is taking a schematic
through the free and open-source toolchain all the way to
silicon-ready GDS files, we selected two circuit designs
already fabricated in silicon as examples: a low-dropout
voltage regulator (LDO) and a crystal oscillator driver. The
LDO design is presented as a novelty in [8], whereas the
crystal oscillator driver topology is common [9], thus it is far
simpler to implement. For the details on operation on either of
these, appropriate references should be consulted as principles
of electric circuit operation are beyond the scope of this paper.
For completeness, we present only high level block
schematics in Figs. 1 and 2, respectively.
The main results obtained through post-layout simulation
for each of the circuits are presented in section V.

Fig. 3. Analog IC design process/toolchain: a) general approach, and b)

tools applied in this work for each step given in a)

V. POST LAYOUT SIMULATION RESULTS

Detailed performance analysis for each of the chips is
beyond the scope of this paper. Our purpose here is to prove
that the analog IC design, from schematic all the way to
silicon – as shown in Fig. 3a – is feasible using the tools
presented in Section IV and depicted in Fig. 3b. In that
context we provide in this Section graphical representation of
Fig. 1. LDO block schematic [8]

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 the most significant results achieved by our designs in Figs.
4 and 5. All figures are obtained through post-layout
simulation, i.e. after the circuits have been laid out and
parasitic extraction has been performed.
In Fig. 4 oscillator driver output is shown given the four
different crystal frequencies: 32 KHz in Fig. 4a, 100 KHz in
Fig. 4b, 1 MHz in Fig. 4c, and 25 MHz in Fig. 4d. The crystal
was modelled using the standard RLC approach [9], where
each of the passives is calculated based on the required
frequency to be simulated.

d)
Fig. 4. Oscillations at a) 30 kHz, b) 100 kHz and c) 1 MH and d) 25 MHz

In Figs. 5-8, the most interesting of the LDO characteris-

tics, obtained through post-layout simulation, are presented.
Output voltage is specified at 1.8 V, taking up that value once
the input DC reaches the same. Output remains 1.8, while the
input increases up to 5 V. In Fig. 6 the LDO output is shown
in red and it represents the response to the input sinusoidal
voltage of 2π MHz frequency and 100 mV amplitude.

a)

Fig. 5. LDO DC transfer characteristic.

b)

c) Fig. 6. LDO sinosoidal input (blue) and output (1.8 V) in time.

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 Maximum output current is 50 mA and in Fig. 7 we show
the LDO output voltage drop caused by such an output
current pulse. Recovery time is around 1 µs. Finally, In Fig.
8, LDO output voltage response to variable input voltage
levels is presented.
Fig. 7. LDO output voltage response to an output current pulse
Fig. 8. LDO output voltage response to variable input voltage levels
VI. LAYOUT
In Figs. 9 and 10, both circuits layouts are shown,
respectively. LDO alone takes up an area of 0.12 mm2, while
the whole IC, including the padring, fits in 0.29 mm2.
Fig. 9. LDO layout, including the padring
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Oscillator driver IC is minute, just 12 µm × 15 µm in size
alone, but the padring adds significantly to the total area,
making the whole circuit 0.2 mm2 in size.
Fig. 10. Oscillator driver layout, including the padring
VII. CONCLUSION
We have shown the feasibility of analog IC design process
using only free and open source CAD tools. Given the known
inferiorities in features, especially in design automation, the
selected designs are simpler in the context that we do not
tackle RF frequencies, intensive currents or voltages, nor we
investigate unknown topologies. The next stage is to fabricate
these designs, bond, package and finally characterize them.
We are working on these steps in close collaboration with
industry partners.
ACKNOWLEDGMENT
The author expresses sincerest gratitude to Tim Edwards,
Edmund Humenberger, Niels Mosely and Elkim Roa for
support on both tools and technology while working on this
project. The author also acknowledges the great effort
students, Darko Derajic, Dejan Gutic, Vladimir Kuridza,
Marko Petkovic, Dmitar Plavsic, Nemanja Smitran and Vanja
Zeric have invested and thanks them greatly. Finally, let us all
think for a moment about thousands of people, engineers and
others, who have worked for millions of hours, for nothing but
the satisfaction of creation and the thought that their work
enables others to work further and see farther – let us think
about them, and thank them all.
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