Progress Report

Title of project: Development of Power SiC Based Solid State Distribution Transformer for Smart Grid

SERB Sanction number: IMP/2019/000222 dated 07.02.2020

1. Literature review-

Literature review on different topologies in SST (Solid state transformer) was done, based on which a Type A-2 single
stage ac-ac conversion which consists of two LF stages and one MF stage is selected for its high efficiency and simple
configuration.

Amorphous core material will be considered in high frequency transformer for its better performance than other available
core materials. Literature review for efficient gate driver design for Sic MOSFETs was also done.
Status: Completed.

2. Development of Simulink Model-

In the Simulink model a 3-kV two-level single-stage (TLSS) direct 3-phase ac–ac SST based on SiC MOSFETs is
developed. In MVLF (Medium voltage low frequency) stage a 3-phase uncontrolled rectifier is used whose output is then
fed to MVMF (Medium voltage Medium frequency) stage, Dual half bridge SRC converter is used in MF stage. In the
second stage, resonant capacitors are split into two pairs of capacitors and distributed symmetrically on the MV and LV
sides. Lastly in LVLF (Low voltage Low frequency) stage a three phase inverter is used for 3 phase ac output.

Taking advantage of SiC materials that have much higher peak electric field strength they can enable simple two-level
configuration if the peak voltage is less than 12 kV. The SiC MOSFET is also suitable for high frequency operation due to
its fast switching capability and ultralow switching loss with a ZVS technique.

When considering single stage SST in general, two major technical challenges need to be addressed to apply direct ac–ac
converter in MV applications. The first challenge is to achieve zero-voltage switching (ZVS) over wide input voltage and
load range. ZVS is needed not only for improving efficiency, but also for reducing the noise when power MOSFET
switches at MVs.
Due to the nonlinearity of MOSFET’s output capacitance Coss versus the applied voltage, the ZVS requirements in direct
ac–ac converter are challenging. The second challenge is the need to reduce system capacitance. MV capacitors are
normally large in size due to the MV requirement, and ac voltage applied to capacitors will lead to unwanted reactive
power.

The first challenge is removed by using a three phase ac rectifier in Input stage which makes the input voltage range very
narrow to the MF stage. Since the variation of C oss is more for low voltage and by using a 6-pulse output low-voltage
range can be avoided. The second challenge is removed by using a symmetric half bridge current fed SRC thus
eliminating the use of large size MV capacitors.

Unlike dc/dc applications which only need to design ZVS with constant input voltage or narrow voltage range, the ac–ac
circuit requires a ZVS design across the entire input voltage range. Due to the nonlinearity of the MOSFET’s output

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capacitance (Coss versus its applied voltage) thus ZVS design becomes much more complicated. ZVS design for a single
phase CFSRC if used on a 3-kV input voltage. This would result in extremely wide voltage range from 0 to 4.24 kV.

Fig.1. Symmetric half bridge Current fed SRC (MF stage) [1]

Now considering a single phase direct ac-ac conversion with Input voltage of 7.2kV (V in_ac) [1], the MF stage is shown in
Fig.1. The DHB MOSFET turns OFF at low current and the turn- OFF process is almost lossless (Eoff =0) since the
energy is simply stored in the output capacitance and stored energy is low. Hence, the turn-OFF loss of this device can be
modeled as zero. Now during the turn-ON of the MOSFET a wide range of input voltage will be applied across it.
To achieve ZVS turn-on, the turn-off current needs to be sufficient to fully discharge the Q oss of P1 and P2 during the
given deadtime. Thus the value of deadtime is derived as (ZVS constraint) [1]-

2∗Qoss∗8∗Lm
T dead ≥ (1)
V ds T s

Where, Lm is magnetization inductance of high frequency transformer, Q oss charge stored by output MOSFET capacitance,
Vds is the Voltage applied across MOSFET, Ts is the switching time period. As can be seen from equation (1) it is
noticeable that the ZVS constraint is independent of load conditions, which simplifies the ZVS design. However, Q oss of
the MOSFET is a nonlinear function of the applied voltage V ds (in this case Vin_ac), which means that the ZVS condition
changes with the applied voltage. In a direct ac–ac circuit, the voltage applied to the device is changing from zero to peak
ac voltage.

Therefore, the Qoss of MOSFET versus Vds needs to be quantified first, [2] proposed a very accurate method to measure the
output charge of MOSFETs at MV voltage. Adopting this method, the measured Q oss versus Vds for a single MOSFET is
depicted in Fig. 2. Observing fig.2 we can see at low voltage, change in Qoss is low.

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 Fig.2. Output charge of a 15 kV Sic MOSFEET [2]

Two circuit parameters, Lm and tdead, can be designed to fulfill ZVS constraint in (1). Fig. 3 shows the ZVS criteria for L m
and tdead design. The dashed orange and blue curves are the required critical deadtime over half-frequency cycle under two
different Lm cases. The required deadtime is small at peak ac voltage and increases rapidly when voltage decreases to a
low level.
If deadtime is designed based on these curves, deadtime is nonlinear, and a large deadtime is required to achieve ZVS at
LV. Thus, in practice, it is possible for MOSFETs to experience partial hard switching at low-voltage conditions as long
as the total amount of loss is small. To simplify the deadtime control complexity, a constant dead-time scheme was
proposed in [301] which is drawn as a pink curve in Fig. 3

Fig.3. Dead time vs Input voltage [1]

So in the proposed model a 3-phase ac-ac three phase is used. By using a three phase rectifier in the input MV stage the ac
voltage variation becomes narrow as the output voltage will be a 6-pulse waveform and low voltage variation of input
voltage will be avoided. Thus, using a half bridge Current fed SRC in MF stage ZVS (Zero Voltage Switching) is

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achieved for entire input voltage range (with a constant dead time) which reduces the switching losses significantly for
high Speed switching devices (Sic MOSFETs).

Status: Ongoing

3. Procurement of equipment and components

Purchase of Sic devices has been done partially ( about 5% only). Manufacturers and specifications for high frequency
transformer, power frequency transformer, PCB boards, Heat sinks, Switching devices and other additional components
have been finalized and purchase is under process. The purchase was delayed due lock down and hence request to
grant 6 months’ extension beyond February 2021 to procure equipment and components.

Status: Ongoing

References:

[1] Q. Zhu et al., “on the Current-Fed Series Resonant Converter and 15-kV SiC MOSFET s,” IEEE Trans. Power
Electron. vol. 34, no. 2, pp. 1099–1112, 2019.

[2] L. Wang, Q. Zhu, W. Yu and A. Q. Huang, "A study of dynamic high voltage output charge measurement for 15 kV
SiC MOSFET," 2016 IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016, pp. 1-7,
doi: 10.1109/ECCE.2016.7854789.