1182 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.

5, MAY 2009

Natural Harmonic Elimination of Square-Wave

Inverter for Medium-Voltage Application
Gautam Poddar and Malaya Kumar Sahu

Abstract—In this paper, a low-frequency square-wave inverter

with a series-connected pulsewidth modulation (PWM) inverter is
investigated for high-power applications. The series compensators
produce only the desired harmonic voltages to make the net out-
put voltage sinusoidal with small PWM switching harmonics only.
An open-loop control strategy for the series compensator is pro-
posed in this paper. This strategy indirectly sets the compensator
dc bus voltage to the desired level. No external dc source or active
power at fundamental frequency is required to control this dc bus
voltage. Different variations of this basic strategy are presented
in this paper for medium-voltage applications. Theoretical analy-
sis of this strategy is presented in this paper with simulation and
experimental results.
Index Terms—AC motor drives, power conversion, power con-
version harmonics.

NOMENCLATURE
Vdc DC bus voltage of the square-wave inverter.
Vdch DC bus voltage of the series compensator.
VS Phase voltage with respect to the middle of the dc bus
of the square-wave inverter.
Vh Total harmonic voltage of the square-wave inverter.
Vn h nth harmonic component of the square-wave inverter.
Vload Load voltage.
Pn h Active power due to the nth harmonic component.
I. INTRODUCTION
HE THREE-PHASE two-level pulsewidth modulation
T (PWM) inverter is a highly preferred scheme as a voltage
source inverter for various applications. To make this inverter
output voltage sinusoidal, a simple L–C filter is normally in-
troduced at the output of this PWM inverter. For high-power
applications, the switching frequency of the two-level inverters
is very much restricted due to the limitation of the available
power devices. This introduces increased harmonic current at
the load. It also demands bigger size of the L–C filter to obtain
sinusoidal voltage at the output.
For special applications like high-speed motor drive, where
the fundamental base frequency of the voltage source can be
as high as 1 kHz, PWM control of the inverter is a difficult
proposition. This is again due to the limitation of the switching
devices like insulated-gate bipolar transistors (IGBTs).
Manuscript received July 6, 2008; revised October 16, 2008. Current version
published April 17, 2009. Recommended for publication by Associate Editor
S. Bhattacharya.
The authors are with the Department of Electrical Engineering, Indian In-
stitute of Technology, Kharagpur 721 302, India (e-mail: gpoddar@ee.iitkgp.
ernet.in; malaya@ee.iitkgp.ernet.in).
Digital Object Identifier 10.1109/TPEL.2009.2013860
0885-8993/$25.00 © 2009 IEEE
Fig. 1. Basic converter topology.
These problems are tackled by various multilevel topolo-
gies [1], [13]. Papers [3]–[7] deal with the standard series-
connected inverter cells to handle higher voltages. Most of
them require separate dc voltage source for each inverter cell.
Paper [4] proposes a method to draw active power at fundamen-
tal frequency by each cell to regulate its dc bus voltage. In [2],
a high-frequency PWM inverter is connected in series with a
low-frequency square-wave inverter. Both the inverters require
separate dc sources.
In this paper, a variant of series-connected converters and its
control strategy are proposed for sinusoidal output. The basic
three-phase high-voltage inverter works in square-wave mode
as in [2]. But the series-connected inverters produce only the
harmonic voltages using carrier-based PWM strategies, unlike
all other papers mentioned before. The net output voltage has
only the fundamental component with relatively small switching
harmonics.
II. FUNDAMENTALS OF THE PROPOSED INVERTER
TOPOLOGY AND CONTROL
The proposed topology (Fig. 1) has evolved from the typical
series compensating devices like the unified power quality con-
ditioner (UPQC), digital video recorder (DVR), etc. The main
square-wave inverter is solely responsible for the fundamental
voltage. Each phase has series-connected (Fig. 1) single-phase
PWM inverter that produces only the required harmonic volt-
ages. These three single-phase cells normally have common dc
bus voltage. Usually, the value of this common dc bus voltage is
less than that of the main square-wave inverter. This justifies the
PODDAR AND SAHU: NATURAL HARMONIC ELIMINATION OF SQUARE-WAVE INVERTER FOR MEDIUM-VOLTAGE APPLICATION 1183

Fig. 2. Single-phase equivalent circuit of the proposed converter and the load. Fig. 3. Single-phase equivalent circuit of the harmonic voltages only.

PWM mode of operation of the series inverter [2]. This common Now, the peak value of the series compensator output voltage
dc bus voltage has to be generated separately. Alternatively, a is Vdc /2. This can be seen by subtracting (3) from (1). Thus, the
small amount of controlled active power has to be drawn by the minimum dc bus voltage required for the series compensator is
series inverters to control this dc bus voltage [4]. The desired Vdc /2.
harmonic voltages are injected to the line using three single- In the proposed topology, there is no separate source to main-
phase transformers, as shown in Fig. 1. Small capacitor and tain this desired value of the series compensator dc bus voltage.
resistor networks at the output of the single-phase transformers Let us assume that the modulation depth (m) of the nth harmonic
remove the switching harmonics. component of the series compensator is as follows:
In this paper, natural open-loop control of this series com- 4
pensator dc bus voltage is proposed without drawing any active . m= (4)
nπ
power at fundamental frequency. A separate active dc voltage
Therefore, the output nth harmonic component of the series
source is also not required here. The active power drawn at
compensator is as follows:
harmonic frequencies regulates the dc bus voltage of the series
compensator. The basic philosophy of the operation is estab- 4Vdch (t)
Vn h (t) = mVdch (t) sin(nωf t) = sin(nωf t). (5)
lished shortly. nπ
A per-phase equivalent circuit of this proposed system is Here, Vdch (t) is the dc bus voltage of the series compensator at
shown in Fig. 2. The load could be a motor with equivalent any time t. The nth harmonic equivalent circuit of this converter
leakage impedance RL , LL , and the sinusoidal back emf EL at with load is shown in Fig. 3. Assuming that the dynamics of
fundamental frequency. It may also represent the grid voltage Vdch (t) is very slow, the average active power Pn h absorbed by
EL at fundamental frequency and the series impedance RL and the series compensator due to the nth harmonic voltage is as
LL . The square-wave voltage varies from +Vdc /2 to −Vdc /2, follows:
with the time period of 2π/ωf . Mathematically, it can be ex- 2
pressed using the unit step function u(t) as follows: 1 4 ((Vdc /2) − Vdch (t))
Pn h = Vdch (t) RL . (6)

      2 nπ RL2 + (nωf LL )2
VS (t) = Vdc u t − 2n ωπf − u t − (2n + 1) ωπf Neglecting the losses of the dc bus capacitor, the dynamical
Vdc equation of Vdch (t) can now be written as follows:
− , n = 0, ±1, ±2, ±3 . . . (1) ∞
2
dVdch (t)
3 Pn h = Vdch (t) Ch . (7)
n =5
dt
Here, Vdc is the dc bus voltage of the square-wave inverter
and ωf is the fundamental frequency (in radians per second) Here, Ch is the total dc bus capacitor of the series compensator
of the square wave. Using Fourier analysis, the desired series and 3 ∞ n =5 Pn h is the net active power considering all three
compensator output voltage can now be obtained as phases. It has to be noted that all the triplen harmonics like
third, nineth, etc., will not contribute any power since there is

∞ 
4 (Vdc /2) no neutral connection (Fig. 1). Using (6) and (7), the dynamics
Vh (t) = sin (nωf t) , where “n” is odd number.
nπ of Vdch (t) becomes
n =3
(2) dVdch (t) Vdc
After perfect compensation using series converter, the load = − Vdch (t)
dt 2
voltage becomes 

∞ 2
3RL 4 1
4 (Vdc /2) × . (8)
Vload (t) = sin (ωf t) . (3) 2Ch nπ RL2 + (nωf LL )2
π n =5
1184
Fig. 4. Basic gate pulse generation scheme for the topology presented in Fig. 1.
Fig. 5. Transformerless operation of the converter.
Now, (8), (2), and (5) suggest that in steady state, Vdch =
Vdc /2 and the load voltage Vload becomes sinusoidal [(3)]. The
fundamental load current does not affect this dc bus voltage
balance as there is no fundamental component of voltage at
the output of the series compensator. The block diagram of the
basic switching control strategy for this topology is presented
in Fig. 4.
III. DIFFERENT VARIATIONS OF THE TOPOLOGY
AND THEIR CONTROL
Single-phase transformers of the series compensator are
bulky. They introduce losses and also increase the cost of the
system. So, the transformerless counterpart of this topology is
as shown in Fig. 5. Each phase series compensator has indepen-
dent dc bus. However, the size of the dc bus capacitor is needed
to be high. Equation (7) still holds good for power balance with
the exception that the power absorbed by each compensator is
∞
n =5 Pn h . Therefore, the dynamical equation of the dc bus of
each compensator is
dVdch (t) Vdc
= − Vdch (t)
dt 2
∞
 current IS sin (ωf t). In case of a MOSFET-based compensator,

RL 4
2
1 the drain resistances (Rd ) can be represented as shown in Fig. 8.
× . (9)
n =5
2Ch nπ RL2 + (nωf LL )2
Hence, in steady state, all three independent dc buses become
Vdc /2. The load voltage Vload also becomes sinusoidal with
small switching harmonics of the series compensator.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009
For the medium-voltage application, the upper limit of Vdc
could be 2.2 kV for the PWM switching of the series compen-
sator with dc bus voltage Vdc /2, i.e., 1.1 kV [2]. At this limit, the
rating of the IGBT for the series compensator may be at least
1700 V. Therefore, the proposed topology presented in Fig. 5
is modified in Fig. 6 to handle the higher level of voltages. In
this topology, several single-phase full-bridge inverter cells are
connected in series similar to multicell topologies [3]. Each cell
handles only one harmonic component and is named as nth har-
monic cell (Fig. 6). Modulation depth “m” is taken as 1 for all
the cells. Equation (5) is now modified for the nth harmonic
voltage at the output of the nth cell is as
Vn h (t) = mVdch (t) sin(nωf t) = Vdch (t) sin(nωf t). (10)
The average power of the nth harmonic cell is then
1 ((4/nπ)(Vdc /2) − Vdch (t))
Pn h = Vdch (t) RL . (11)
2 RL2 + (nωf LL )2
Using power balance as before, the dynamics of the nth cell
dc bus becomes

dVdch (t) 2Vdc RL 1
= − Vdch (t) .
dt nπ 2Ch RL2 + (nωf LL )2
(12)
Hence, in steady state, the dc bus voltage of the nth harmonic
cell becomes 2Vdc /nπ. Therefore, each cell dc bus voltage will
differ from the other cell. The highest dc bus voltage is required
for the lowest harmonic, i.e., fifth harmonic here. The higher
harmonics will require lower dc bus voltages. This enables hav-
ing higher switching frequency for higher harmonics. The block
diagram of the basic switching control strategy for this topology
is presented in Fig. 7. Assuming that the dc bus voltage of the
fifth harmonic cell is limited to 1.1 kV for PWM operation, the
other cell voltages and the main square-wave converter voltages
are summed up in Table I.
IV. PRACTICAL ISSUES OF LOSSES IN THE SERIES
COMPENSATORS
The analysis presented in the earlier sections is assumed to
have zero losses in the series compensator. However, the practi-
cal converters have the switching and the conduction losses. An
approximate equivalent circuit of each harmonic cell is shown
in Fig. 8. In steady state, the series compensator current is
mostly dominated by the fundamental component of current.
This is represented by a current source IS sin (ωf t) in Fig. 8.
In this equivalent circuit, the VCE(sat) (or VF ) drop of the IGBT
switches (or the antiparallel diodes) can be approximately rep-
resented by a square-wave voltage signal whose fundamental
frequency is same as that of the series compensator current. This
square-wave voltage is also in phase with the series compensator
Now, the actual switches shown in Fig. 8 have only the nonideal
switchings but no conduction drops. For ideal switching, the
voltage at port a–b (Vab ) in Fig. 8 is mainly mVdch sin (nωf t)
and the switching harmonics. Therefore, there is no net active
power transfer across the port a–b. Hence, the current source,
PODDAR AND SAHU: NATURAL HARMONIC ELIMINATION OF SQUARE-WAVE INVERTER FOR MEDIUM-VOLTAGE APPLICATION
Fig. 6. Topology for medium-voltage application.
Fig. 7. Basic gate pulse generation scheme for the topology presented in Fig. 6.
i.e., the main square-wave inverter delivers the complete con-
duction losses of each harmonic cell.
Due to nonideal switchings, Vab has the additional harmonic
components of “nωf ” and a small amount of voltage having fre-
quency ωf due to the current source. This small voltage also is
in phase with this current source IS sin (ωf t). Therefore, there
is a small amount of net active power transfer from the current
source, i.e., the main square-wave inverter to the compensator
across this port a–b. This small active power shares the switching
losses of the compensator. Depending upon the device switch-
ing characteristics, the compensator dc bus Vdch also shares the
switching losses. Moreover, half of the total switching per fun-
damental cycle (1/ωf ) is soft switching (ZVS). Therefore, the
net power loss (Psw ) at the compensator dc bus (Vdch ) consists
of small amount of device switching power loss only. Thus, a
small amount of active power is required to be drawn by this
compensator to maintain its dc bus voltage Vdch in steady state.
For the simplification, this switching power loss (Psw ) can be
assumed to be proportional to Vdch . In steady state, Psw should
be equal to the active power due to nth harmonic for nth har-
1185
monic cell (Pn h ). Using (11), the steady-state dc bus voltage
Vdch of the nth harmonic cell can be written as
1 ((4/nπ) (Vdc /2) − Vdch )
Ksw Vdch = Vdch RL ,
2 RL2 + (nωf LL )2
or,
 
2Vdc 2Ksw RL2 + (nωf LL )2
Vdch = − . (13)
nπ RL
where Ksw is the proportionality constant.
For standard designed converter, Psw is very small, and hence,
Ksw is also negligibly small. Then, Vdch is slightly less than the
desired voltage 2Vdc /nπ. Therefore, this compensator loss in-
troduces a small amount of uncompensated nth harmonic volt-
age (2) at the load terminals. For a standard designed converter,
this small loss does not lower the performance of the series
compensator appreciably, as evident from the experimental re-
sults presented later. From (13), it can be seen that the per-
formance of the compensator deteriorates for the higher order
harmonics. Since the higher order harmonics have the lower or-
der magnitudes (2), this may not be a serious limitation of this
configuration.
V. SIMULATION RESULTS
The proposed strategies are simulated to validate the per-
formances. The converter configuration presented in Fig. 1 is
simulated on SIMULINK platform. The fixed dc bus voltage of
the square-wave inverter is 600 V. It operates in 180◦ conduc-
tion mode. The PWM switching frequency of the compensator
is 5 kHz. A small ac capacitor is connected at the output of the
single-phase transformer of the compensator (Fig. 1) to remove
the switching ripple from the load voltage. This converter is
connected to a three-phase load. This load consists of a voltage
source of 415 V L–L and has series impedance of 0.5 Ω resis-
tance and 180 µH inductance. This converter output voltage is
required to be sinusoidal.
Fig. 9 shows the different waveforms of the configuration pre-
sented above. Fig. 9(a) shows the first-order rise of the common
1186 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009

TABLE I
DIFFERENT CELL VOLTAGES OF THE PROPOSED CONVERTER FOR A TYPICAL 6.6 KV APPLICATIONS

Fig. 8. Equivalent circuit of each harmonic cell for loss estimation.

Fig. 10. Natural building of dc bus voltages for different harmonic cells. The
dc bus voltage of the square-wave inverter is 4400 V.

Fig. 9. (a) Dynamics of the compensator dc bus voltage. (b) Square-wave

inverter output line-to-line voltage. (c) Load voltage near zero compensator
output. (d) Load voltage at steady state. (e) Compensator reference voltage.
(f) Actual output of the compensator after ac filter capacitor in steady state.

dc bus voltage of the compensator. The steady-state value of this

voltage is nearly 300 V. These conform to (8). Fig. 9(b) shows
the quasi-square line voltage waveform of the square-wave in-
verter. Fig. 9(c) and (d) shows the load voltage waveforms at the
beginning of the compensation and at the steady state, respec-
tively. Fig. 9(e) shows the voltage reference signal of the series
compensator. This is obtained by subtracting the fundamental
component of phase voltage of the square-wave inverter from its
actual square-wave profile. Here, the phase voltage is measured
between the line and the middle of the dc bus. The third har-
monic component is also subtracted from the earlier reference
signal. The third harmonic component of the phase voltage does
not appear in the line voltage. Finally, Fig. 9(f) shows the actual
output of the compensator.
The configuration shown in Fig. 6 is also simulated for four
cells connected in series with the square-wave inverter. Unlike
the previous case, the modulating signals for all the cells are
Fig. 11. Load voltage and current at start and at steady state.
sinusoidal and the modulation depths are 1. The frequency of
the nth harmonic cell is the nth harmonic of the fundamental
frequency of the square-wave inverter, as shown in Fig. 6. The
fixed dc bus voltage of the square-wave inverter is 4400 V. The
load has emf source of line-to-line rms voltage 3300 V and has
series impedance of 0.2 Ω resistance and 360 µH inductance.
Fig. 10 shows the dynamics of the dc bus voltage of different
harmonic cells. The dc bus voltage of each cell develops with
first-order dynamics. The steady-state values of all the cells con-
form to (12). Fig. 11 shows the quasi-square-wave load voltage
and the nonsinusoidal load current at start when the compensator
voltages are almost zero. It also shows the PWM load voltage
PODDAR AND SAHU: NATURAL HARMONIC ELIMINATION OF SQUARE-WAVE INVERTER FOR MEDIUM-VOLTAGE APPLICATION 1187

Fig. 14. Naturally compensated line voltage around 350 Hz.

Fig. 12. Experimental setup for the topology presented in Fig. 1.

Fig. 15. Natural building of dc bus voltage of the series compensator.

Fig. 13. Quasi-square-wave line voltage and compensated line voltage around
900 Hz.

and nearly sinusoidal load current when the compensator volt-

ages reach their corresponding steady-state values.

VI. EXPERIMENTAL RESULTS

In this paper, the proposed concept of compensation has been
applied to high-frequency three-phase ac drives application. The
fundamental base frequency varies from 250 Hz to 1 kHz. The
motor requires V /f control with sinusoidal terminal voltage.
The rated rms line-to-line voltage of the motor is 300 V at 1 kHz.
The power rating of the protomodel is 5 kV·A. The basic topol-
ogy shown in Fig. 1 is adopted for this application. The main
square-wave inverter is based on IGBT switches. This inverter
has a variable input Vdc . Thus, the output fundamental ac volt-
age is varied with frequency. The series compensator, handling
only the harmonic voltage, is MOSFET-based and operating
at 100 kHz. The complete controller including the pulsewidth
modulator is implemented on a field-programmable gate array Fig. 16. (a) R-phase compensator output at 1000 Hz. (b) Y-phase compensator
output at 1000 Hz. (c) B-phase compensator output at 1000 Hz. (d) Correspond-
(FPGA)-based platform. The experimental setup is shown in ing sinusoidal output voltage of the converter.
Fig. 12.
1188
The experimental results are shown in Figs. 13–16. The main
inverter is working in 180◦ conduction mode. Channel 2 of
Fig. 13 shows the quasi-square-wave line voltage of this main
inverter around 900 Hz fundamental frequency. Corresponding
compensated line voltage is shown in Fig. 13 (channel 1). At
low-frequency (around 350 Hz), compensated line voltage is
shown in Fig. 14. The peak value of the line voltage is around
100 V. Then, the dc bus voltage Vdc of the square-wave inverter
is around 128 V. From (8), the dc bus voltage of the series
compensator is expected to be 64 V in steady state. Fig. 15
shows the dc bus voltage dynamics of the series compensator.
In steady state, this voltage is around 60 V and has first-order
dynamics. These conform to (8). Fig. 16 shows the compensator
output voltages for the three phases and the net sinusoidal output
voltage at 1000 Hz.
VII. CONCLUSION
In this paper, an open-loop natural control of voltage source
inverter has been proposed mainly for high-power applications.
The main square-wave inverter is built with high-voltage low-
switching-frequency semiconductor devices like integrated gate
commutated thyristors (IGCTs). The series compensators are
IGBT-based inverters and operate from relatively low dc bus
voltages at high switching frequencies. The series compensators
produce only the desired harmonic voltages to make the net out-
put voltage sinusoidal. For medium-voltage application, several
compensating PWM inverters are connected in series. Each cell
compensates one particular harmonic only. As the order of har-
monics increases, the required dc bus voltage level drops. This
enables to exploit higher switching frequency for higher order
harmonic cell. It has been established both theoretically and ex-
perimentally that the dc bus of the compensators do not require
any external dc source or closed-loop controller for this pro-
posed strategy. The active power at harmonic frequencies keeps
the compensator dc bus voltage charged. For variable-speed-
drives applications, the magnitude of the fundamental output
voltage should be controlled by regulating the dc bus voltage of
the square-wave inverter. For static synchronous compensator
(STATCOM) applications, the limited variation of this dc bus
voltage may also be required. This can be achieved by drawing
small active power at fundamental frequency from the grid.
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Gautam Poddar received the B.E. degree from
Bengal Engineering College, Calcutta University,
Kolkata, India, in 1992, the M.Tech. degree from the
Indian Institute of Technology, Kharagpur, India, in
1994, and the Ph.D. degree from the Indian Institute
of Science, Bengaluru, India, in 2002, all in electrical
engineering.
From 1995 to 2004, he was with the
Power Electronics Group, Centre for Development
of Advanced Computing (formerly ER&DCI),
Thiruvananthapuram, India, where he was working
in the field of power electronics and drives. In 2004, he joined the Department
of Electrical Engineering, Indian Institute of Technology, Kharagpur. His cur-
rent research interests include control of high-power drives, sensorless control
of ac motor, and active power filters.
Dr. Poddar was a recipient of the Indian National Academy of Engineers
(INAE) Young Engineers Award in 2003.
Malaya Kumar Sahu was born in Orissa, India,
in 1978. He received the B.E. degree in electri-
cal engineering from Orissa Engineering College,
Bhubaneswar, India, in 2001, and the M.Tech. de-
gree in power system engineering from the Univer-
sity College of Engineering, Burla, India, in 2004. He
is currently working toward the Ph.D. degree at the
Indian Institute of Technology, Kharagpur, India.
His current research interests include FACTs de-
vices and medium voltage converters.