Lecture 6: Combinational logic

Hyeon-Min Bae

Department of Electrical Engineering

KAIST, Daejeon, Korea

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Combinational vs. Sequential Logic

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

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Static CMOS Circuit

At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path. à low impedance output

Ex) High impedance output: charge stored in a capacitor

à Sensitive to noise
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
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Static Complementary CMOS

VDD

In1
PMOS only
In2 PUN

…
InN
F(In1,In2,…InN)
In1
In2 PDN
…

NMOS only
InN

PUN and PDN are dual logic networks

(PUN: Pull up network
PDN: Pull down network)
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NMOS Transistors in Series/Parallel Connection

Transistors can be thought as a switch controlled by its

gate signal
NMOS switch closes when switch control input is high

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PMOS Transistors in Series/Parallel Connection

PMOS switch closes when switch control input is low

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Threshold Drops

VDD
PUN VDD ® |VTp|
S VGS
S CL

D 0 ® VDD D

CL
Good for pull up
VDD
PDN VDD ® 0
D
D CL VDD
VDD
S 0 ® VDD - VTn
S VGS
CL
Good for pull down
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Example

2.5V

A B C
D E F
G H I

1) Initial voltage: 0V
2) Initial voltage: 2.5V

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Complementary CMOS Logic Style

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Example Gate: NAND

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Example Gate: NOR

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Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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Constructing a Complex Gate

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Properties of Complementary CMOS Gates Snapshot

1. High noise margins

:
VOH and VOL are at VDD and GND, respectively.
2. No static power consumption
:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode .
3. Comparable rise and fall times:
(under appropriate sizing conditions)

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CMOS Properties

• Full rail-to-rail swing; high noise margins

• Logic levels not dependent upon the relative
device sizes; ratioless
• Always a path to Vdd or Gnd in steady state;
low output impedance
• Extremely high input resistance; nearly zero
steady-state input current
• No direct path steady state between power
and ground; no static power dissipation
(except leakage)
• Propagation delay function of load
capacitance and resistance of transistors
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Switch Delay Model

A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

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Input Pattern Effects on Delay

• Delay is dependent on
Rp Rp the pattern of inputs
A B • Low to high transition
– both inputs go low
Rn CL • delay is 0.69 Rp/2 CL
B – one input goes low
• delay is 0.69 Rp CL
Rn
Cint
• High to low transition
A
– both inputs go high
• delay is 0.69 2Rn CL

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Input Pattern Effects on Delay

A=B=1®0
Rp Rp
A B A=1 ®0, B=1
Voltage [V]
Rn CL A=1, B=1®0
B

Rn
Cint
A

time [ps]

Charge both CL and Cint

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Delay Dependence on Input Patterns

Input Data Delay

Rp Rp Pattern (psec)
A B A=B=0®1 69

Rn
A=1, B=0®1 50 Discharged Cint
CL
A= 0®1, B=1 62
B
A=B=1®0 35
Rn
Cint A=1, B=1®0 57
A
A= 1®0, B=1 76

NMOS = 0.5µm/0.25µm
PMOS = 0.75µm/0.25µm
CL = 100 fF
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Transistor Sizing

•
Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

If the mobility ratio of N and P devices is 2:1

(Based on worst case delay)

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Transistor Sizing a Complex CMOS Gate

B 8
A 4
C 8

D 4
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

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Fan-In Considerations

A B C D

A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.

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tp as a Function of Fan-In

quadratic

Gates with a
fan-in greater
tp (psec)

tpHL tp than 4 should

be avoided.
tpLH
linear

fan-in

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tp as a Function of Fan-Out

All gates have

tpNOR2 tpNAND2 the same
drive current.
tpINV
tp (psec)

Slope is a
function of
“driving
strength”
eff. fan-out

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Review: tp as a Function of Fan-In and Fan-Out

• Fan-in: quadratic due to increasing resistance and

capacitance
• Fan-out: each additional fan-out gate adds two
gate capacitances to CL

• tp = a1FI + a2FI2 + a3FO

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Review: Design Technique 1

• Transistor sizing
– as long as fan-out capacitance dominates
• Progressive sizing

Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks

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Review: Design Technique 2

• Transistor ordering

critical path critical path

charged 0®1
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
0®1

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

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Review: Design Technique 3

• Alternative logic structures

F = ABCDEFGH

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Review: Design Technique 4

• Isolating fan-in from fan-out using buffer insertion

CL CL

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Review: Design Technique 5

• Reducing the voltage swing

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )

– linear reduction in delay
– also reduces power consumption
• But the following gate is much slower!
• Or requires use of “sense amplifiers” on the
receiving end to restore the signal level (memory
design)

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