Lecture10 Sequential

Lecture 10: Sequential logic
Hyeon-Min Bae
Department of Electrical Engineering

KAIST, Daejeon, Korea
Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 1

Sequential Logic
2 storage mechanisms
• positive feedback, static
• Charge storage, dynamic

Naming Conventions
• In our text:
– a latch is level sensitive
– a register is edge-triggered
• There are many different naming conventions
– For instance, many books call edge-triggered elements
flip-flops
– This leads to confusion however

Latches
Transparent in one clock state, hold the final value when closed

Mux-Based Latches
Negative latch Positive latch

(transparent when CLK= 0) (transparent when CLK= 1)
Q 0 Q
1
D 0 D 1
CLK CLK

Implementation of MUX
• Transmission gate
NFET for the transmission of “L”

PFET for the transmission of “H”

Latches and registers
• Static: use bi-stable elements (Flip flops)

– Mux based
• Dynamic latches and registers
• Typically dynamic latches and registers have
keepers and become pseudo static

Critical element: Flip-flop
V o1 Vi2
V i1 V o2
A
V i2 =V o1
Bi-Stability : two
C
stable states (0 and 1)
B
V i1 =V o2

Meta-Stability
Gain should be larger than 1 in the transition region

Storage Mechanisms
Static Dynamic (charge-based)
CLK
D Q
CLK

Writing into a Static Latch
Use the clock as a decoupling signal,

that distinguishes between the transparent and opaque states
CLK
D D
CLK
Forcing the state

Converting into a MUX (can implement as NMOS-only)
Ratioless Ratioed
Increased clock load (important)
Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only Non-overlapping clocks

Non overlapping clock
Both 𝜙1 and 𝜙2 are not High at the same time

Latch versus Register
q Latch q Register
stores data when stores data when
clock is low clock rises
D Q D Q
Clk Clk
Clk Clk
D D

Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge

Also called master-slave latch pair
Input signal seen at the rising (fall) edge is memorized

Master-Slave Register
Multiplexer-based latch pair

Reduced Clock Load Master-Slave Register
Initial Q=0, D=1 à I2 and I4 should be scaled for proper

operation
Characterizing Timing
Register Latch

Clk-Q Delay

Timing Definitions for register
CLK
t Register
tsu thold D Q
D DATA
STABLE CLK
t
tc 2 q
Q DATA
STABLE t
Important terms: Race, set-up time , hold time, clk to Q, data to q

tSetup: Signal hasn’t arrived at the input of slave latch (problem in
slow corner) à td2q dominates
Thold : clock path is slow or signal path is too fast (Problem in the
fast corner in general)

Setup, Hold time, clk2q
Setup time violation

Setup, Hold time, clk2q
Hold time violation

• Setup time: Time required for the spacecraft to
pass the gate
• Hold time: Gate closing time
• Clk2q: time required for the spacecraft to exit the
2nd gate

Maximum Clock Frequency
Also:
tcdreg + tcdlogic > thold
tcd: contamination delay =
minimum delay
tclk-Q + tp,comb + tsetup = T

Example
• Channel impulse response: Y(n)=X(n)+aX(n-1)

!
à " = 1 + 𝑎𝑍 #$
• At the receiving side, we need a proper equalizer
!
à 𝑇 = !"#$!"
• One clock cycle delay can be implemented using

a register.
• Max clock freq: fmax=(Tclk2q+Tmult+ Tadd+Tsetup)-1

Example
• Apple loop unrolling (precomputation)

$
• 𝑇 = $%&' !" à Y(n)=X(n)-aY(n-1), Y(n-1)= -1 or 1
• Y(n)=X(n)-a or Y(n)=X(n)+a
• Select one of the two values depending on Y(n-1)

• Max clock freq: fmax=(Tclk2q+Tmux+Tsetup)-1

Pipelining
Purpose:
• Increase circuit speed
• Reduce power
REG
REG
a a
REG
REG
REG
REG
log Out CLK log Out
CLK
REG
REG
b CLK b CLK CLK CLK
CLK CLK
Reference Pipelined
Tclk ³ tclk -Q + t p1 + t p 2 + t p 3 + t su Tclk ³ tclk -Q + max(t p1 , t p 2 , t p 3 ) + t su

Pipelining
Latency: The output is available after N clock cycles

What if we don’t increase the clock frequency after the
pipelining?

More Precise Setup Time

Flip-flop latching time
wT t
From DV » DVinit e
1 ∆𝑉
𝑡= 𝑙𝑛
𝜔 % ∆𝑉&'&(
à Decreased initial voltage increases latching time

Setup/Hold Time Illustrations
Circuit before clock arrival (Setup-1 case)





Hold-1 case

Hold-1 case

Hold-1 case

Hold-1 case

Hold-1 case

Edge triggered register
CLK X CLK
Q
A
D
B
CLK CLK
t su = t p ,n
t su = t p ,n + t p ,inv
tclk -Q = 2t p ,inv + t p ,n OR tclk -Q = t p ,inv + t p ,n
th = 0
SUM: t su + tclk -Q = 2t p,n + 2tp,inv

Avoiding Clock Overlap
CLK X CLK
Q
A
D
B
CLK CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
Race condition: data vs clock Nonoverlapping clk

Other Latches/Registers: C2MOS
Clocked CMOS
à C2MOS
“Keepers” can be added to make circuit pseudo-static

No overlap time in sampling and hold phase
Insensitive to Clock-Overlap
VDD VDD
M2 M6
CLK
clk CLK
0 M4 0 M8
X
D Q
CLK
CLK clk
M1 M5
(a) (0-0) overlap
X should go zero to affect the output during M8 is on

Insensitive to Clock-Overlap
VDD VDD
M2 M6
clk CLK CLK

X
D CLK Q
1 M3 1 M7 CLK
clk
M1 M5
(b) (1-1) overlap

Insensitive to clk overlap

Latch-Based Design
• N latch is transparent • P latch is transparent

when φ = 0 when φ = 1
φ
N P
Logic
Latch Latch
Logic
Race condition!
But smaller hardware, we will revisit

Latch-Based Pipeline

NORA
Even number of static logic gates between C2MOS

np-CMOS
Clk Mp Clk Me
1®1
Out1
1®0
In1 In4 PUN
In2 PDN In5
0®0
In3 0®1
Out2
(to PDN)
Clk Me Clk Mp
Only 0 ® 1 transitions allowed at inputs of PDN

Only 1 ® 0 transitions allowed at inputs of PUN

NORA Logic
Clk Mp Clk Me
1®1
Out1
1®0
In1 In4 PUN
In2 PDN In5
0®0
In3 0®1
Out2
(to PDN)
Clk Me Clk Mp
to other to other
PDN’s PUN’s
WARNING: Very sensitive to noise!

NORA CMOS
• Clk overlap between

dynamic and
C2MOS would not
cause race
condition.
• CLK and CLK’
modules are
alternating for latch
based pipeline
• Only for high
performance
applications due to
complexity

Other Latches/Registers: TSPC (true single phase clock)
Positive latch Negative latch

(transparent when CLK= 1) (transparent when CLK= 0)

Including Logic in TSPC
Example: logic inside the latch

AND latch

TSPC Register
Tsetup : 1 inverter
Thold : less than 1 inverter (discharge through M4 and M5 - delay of M1)
Tc2q : 3 inverter

TSPC Register
Race condition: M7-8 should be slower than M4-5

Ex) CLK:L, Y:H, Q:L, X:H à glitch problem

Sense amp based register
Common in Memory design: Amplifier + register

Shorting transistor
State should not change once the output is latched

Pulse-Triggered Latches
An Alternative Approach
Ways to design an edge-triggered sequential cell:
Master-Slave Pulse-Triggered
Latches Latch
L1 L2 L
Data Data
D Q D Q D Q
Clk Clk Clk Clk

Clk

Pulsed Latches
VDD VDD
M3 M6 VDD
CLK
Q
D CLKG CLKG MP CLKG
M2 M5
X
MN
M1 M4
(a) register (b) glitch generation
CLK
CLKG
(c) glitch clock

Pulsed Latches
Hybrid Latch – Flip-flop (HLFF), AMD K-6 and K-7 :
CLK P1 P3
x Q
M6
M3
D P2 M5
M2
M4
M1 CLKD

Non-Bistable Sequential Circuits─
Schmitt Trigger
Vou t V OH
In Out
•VTC with hysteresis V OL
•Restores signal slopes

VMœ VM+ Vi n

Noise Suppression using Schmitt Trigger

CMOS Schmitt Trigger
VDD
M2 M4
Vin X Vout
M1 M3
Moves switching threshold

of the first inverter

Schmitt Trigger Simulated VTC
2.5 2.5
2.0 2.0
1.5 VM1 1.5
1.0 VM2 x 1.0

X k=1
k=3
k=2
0.5 0.5
k=4
0.0 0.0
0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5
Vin (V) Vin (V)
Voltage-transfer characteristics with hysteresis. The effect of varying the ratio of the
PMOS device M4. The width is k* 0.5m m.

CMOS Schmitt Trigger (2)
VDD
M4
M6
M3
In Out
M2
X M5
VDD
M1

Schmitt Trigger
Lower threshold
1 1
K1VDSAT (Vin - Vth 0 - VDSAT ) = K 5VDSAT (VDD - Vx - Vth - V DSAT)
2 2
Vth = Vth 0 + g ( 2fF + Vx - 2fF )
Vin = Vx + Vth

Lecture10 Sequential

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Lecture10 Sequential

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Lecture 10: Sequential logic

Department of Electrical Engineering

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 1

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 2

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Negative latch Positive latch

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NFET for the transmission of “L”

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• Static: use bi-stable elements (Flip flops)

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Gain should be larger than 1 in the transition region

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Static Dynamic (charge-based)

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Use the clock as a decoupling signal,

Forcing the state

NMOS only Non-overlapping clocks

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Both 𝜙1 and 𝜙2 are not High at the same time

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Two opposite latches trigger on edge

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Multiplexer-based latch pair

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Initial Q=0, D=1 à I2 and I4 should be scaled for proper

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Important terms: Race, set-up time , hold time, clk to Q, data to q

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Setup time violation

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Hold time violation

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• Channel impulse response: Y(n)=X(n)+aX(n-1)

• One clock cycle delay can be implemented using

• Max clock freq: fmax=(Tclk2q+Tmult+ Tadd+Tsetup)-1

Copyright 2022, Nanoscale advanced integrated systems lab, KAIST 25

• Apple loop unrolling (precomputation)

• Select one of the two values depending on Y(n-1)

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b CLK b CLK CLK CLK

Tclk ³ tclk -Q + t p1 + t p 2 + t p 3 + t su Tclk ³ tclk -Q + max(t p1 , t p 2 , t p 3 ) + t su

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Latency: The output is available after N clock cycles

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à Decreased initial voltage increases latching time

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Circuit before clock arrival (Setup-1 case)

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Circuit before clock arrival (Setup-1 case)

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Circuit before clock arrival (Setup-1 case)

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Circuit before clock arrival (Setup-1 case)

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Circuit before clock arrival (Setup-1 case)