ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION II: 2023/2024

DEC50143 - CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 4: Layout Design and Simulation of XOR and XNOR Logic Gate.
PRACTICAL WORK
-
DATE:
LECTURER’S NAME: ENCIK WAN ZAIMI BIN WAN YUSOF
GROUP NO.: -
TOTAL
STUDENT ID & NAME: MARKS
(100%)

(1) MUHAMMAD ADAM BIN ABDULLAH (13DTK21F1126)

DATE SUBMIT:- DATE RETURN:-

6 RESULT

Part A: Designing the layout of 2-input XOR gate

Part B: Simulating the layout of 2-input XOR gate.

OPTIMIZED LAYOUT AREA = 190 λ x 180 λ

=34200 λ^2

7 DISCUSSION

1. Produce a truth table for a 2-input XNOR gate.

 (3 marks)
2. From the truth table of 2-input XNOR gate in (1), derive the Boolean equation for XNOR.
F=AB OR F=AB
THEN F=AB+AB
(3 marks)
3. Produce a truth table for a 3-input XOR gate.

(2 marks)

8 CONCLUSION

Write TWO (2) conclusions for the practical work that you have done.
In conclusion, the layout design and simulation of XOR and XNOR logic gates have been
successfully executed, providing a comprehensive understanding of their functionality and
performance characteristics. Through the meticulous process of designing the physical layout and
simulating the gate operations, valuable insights have been gained into the intricacies of digital
circuitry.
(4 marks)
 PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 4
Student Name : Class :
Date :
Student ID# :

SCORE DESCRIPTION
ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Use correct technology feature Use correct technology feature
A. Technology feature Use other technology feature. x1
for ALL parts of the layout. for parts of the layout.
Follow lambda design rule for
Follow lambda design rule for Follow lambda design rule for
B. Design rule minimum width and spacing for x1
MANY of the polygons. ONLY a few of the polygons.
ALL polygons.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and
C. Transistor size x2
transistor size. transistor size. NMOS transistor size.
Use correct number of metal Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x2
display display for ALL layouts. display for some of the layouts. error’ display at ALL.
Layout Design Produce acceptable floorplan
Produce good floorplan and Produce appropriate floorplan
F. – input / output / and input / output layout x2
input / output layout design. and input / output layout design.
floorplan design.
Not able to produce any
Able to produce the simulation Able to produce the simulation
G Layout simulation simulation for ALL of the x2
of ALL layouts correctly. for some of the layouts correctly.
layouts.
Layout size (end Produce small layout size (end Produce acceptable layout size Produce large layout size (end
H. x2
product) product). (end product). product).
TOTAL / 70

…………….…………………….
Supervisor Name & Signature
 SUSTAINABILITY AND ENVIRONMENT FRIENDLY SKILL RUBRIC - CLO3

SCORE DESCRIPTION
ITEM ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Layout Performance & Total using technology feature having Using technology feature having Not using transistor technology
Low Power Design green elements to achieve both green elements either to achieve feature having green elements to
A. technology feature layout performance efficiency and layout performance efficiency or achieve layout performance x 10 / 50
low power consumption is evident in low power consumption in the efficiency and low power
the final layout. final layout. consumption in the final layout.

B. Final IC Layout Size Total usage of environment friendly,
green materials / elements or reduce,
recycled and reused concept to
produce small IC layout size is clearly
evident.
Using environment friendly, green
materials / elements or reduce,
recycled and reused concept that
help to produce acceptable IC
layout size is partly evident.
No usage of environment friendly,
green materials / elements or
reduce, recycled and reused concept x 10 / 50
thus producing large IC layout size.

Total Generic Skill: / 100

…………….…………………….
Supervisor Name & Signature