ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: ____________

DEC50143 – CMOS IC DESIGN AND FABRICATION
Layout Design and Simulation of CMOS Inverter (NOT Logic
PRACTICAL WORK 2 :
Gate)
PRACTICAL WORK
DATE :
LECTURER’S NAME: WAN ZAIMI BIN WAN YUSOF
GROUP NO. :
TOTAL
STUDENT ID & NAME : MARKS
(100%)

(1) AIMAN IZZUDIN BIN AHMAD NAZRI

13DTK21F1102

(2)

(3)

(4)

(5)

DATE SUBMIT : DATE RETURN :

1 LEARNING OUTCOMES (LO):

1. : Design the basic logic gates, digital circuits from Boolean function and integrated
circuit layout based on the knowledge of integrated circuit design methodology.

2. : Construct the layout design of CMOS circuits using layout design software based on
specific CMOS layout design rules.

3. : Demonstrate elements of environmental sustainability in implementing reduce and

reuse techniques in design parameters and design consideration through practical
work.
2 OBJECTIVES:

At the end of this practical work session, the student should be able to:
1. design the layout of :
a) Horizontal inverter layout
b) Inverter with dual contact and substrate
c) IC 4069 (IC for CMOS inverter/ NOT gate)
2. calculate the layout size/area.

3 THEORY:

The symbol and the truth table of an inverter or NOT gate:

The schematic diagram of a CMOS inverter:

PMOS is placed close to VDD to pull-up the output. NMOS is placed close to ground to pull down the
output. Both Gate terminals of PMOS and NMOS are tied together to be the input. The Drain
terminals of PMOS and NMOS are connected to become the output.

When Vin is high and equal to VDD, the NMOS transistor is ON, while the PMOS is OFF. A direct path
exists between Vout and the ground node, resulting in a steady-state value of 0V.
When the input voltage is low (0V), NMOS transistor is OFF, while PMOS transistor is in ON. A direct
path exists between VDD and Vout, resulting in a steady-state value of VDD.
4 EQUIPMENT / TOOLS:

1. PC Set
2. Microwind 2.6a software.

5 PROCEDURE:

Part 1 : Designing and simulating horizontal CMOS inverter layout.

• Open the Microwind Editor window.

• Select the Foundry file from File menu. Select “cmos012.rul” file.
• Draw the CMOS inverter layout as shown in Figure 2.1.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
• Make sure to obey the design rules.
• Run DRC by selecting:
>Analysis>Design Rule Checker
• Save your layout.

Figure 2.1: Layout of horizontal CMOS inverter layout

• Apply a clock to the input. Click on the Clock icon, and then click on the metal at the gate.
The Clock menu appears, change the name into « input ».

• Set the value of the input pulse as the following:

Time low (tl) = 0.2 ns
Time high (th) = 0.2 ns
Rise time (tr) = Fall time (tf) = 0.001 ns

• Click OK.

• To watch the output, click on the Visible icon and then, click on the metal that connects the
Drain. Change the name into « output». Click OK. The Visible property is then sent to the
node.
 • Simulate the inverter layout by selecting:
>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.
The timing diagram of the inverter appear, as shown in Figure 2.2.

• Measure the optimized area of the layout. The unit is lambda2 (2).

Figure 2.2: Timing diagram of vertical CMOS inverter layout

Theory:

The optimized area of the layout is determined by the following:

Area = Layout Width x Layout Length = 31.5 x 63 = 1984.5 2

Part 2 : Designing and simulating CMOS inverter layout with dual contact and substrate.

• Open the Microwind Editor window.

• Select the Foundry file from File menu. Select “cmos012.rul” file.
• Draw the CMOS inverter layout as shown in Figure 2.3.
Use : NMOS size - W=6, L=2
PMOS size - W=12, L=2
 Figure 2.3: Layout of vertical CMOS inverter layout with dual contact and substrate.

• Make sure to adhere the design rules.

• Run DRC by selecting:

>Analysis>Design Rule Checker

• Save your layout.

• Simulate the inverter layout and get the:

a) timing diagram of the inverter
b) layout area

Part 3 : Designing the layout of IC 4069 (CMOS inverter ).

• Design the layout of IC 4069 based on the CMOS IC logic gates shown in Figure 2.4.

Figure 2.4 : Internal Structure of IC 4069

• Do the DRC to ensure that your design conforms to all design rules.
• Measure the optimized area of the layout (the unit is λ2).
6 RESULT

In your report, include the following:

PART 1
a) Inverter layout.

b) Input/output timing diagram

c) layout area = _________ x _________ = ____________²

PART 2: CMOS INVERTER WITH DUAL CONTACTS AND SUBSTRATE
a) INVERTER LAYOUT

b) INPUT/OUTPUT TIMING DIAGRAM.

c) Layout area = _________ x _________

= ____________2

PART3

a) IC LAYOUT
 d) The optimized area of the IC layout = _________ x _________
= ____________2
(4 marks)

7 DISCUSSION

1. Explain the operation of NMOS and PMOS transistors in CMOS inverter by using a suitable
diagram.
 When the low input voltage is given to the CMOS inverter, then the PMOS transistor is switched
ON whereas the NMOS transistor will switch OFF by allowing the flow of electrons throughout
the gate terminal & generating high logic output voltage.

Similarly, when the high input voltage is given to the CMOS inverter then, the PMOS transistor is
switched OFF whereas the NMOS transistor will be switched ON avoiding as many electrons from
attaining the output voltage & generating low logic output voltage.
(4 marks)

2. Make a comparison between the optimized area of the layouts in Part 1 and Part 2 and explain
your findings.

Both design' optimized areas are 288 lambdas. This is so that the area of the Horizontal
CMOS Inverter can be precisely matched by the Dual Contact CMOS Inverter with
Substrate, while obtaining the appropriate substrate control and electrical performance. To
do this, it is necessary to strike a balance between improving well-tap structures, contact
positions, and transistor placement.
(3 marks)

3. Explain the difference between an inverter from the TTL 7400 families and from the CMOS 4000
families.

To compare TTL and CMOS, one must think about the points mentioned above. As the CMOS
consists of the FET’s and the TTL circuits are made up of BJT, CMOS chips are much faster and
efficient. There is a much higher density of the logic functions in a single chip in CMOS as
compared to the TTL. Also, the power consumption of the TTL circuits is higher when
compared to the power consumption of CMOS. Though the CMOS has lesser power
consumption, CMOS chips are more susceptible to the static electric discharge and thus can
be damaged easily. CMOS chips could have the TTL logics and could be used for the
replacement of the TTL IC.
(3 marks)
8 CONCLUSION

Give TWO (2) conclusions for this practical work. (4 marks)

In my conclusion, I have learn how to design a layout of horizontal inverter layout.

Then, I able to design a inverter with dual contact and substrate. After that, I
understand about IC 4069. Lastly, I able to calculate the layout size.
 PRACTICAL SKILL ASSESSMENT RUBRIC
DEC50143 CMOS IC DESIGN & FABRICATION
PRACTICAL WORK 2
Student Name : Class :
Date :
Student ID# :

SCORE DESCRIPTION
ASPECTS EXCELLENT MODERATE POOR SCALE SCORE
4-5 2-3 1
Use correct technology feature Use correct technology feature
A. Technology feature Use other technology feature. x1
for ALL parts of the layout. for parts of the layout.
Follow lambda design rule for
Follow lambda design rule for Follow lambda design rule for
B. Design rule minimum width and spacing for x1
MANY of the polygons. ONLY a few of the polygons.
ALL polygons.
Use correct PMOS and NMOS Use acceptable PMOS and NMOS Use incorrect PMOS and
C. Transistor size x2
transistor size. transistor size. NMOS transistor size.
Use correct number of metal Use correct metal layers but Use incorrect metal layers and
D. Metal layers x2
layers and width. incorrect width. width.
‘No DRC error’ Able to produce ‘No DRC error’ Able to produce ‘No DRC error’ Not able to produce ‘No DRC
E. x2
display display for ALL layouts. display for some of the layouts. error’ display at ALL.
Layout Design Produce acceptable floorplan
Produce good floorplan and Produce appropriate floorplan
F. – input / output / and input / output layout x2
input / output layout design. and input / output layout design.
floorplan design.
Not able to produce any
Able to produce the simulation Able to produce the simulation
G Layout simulation simulation for ALL of the x2
of ALL layouts correctly. for some of the layouts correctly.
layouts.
Layout size (end Produce small layout size (end Produce acceptable layout size Produce large layout size (end
H. x2
product) product). (end product). product).
TOTAL / 70

…………….…………………….
Supervisor Name & Signature