Elements of Computing Systems-1

Combinational Logic (Part 2)

Dr. Jyothish Lal G, Assistant Professor (Sr. Gr)

Department of AI / Center for Computational Engineering and Networking (CEN)
Amrita School of AI, Coimbatore
Acknowledgment: Prof. Noam Nisan, Prof. Shimon Schocken
Multi-bit Buses

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 Arrays of bits
• Manipulate array of bits together
• We conceptually think such groups as a single entity, termed bus
• HDL has a convenient notion for representing bus

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Example : Addition of two 16 bit numbers

• The bitwise additions are done in parallel

• The carry propagation is sequential

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Buses in HDL

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Using buses in HDL

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Using buses in HDL

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Working with bits in buses: Example 1

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Working with bits in buses: Example 2

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Relevant bus tips

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Relevant bus tips

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 Hack exercises
• Implement 16 bit variants of
– NOT gate (chip name chip name in project folder : Not16)
16-bit bitwise NOT
– AND gate (chip name chip name in project folder : And16)
16-bit bitwise AND
– OR gate (chip name chip name in project folder : Or16)
16-bit bitwise OR
• Implement multi-way variant
– Or8way (ie, OR together all 8 bits of the input)

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 Parallel Adder Design
• Various designs of n-bit parallel adder
– Ripple carry adder
– Carry look-ahead adder

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 Ripple carry adder
• Cascade n full adders to create a n-bit parallel adder
• Carry output from ith stage propagates as carry input to (i+1)th
stage

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Important note :
4 bit binary parallel adder can be constructed
✓By using 4 full adders with input carry for LSB full adder as zero
Or
✓By using 3 full adders and one half adder

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4 bit Parallel Adder :HDL code

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 Hack exercise
• Implement 4-bit parallel adder
• Implement 16-bit parallel adder (chip name in
project folder: Add16)

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 Drawback of Ripple carry adder
• The main bottleneck is the carry, which
propagates sequentially from one stage to the
next
• How this can be overcome ?
– Generate all the carry bits in parallel before the
addition starts
– All the addition can be done parallel

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 Thank You

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