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HDLexp 1
HDLexp 1
HDLexp 1
VHDL Code :
Behavioral Modelling
entity decoder is
Port ( a : in STD_LOGIC_VECTOR(2 DOWNTO 0);
a1 : out STD_LOGIC_VECTOR(7 DOWNTO 0));
end decoder;
architecture Behavioral of decoder is
begin
process(a)
begin
case a is
when "000"=>a1<="10000000";
when "001"=>a1<="01000000";
when "010"=>a1<="00100000";
when "011"=>a1<="00010000";
when "100"=>a1<="00001000";
when "101"=>a1<="00000100";
when "110"=>a1<="00000010";
when "111"=>a1<="00000001";
when others=>null;
end case;
end process;
end Behavioral;
Observations:
Result:
The 3:8 decoder was implemented using schematics and VHDL and
successfully simulated and verified.
AIM: Write a VHDL program to implement 3:8 decoder
RTL Schematic: