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    The document outlines 13 experiments conducted between December 2022 and March 2023 related to designing and realizing various digital logic circuits. The experiments include designing logic gates, half and full adders/subtractors, multiplexers, demultiplexers, flip-flops, shift registers, and priority encoders using basic gates like NAND and NOR. Dates and remarks are provided for each experiment.

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    The document outlines 13 experiments conducted between December 2022 and March 2023 related to designing and realizing various digital logic circuits. The experiments include designing logic gates, half and full adders/subtractors, multiplexers, demultiplexers, flip-flops, shift registers, and priority encoders using basic gates like NAND and NOR. Dates and remarks are provided for each experiment.

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    3 views1 page

    CONTENTS

    Uploaded by

    pojito4268
    The document outlines 13 experiments conducted between December 2022 and March 2023 related to designing and realizing various digital logic circuits. The experiments include designing logic gates, half and full adders/subtractors, multiplexers, demultiplexers, flip-flops, shift registers, and priority encoders using basic gates like NAND and NOR. Dates and remarks are provided for each experiment.

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    of 1

    S.NO.

    EXPERIMENT NAME DATE REMARKS


    1. Design and realize all 12/12/2022
    logic gates and universal
    gates.
    2. Design and realize all 12/12/2022
    basic gates from NOR
    and NAND gate.
    3. Design and realize half 19/12/2022
    adder, full adder.
    4. Design and realize half 26/12/2022
    subtractor, full subtractor.
    5. Design and realize 04/01/2023
    multiplexer.
    6. To design and realize 16/01/2023
    Demultiplexer.
    7. Design and realize S R 16/01/2023
    Flip Flop.
    8. Design and realize J K 06/02/2023
    Flip Flop.
    9. Design and realize Master 13/02/2023
    Slave J K Flip Flop using
    NAND gate.
    10. Design and realize 20/02/2023
    SERIAL-IN-SERIAL-
    OUT SHIFT
    REGISTRES.

    11. Design and realize 20/02/2023


    SERIAL-IN-
    PARALLEL-OUT SHIFT
    REGISTRES.

    12. Design and realize 4 bit 06/03/2023


    binary adder.
    13. Design and realize 06/03/2023
    Priority Encoder.

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