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    Lab1 Ex2 - 2

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    ABHYANSH SHRIVASTAVA
    This document describes a test bench for a logic circuit with two inputs (a and b), a 2-bit selector input (sel), and one output (c). The circuit uses a case statement to determine the logic operation performed on a and b based on the value of sel, performing AND, OR, NAND, or NOR. The test bench applies all possible combinations of inputs over time and verifies the output.

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    Lab1 Ex2 - 2

    Uploaded by

    ABHYANSH SHRIVASTAVA
    3 views6 pages
    This document describes a test bench for a logic circuit with two inputs (a and b), a 2-bit selector input (sel), and one output (c). The circuit uses a case statement to determine the logic operation performed on a and b based on the value of sel, performing AND, OR, NAND, or NOR. The test bench applies all possible combinations of inputs over time and verifies the output.

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    lab1 ex2_2

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    This document describes a test bench for a logic circuit with two inputs (a and b), a 2-bit selector input (sel), and one output (c). The circuit uses a case statement to determine the logic operation performed on a and b based on the value of sel, performing AND, OR, NAND, or NOR. The test bench applies all possible combinations of inputs over time and verifies the output.

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    © All Rights Reserved
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    Flag for inappropriate content
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    3 views6 pages

    Lab1 Ex2 - 2

    Uploaded by

    ABHYANSH SHRIVASTAVA
    This document describes a test bench for a logic circuit with two inputs (a and b), a 2-bit selector input (sel), and one output (c). The circuit uses a case statement to determine the logic operation performed on a and b based on the value of sel, performing AND, OR, NAND, or NOR. The test bench applies all possible combinations of inputs over time and verifies the output.

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    © All Rights Reserved
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    of 6

    Lab1_2_2( when case)

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity L1_E2_2_201B013 is

    Port ( a : in STD_LOGIC;

    b : in STD_LOGIC;

    sel : in STD_LOGIC_VECTOR (1 downto 0);

    c : out STD_LOGIC);

    end L1_E2_2_201B013;

    architecture Behavioral of L1_E2_2_201B013 is

    begin

    process(sel,a,b)

    begin

    case sel is

    when "00" => c <= a and b;

    when "01" => c <= a or b;

    when "10" => c <= a nand b;

    when others => c <= a nor b;

    end case;

    end process;

    end Behavioral;
    Test Bench

    LIBRARY ieee;

    USE ieee.std_logic_1164.ALL;

    ENTITY l1_e2_013_tb IS

    END l1_e2_013_tb;

    ARCHITECTURE behavior OF l1_e2_013_tb IS

    COMPONENT L1_E2_2_201B013
    PORT(

    a : IN std_logic;

    b : IN std_logic;

    sel : IN std_logic_vector(1 downto 0);

    c : OUT std_logic

    );

    END COMPONENT;

    signal a : std_logic := '0';

    signal b : std_logic := '0';

    signal sel : std_logic_vector(1 downto 0) := (others => '0');

    signal c : std_logic;

    BEGIN

    uut: L1_E2_2_201B013 PORT MAP (

    a => a,

    b => b,

    sel => sel,

    c => c

    );

    -- Stimulus process

    stim_proc: process

    begin

    sel <= "00";

    a <= '0';

    b <= '0';
    wait for 100 ns;

    sel <= "00";

    a <= '0';

    b <= '1';

    wait for 100 ns;

    sel <= "00";

    a <= '1';

    b <= '0';

    wait for 100 ns;

    sel <= "00";

    a <= '1';

    b <= '1';

    wait for 100 ns;

    sel <= "01";

    a <= '0';

    b <= '0';

    wait for 100 ns;

    sel <= "01";

    a <= '0';

    b <= '1';

    wait for 100 ns;

    sel <= "01";

    a <= '1';

    b <= '0';

    wait for 100 ns;


    sel <= "01";

    a <= '1';

    b <= '1';

    wait for 100 ns;

    sel <= "10";

    a <= '0';

    b <= '0';

    wait for 100 ns;

    sel <= "10";

    a <= '0';

    b <= '1';

    wait for 100 ns;

    sel <= "10";

    a <= '1';

    b <= '0';

    wait for 100 ns;

    sel <= "10";

    a <= '1';

    b <= '1';

    wait for 100 ns;

    sel <= "11";

    a <= '0';

    b <= '0';

    wait for 100 ns;


    sel <= "11";

    a <= '0';

    b <= '1';

    wait for 100 ns;

    sel <= "11";

    a <= '1';

    b <= '0';

    wait for 100 ns;

    sel <= "11";

    a <= '1';

    b <= '1';

    wait for 100 ns;

    wait;

    end process; END;

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