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Chapter 2
Instructions: Language of the Computer
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Instruction Set

• The repertoire of instructions of a computer

• Different computers have different instruction sets
• But with many aspects in common
• Early computers had very simple instruction sets
• Simplified implementation
• Many modern computers also have simple instruction sets → RISC
instruction sets

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Instruction Set Architecture

• It is common to execute Instruction Set Architecture (ISA) with

implementation (micro)-architecture.
• The same ISA can have multiple implementations.
• The table below provides examples of features that are/aren’t part of some ISA.
Specified by ISA
There is an add instruction
8 Registers, each is 32 bits
multiply instruction exists
Instructions are 16-bit wide and have to be
aligned
There are three branch instructions variations
Data are stored in big-endian order
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Not Specified by ISA
There is a 32 Kbyte cache
Implemented using CMOS technology
The multiplier by a series of shifts and adds.
CPU stores a fetched instruction in some
“invisible” register.
There is a “tournament” branch predictor.
The frequency is 1.5 GHz
…..
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The RISC-V Instruction Set

• Used as the example throughout the book

• Developed at UC Berkeley as open ISA
• Now managed by the RISC-V Foundation (riscv.org)
• Typical of many modern ISAs
• See RISC-V Reference Data tear-out (green) card
• In this course, we study the 32-bit version of the RISC V architecture.
• ( Previous sections studied the 64-bit version).

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ISA Overview
• Instructions: 32-bits (8 bits = 1byte)
• Instructions are aligned in memory (must start at location divisible by 4).
• Number of (gp) Registers: 32. (X0..X31), X0 ≡ 0 (inside the CPU)
• Each register is 32-bits wide & register 0 is hardwired (fixed) to the value 0.
• Memory is byte-addressable
• Data address is the address of the lowest byte of the data item.
• Data does not have to be aligned in memory (can start at any address).
• Data Aligned means address A of data is multiple of S (size of data).
• Data is stored in a little-endian manner (Endianness??)
• That means the least significant byte of a word in stored in the lowest address of the word.
• Example: integer 0x00112233 at location 80 is stored as
80 81 82 83

Little-Endian 33 22 11 00
Big Endian 00 11 22 33

Interesting Fact: Little-endian/Big-endian comes originally from the book

Gulliver’s travels.
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Assembly Instructions

• A user-friendly SW representation of the binary instructions.

• The assembler translates assembly instructions into binary code.
• Programmer does not have to remember binary representation.
• There can be multiple assemblers (by more than one vendor) for the
same ISA.
• For example
• Assembler 1: add x9, x8, x7
• Assembler 2: R9= R8+R7
• Both should translate to exactly same add instruction.

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RISC-V Registers SW Usage Convention (part of ABI)

• x0: the constant value 0, • This naming is useful for standardizing, and unless you will
• x1: return address, write real code interfacing with other people’s libraries and/or
code, it can be ignored.
• x2: stack pointer • But it is good to know
• x3: global pointer
• x4: thread pointer
• x5 – x7, x28 – x31: temporaries
• x8: frame pointer
• x9, x18 – x27: saved registers
• x10 – x11: function arguments/results
• x12 – x17: function arguments

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Memory Accesses: Loads/Stores

• Variables reside in memory.

• To copy into processor registers→ “Load” instructions
• To copy from processor, register to memory → “Store” instructions.
RISC V Load/Store Example

lw x9, 101(x13) sw x9, 101(x13)

• Calculate memory address: • Calculate memory address:
• addr = 101 + contents(x13) • addr = 101 + contents(x13)
• Copy four bytes [addr:addr+3] to register x9 • Copy register x9 into four bytes [addr:addr+3]

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Load Instruction Variations

• lw→ load word, lh→ load halfword, lb→ load byte
• Signed versus unsigned loads
• lh/lb load 4/2/1 bytes into least significant bytes of a 4-byte register.
• Issue: how to fill the rest of the register bytes?
• Answer: Depends on whether we treat the quantity loaded as signed or unsigned.
• Signed loads fill the rest of the register with the sign of the number (most significant bit is the sign).
• Unsigned loads fill the rest of the register with 0’s.
• lh/lb are signed loads. lhu/lbu are the unsigned equivalents.
• lw does not leave register bits to be filled.
Signed/Unsigned Example
lb “0xff” into register lbu “0xff” into register
ff ff ff ff 00 00 00 ff

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Store Instruction Variations

• sw→ store word, sh→ store halfword, sb→ store byte
• sh/sb copy the least significant 4/2/1 bytes of a register into bytes of memory.
• Because source data and destination memory have same size, no signed/unsigned distinction
is needed.
• Example: sw x3 to location 102
• Assume x3 = 0x01 0x12 0x23 0x34

Memory 102 103 104 105

Address
Contents Before 0xaa 0xbb 0xcc 0xdd

Contents After 0x34 0x23 0x12 0x01

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Load Instruction Format

Func3[2:0]
Immed[11:0] Rs1[4:0] Rd[4:0] Opcode[6:0](decimal)
(binary)
lb 0 0 0
lh Source register 0 0 1
Destination 3
lw 12-bit 2’s complement offset (part of address 0 1 0 (same opcode shared by all load
register
lbu calculation) 1 0 0
variants)

lhu 1 0 1

All variants share same opcode, differentiated by func3 field.

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Store Instruction Format

Func3[2:0]
Immed[11:5] Rs2[4:0] Rs1[4:0] Immed[4:0] Opcode[6:0](decimal)
(binary)
sb 0 0 0 Lower 5 bits
Source register Source register 35
sh Upper 7 bits of 12-bit 0 0 1 of 12-bit 2’s
for data to copy (part of address (same opcode shared
2’s complement offset complement
sw to memory calculation) 0 1 0 by all load variants)
offset

All variants share same opcode, differentiated by func3 field.

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Arithmetic & Logic Instructions-1

• R-type: 2 inputs in source registers, output in destination register.
• Destination register cannot be x0.
• Examples:
add x9, x8, x7
xor x11, x19, x5
• Format:
Func7[9:3] Rs2[4:0] Rs1[4:0] Func3[2:0] Rd[4:0] Opcode[6:0](decimal)
(binary) (binary)
51

• Function bits select specific r-type operation

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Arithmetic & Logic Instructions-2

• I-type: 1 input in source registers, 1 input immediate value in
instruction, output in destination register.
• Destination register cannot be x0.
• Immediate data reduces pressure on register usage.
• But data width limited to 12 bits (2’s complement)
• Examples:
addi x9, x8, -5
xori x11, x19, -5
• Format: Immed[11:0] Rs1[4:0] Func3[2: Rd[4:0] OpCode [6:0]
• Note similarity to load formats 0]
but different opcode (19). decimal
19

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Func* Fields

• Seven bits of opcode → 128 instructions.

• To save on opcode usage (to allow for future extensions):
• Groups of similar instructions share same opcode
• Distinguished from one another using Func3 or Func7 fields.

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Short Code Example

• C code:
f = (g + h) - (i + j);
• Compiled RISC-V code.
• Assume f through j stored in consecutive memory locations starting at value stored in x2.

lw x3,4(x2); load g
lw x4, 8(x2); load h
lw x5, 12(x2); load i
lw x6, 16(x2); load j
add x7, x3, x4; t0=g + h
add x8, x5, x6; t1=i + j
sub x7, x7, x8; t0= t0-t1
sw x7, 0(x2); store f
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Array Usage Example

• C code:
A[12] = h + A[8];
• h in x21, base address of A in x22
• Compiled RISC-V code
• Assuming h and address of A[0] are already in registers
lw x9, 32(x22); Index 8 requires offset of 32
add x9, x21, x9
sw x9, 48(x22); Index 12 requires offset of 48

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Shift Operations
funct6 immed rs1 funct3 rd Opcode =19
6 bits 6 bits 5 bits 3 bits 5 bits 7 bits

• immed: how many positions to shift

• Shift left logical
• Shift left and fill with 0 bits
• slli by i bits multiplies by 2i
• Shift right logical
• Shift right and fill with 0 bits
• srli by i bits divides by 2i (unsigned only)

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Conditional Operations
• Branch to a labeled instruction if a condition is true
• Otherwise, continue sequentially

• beq rs1, rs2, L1

• if ((rs1) == (rs2)) branch to instruction labeled L1 otherwise go to next instruction
• bne rs1, rs2, L1
• if ((rs1) != (rs2)) branch to instruction labeled L1 otherwise go to next instruction
• Note
• == and != tests apply to contents of registers – not their names.
Example: (x7 != x8) may be true or false depending on their contents.
obviously (x7==x7) is always true.

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Using Branches in If Statements

• C code:
if (i==j) f = g+h;
else f = g-h;
• f, g, … in x19, x20, …
• Compiled RISC-V code:
bne x22, x23, Else
add x19, x20, x21
beq x0,x0,Exit // unconditional
Else: sub x19, x20, x21
Exit: …

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Using Branches in Loop Statements

• C code:
while (save[i] == k) i+= 1;
• i in x22, k in x24, address of save in x25
• Compiled RISC-V code:
Loop: slli x10, x22, 3; shift left logical immediate
add x10, x10, x25
lw x9, 0(x10); load save[i] into x9
bne x9, x24, Exit
addi x22, x22, 1
beq x0, x0, Loop; branch always back to Loop
Exit: …

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More Conditional Operations

• blt rs1, rs2, L1

• if (rs1 < rs2) branch to instruction labeled L1
• bge rs1, rs2, L1
• if (rs1 >= rs2) branch to instruction labeled L1
• Example
if (a > b) a += 1;
• a in x22, b in x23
bge x23, x22, Exit // branch if b >= a
addi x22, x22, 1
Exit:

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Branch Instruction Formatting

• Branch instructions specify

• Opcode, two registers, target address
• Most branch targets are near the branch instruction.
• Forward (to higher addresses) or backward (to lower addresses)
• Memory addresses are 32 bits.
→Obviously, the whole memory address of target cannot be embedded in instruction.
• PC-relative addressing is used.
• The distance between the branch instruction and the target address is stored.
• This means the branch instruction can only reach a window of instructions
surrounding it.

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Branch Instruction Formatting

SB format:
Immed[12] Immed[10:5] Rs2[4:0] Rs1[4:0] func3 Immed[4:1] Immed[11] Opcode[6:0]
=96

• Immed[0] is not stored and is equal to zero.

• Immed[12] is the sign bit used for sign-extending the immediate value.
• Immed[0] is not stored because any instruction address is divisible by 2
• Hence Immed[0] is ALWAYS 0.
• Actually, in the current implementation instruction address is divisible by 4.
• Means Immed[1] is ALWAYS 0.
• But to accommodate future extensions of instruction set to include 16-bit
instructions, we store Immed[1], and not assume it is always 0.
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Branch Instruction Encoding Example 1

Assume beq at address 80 and target (END) at 180

(80) beq x1, x3, END
….
END ….
Immed = distance =180-80= 100 dec→ 0000_0011_0010_0 binary
0000_0011_0010_0 (least significant bit not stored in instruction).

The assembler will take the leftmost 12 bits and pack them in
instruction binary representation.

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Branch Instruction Decoding Example 1

During run time assume beq is at address 80 (PC=80)

beq x1, x3, END
• Hardware finds 0000_0011_0010 stored in Immed[12:1] fields
• Hardware extends it to 0000_0011_0010_0 binary.
• 0000_0011_0010_0 = 100 dec
• Therefore, HW advances program counter to PC+100= 180.

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Procedure Call Instructions

• Procedure call: jump and link

80 jal x1, ProcedureLabel; put 84 in x1
• Address of following instruction put in x1
• Jumps to target address
• Procedure return: jump and link register
jalr xd, 0(x5)
• Like jal, but jumps to 0 + address in x5
• Use xd as rd
• Can also be used for computed jumps
• e.g., for case/switch statements

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Jump Addressing
• Jump and link (jal) target uses 21-bit immediate for
larger range
• UJ format:
imm[10:1] imm[19:12] rd opcode
5 bits 7 bits
imm[20] imm[11]

◼ For long jumps, e.g., to 32-bit absolute

address
◼ lui: load address[31:12] to temp register
◼ jalr: add address[11:0] and jump to target
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RISC-V Encoding Summary

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RISC V Versus MIPS Instruction Encoding

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Concluding Remarks

• Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Good design demands good compromises
• Make the common case fast
• Layers of software/hardware
• Compiler, assembler, hardware
• RISC-V: typical of RISC ISAs
• c.f. x86

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