A

SEMINAR REPORT
ON

“THREE-DIMENSIONAL INTEGRATED CIRCUIT”

Submitted in partial fulfilment of the requirement for the degree of

Bachelor of Engineering

In
Electronics and Communication Engineering

Guided By Submitted By

Mr. Navneet Parihar Dileep Sharma

Electronics and Communication Department Roll No.: 20UECE7012
M.B.M University, Jodhpur Enrolment No.:19R/44431

Department of Electronics and Communication Engineering

M.B.M. University
Jodhpur-342011
2022-23
 CERTIFICATE

This is to certify that this seminar report titled Three-Dimensional Integrated Circuit
has been submitted by Dileep Sharma (19R/44431) in partial fulfillment of the
requirements for the degree of Bachelor of Engineering in Electronics &
Communication Engineering of the MBM University, Jodhpur during the academic
year 2022-23 and is a record of study applied by him/her under my guidance and
supervision.

______________________

Mr. NAVNEET PARIHAR Date:

Department of Electronics & Communication Engineering,
M.B.M University, Jodhpur

i
 ACKNOWLEDGEMENT

I have made this report file on the topic Three-Dimensional Integrated Circuit. I have
tried my best to elucidate all the relevant details to the topic to be included in the report.

My efforts and wholehearted co-corporation of each and every one has ended on a
successful note. However, it would not have been possible without the kind support and
help of many individuals and organizations. I would like to extend my sincere thanks to
all of them.

I am highly indebted to Dr. RAJESH BHADADA, Professor and Head of Department

for their guidance and constant supervision throughout the preparation of this topic. I
thank him for providing me the reinforcement, confidence and most importantly the track
for the topic whenever I needed it.

I would like to thank Mr. NAVNEET PARIHAR Seminar Mentor for his valuable
suggestions in the preparation of the seminar report.

I would like to express my gratitude toward the members of M.B.M University, Jodhpur
for their kind cooperation and encouragement which help me in completion of this report.

________________________
Dileep Sharma
Roll No.: 20UECE7012
Enrolment No.:19R/44431
Department of Electronics & Communication Engineering,
M.B.M University, Jodhpur

ii
 ABSTRACT

The future of technology is in compact but faster and affordable devices that provide
ability to connect anywhere, anytime with any service to get uninterrupted access to
information, entertainment, communication, monitoring and control.
Microminiaturization is the key to make the compact electronic devices used for high
reliability in application. Latest trend in technology is to move from3D flexible
configuration to 3D stacking and then to 3D ICs. There are different motivations like form
factor, electrical performance and cost of 3D integration for development of 3D IC. The
3D IC technology is at research and development stage in the bigger IC companies today
and technical issues are very close to be solved. The adoption of advanced packaging
technologies could also change the industry food chain of the semiconductor. The current
goal is to develop a cost-effective technology tool for 3D ICs.

3D integration consists of stacking integrated circuits and connecting them vertically. It

replaces long vertical wiring connections by vertical interconnects Minimum pitch of
vertical interconnect had been used previously in 2007 was approximately 50µm which
has been now a day reduced up to 5 µm and will reduce to less than 2 µm in near future.
Application of 3D integration is 3D stacked memory and in future application will be in
logic (multi core processor with cache memory) and vertical device on CMOS or
multilevel 3D IC. 3D ICs offer numerous other advantages as well, including the potential
for reduced interconnect length, and the ability to easily integrate heterogeneous
technologies on multiple tiers into a single package.

This report discusses the latest trends in 3D ICs like TSV as well as challenges in 3D IC
technologies, its applications and the advantages of using this technology. Also, what is
the future scope and enhancement to the above proposed system so that it could be more
accurate, is discussed in the report.

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 TABLE OF CONTENTS
Certificate i
Acknowledgement ii
Abstract iii
Table of Contents iv
List of Figure v
Chapter-1 Introduction 1
1.1 Integrated circuit 2
1.2 History 2
1.2.1 Multi-Chip modules (MCMs) 3
1.2.2 System on chip (SOC) 3
1.2.3 2.5D ICs 4
Chapter-2 Literature Review 6
Chapter-3 Development Of 3D ICs 10
3.1 3D Architecture 12
3.1.1 Advantages Of 3D Architecture 13
3.2 Area And Performance Estimation of 3D ICs 13
3.2.1 2-D And 3-D Wire Length Distributions 14
3.2.2 Estimating 2D and 3D Chip Area 16
3.2.3 Two Active Layer 3D Circuit Performance 18
3.2.4 Effect Of Increasing Number Of Silicon Layers 20
3.2.5 Effect Of Increasing The Number Of Metal Layers 20
3.2.6 Optimization Of Interconnect Distribution 21
3.3 Challenges For 3-D Integration 21
3.3.1 Thermal Issues In 3-D ICs 21
3.3.2 Reliability Issues In 3-D ICs 22
3.4 Manufacturing Methods Of 3-D ICs 22
3.4.1 Beam Recrystallization 22
3.4.2 Silicon Epitaxial Growth 23
3.4.3 Processed Wafer Bonding 24
3.4.4 Vertical Interlayer Interconnect Technology Options 25
3.5 Applications 26
Chapter-4 Conclusion and Future Works 27
4.1 Conclusion 27
4.2 Future Works 27
Appendix 29
References 31

iv
List of Figure

Fig 1 Multi Chip Module 3

Fig 2 System on Chip (SOCs) 4
Fig 3 2.5D IC and 3D IC 7
Fig 4 Various ICs types 9
Fig 5 Three die stacks, each comprised of two layers using three possible 11
bond styles: (a) face-to-face, (b) face-to-back, and (c) back-to-back.
Fig 6 3D IC Architecture 12
Fig 7 Gates block 14
Fig 8 Wiring tiers 17
Fig 9 The effect of using 3-D ICs with constant metal layers 20
Fig 10 Beam recrystallization 23
Fig 11 Epitaxial growth of 3D ICs 24
Fig 12A Comparison between 2D ICs and Monolithic 3D ICs on footprint 29
Fig 13A Comparison of a Monolithic 3D-IC and a 2D-IC at the same 29
Technology node
Fig 14A Costing of 3D ICs 30
Fig 15A 3D-ICs Dynamic thermal analysis 30

v
CHAPTER 1
INTRODUCTION

In the domain of electronic product design, solely relying on process shrink as the primary
driver of product innovation and improved system performance is no longer a viable
approach. The cost and complexity associated with advanced nodes has everyone looking
for alternatives to the traditional monolithic system on chip (SoC). The path most are
taking leads to the world of “More than Moore” and heterogenous integration. These
heterogenous, multi-chiplet architectures provide a much lower cost alternative to the
latest design nodes, while still providing a robust re-use model based on IP in the form
of physically realized chiplets. The package design now sits in the center of the universe
for the next generation of electronics.

There is a saying in real estate; when land get expensive, multi-storied buildings are the
alternative solution. We have a similar situation in the chip industry. For the past thirty
years, chip designers have considered whether building integrated circuits multiple layers
might create cheaper, more powerful chips. Performance of deep-sub micrometer very
large scale integrated (VLSI) circuits is being increasingly dominated by the
interconnects due to increasing wire pitch and increasing die size. Additionally,
heterogeneous integration of different technologies on one single chip is becoming
increasingly desirable, for which planar (2-D) ICs may not be suitable.

The three dimensional (3-D) chip design strategy exploits the vertical dimension to
alleviate the interconnect related problems and to facilitate heterogeneous integration of
technologies to realize system on a chip (SoC) design. By simply dividing a planar chip
into separate blocks, each occupying a separate physical level interconnected by short
and vertical interlayer interconnects (VILICs), significant improvement in performance
and reduction in wire-limited chip area can be achieved. In the 3-Ddesign architecture,
an entire chip is divided into a number of blocks, and each block is placed on a separate
layer of Si that are stacked on top of each other.

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1.1 INTEGRATED CIRCUIT (IC)

To define Integrated Circuit (IC) we can consider that If multiple electronic components
are interconnected on a single chip of semiconductor material, then that chip is called as
an integrated circuit (IC). It consists of both active and passive components

An integrated circuit or monolithic integrated circuit (also referred to as an IC, a chip, or

a microchip) is a set of electronic circuit on one small flat piece (or "chip") of
semiconductor material, usually silicon. Large number of tiny MOSFETs (metal–oxide–
semiconductor field-effect transistor) integrate into a small chip. This results in circuits
that are orders of magnitude smaller, faster, and less expensive than those constructed of
discrete electronic components. The IC's mass production capability[1], reliability, and
building-block approach to integrated circuit design has ensured the rapid adoption of
standardized ICs in place of designs using discrete transistors. ICs are now used in
virtually all electronic equipment and have revolutionized the world
of electronics. Computers, mobile phones and other home appliances are now
inextricable parts of the structure of modern societies, made possible by the small size
and low cost of ICs such as modern computer processors and microcontrollers.

1.2 HISTORY

The concept of Integrated Circuit (IC), also known as “chip”, which integrates a circuit
of several electronic components into a solid block was envisaged in 1952. In 1959, the
invention of the planar process with aluminum metallization by Robert Noyce and Jean
Hoerniat Fairchild Semiconductor enabled large-scale production of ICs.

The development of the integration of circuitry was very rapid. In the year 1964, the
small-scale integration (SSI) chip having digital logic gates circuitry was introduced.
Gordon Earle Moore at Fairchild semiconductor predicted that the number of transistors
on a silicon chip would increase from 50 in 1965 to 65,000 in 1975. It was recognized as
his first articulation of Moore's law suggests that the number of transistors on a chip will
double every year[2]. Moore's prediction indeed was true and Medium-Scale Integration

2
(MSI) chip with a complete register circuit appeared in 1968. The Large-scale integration
(LSI) memory chip (256-bit RAM) was produced by Fairchild in 1970. In 1971, the LSI
chips with 1024-bit Dynamic Random access memory (DRAM) and Universal
Asynchronous Receiver Transmitter (UART) were developed

1.2.1 Multi Chip Module(MCMs): Sometime around the beginning of the 1990s we
saw the advent of devices known as multi-chip modules (MCMs) . To the best of my
recollection, these typically involved a number of digital-only dice* mounted on the same
package substrate. And speaking of package substrates (meaning the base layer), a variety
of materials could be used, ranging from silicon to super-thin laminates (like little printed
circuit boards), all presented in ceramic, metallic, or even plastic packages. (* Dies is
used as the plural for die in the sense of a mold, while dice is used as the plural (and
increasingly as the singular) in the sense of a small random number generator (on
gambling and games, we may roll one die or toss two or more dice ). Dice is also the
accepted plural form of die in the semiconductor industry).

Fig 1: Multi Chip Module

1.2.2 System On Chip(SOCs): Different people have different definitions as to exactly

what comprises an SoC. A digital logic designer might say that an SoC contains one or

3
more processor cores, memory blocks, peripheral functions, and hardware accelerators,
all created on the same piece of silicon[3]. By comparison, someone like a system
architect looking at things from a slightly higher vantage point might say that an SoC is
a single device that combines digital logic, memory, and analog/RF functions all on the
same die.

Fig 2: System on Chip (SOCs)

The advantage of an SoC is that you get the highest performance with the lowest power
consumption – at least you do for the digital portions of the device. The disadvantage is
that creating one of these little rascals is horrendously complicated, resource intensive,
and time consuming. Also, adding analog and RF functions on the same die as the digital
logic my mean that (a) the analog/RF functions aren’t as optimal as they could be if
implemented using a dedicated process and (b) you can run into all sorts of noise and
isolation problems. And yet another consideration is the time and expense involved in re-
spinning the design in the future to evolve existing functionality or add new features.

1.2.3 2.5D ICs: All of which leads us to the concept of a 2.5D IC/SiP. The main difference
between a traditional 2D IC/SiP as shown below and a 2.5D IC/SiP as shown below is
that, in the case of the 2.5D version, a silicon interposer is placed between the SiP

4
substrate and the dice, where this silicon interposer has through-silicon vias (TSVs)
connecting the metallization layers on its upper and lower surfaces.

In this case, the dice are attached to the silicon interposer using micro-bumps, which are
~10um in diameter. Meanwhile, the silicon interposer is attached to the SiP substrate
using regular flip-chip bumps, which will be ~100um in diameter. The tracks on the
silicon interposer’s topside and backside metal layers (there can be multiple metal layers
in both cases) are created using the same processes as the tracks on the silicon chips.
Although the silicon interposer and the silicon dice in the image above appear to be a little
“chunky”, you have to remember that this drawing is not to scale. In reality, the dice are
only ~0.2mm thick, while the silicon interposer is not much thicker.

As one example of the use of this technology, the Xilinx Virtex-7 2000T device has four
FPGA dice attached to a silicon interposer, which supports ~10,000 silicon-speed
connections between adjacent dice[4].The advantage of using 2.5D IC/SiP technology is
that it’s an incremental step from traditional 2D IC/SiP technology that offers tremendous
increases in capacity and performance. There are also yield advantages, because it’s easier
to make a number of small dice as opposed to a single large one. The main disadvantage
is that it’s non-trivial to make all of this work.

5
CHAPTER 2
LITERATURE REVIEW

The unprecedented growth of the computer and the information technology industry is
demanding Very Large Scale Integrated ( VLSI ) circuits with increasing functionality
and performance at minimum cost and power dissipation. Continuous scaling of VLSI
circuits is reducing gate delays but rapidly increasing interconnect delays. A significant
fraction of the total power consumption can be due to the wiring network used for clock
distribution, which is usually realized using long global wires.

Furthermore, increasing drive for the integration of disparate signals (digital, analog, RF)
and technologies (SOI, SiGe, GaAs, and so on) is introducing various SoC design
concepts, for which existing planner (2-D) IC design may not be suitable.

Many companies are working on the 3-D chips ,including groups at Massachusetts
institute of technology (MIT),international business machines(IBM). Rensselar
Polytechnic and SUNY Albany are also doing research on techniques for bonding
conventional chips together to form multiple layers[5] .whichever approach ultimately
wins ,the multilayer chip building technology opens up a whole new world of design
.However ,the Santa Clara, California US based startup company matrix semiconductor
will bring the first multilayer chip to the market ,while matrix’s techniques will not likely
result in more computing power ,they will produce cheaper chips for certain applications,
like memory used in digital cameras , personal digital assistants ,cellular phones ,hand
held gaming devices ,etc .matrix has adapted the technology developed for making flat –
panel liquid crystal displays to build chips with multilayer of circuitry.

6
 Fig 3: 2.5D IC and 3D IC

The company’s first products will be memory chips called 3-D memory, for consumer
electronics like digital cameras and audio players. current flash memory cards for such
devices are rewritable but expensive .however the newly produced chips will cost ten
times less, about as much as an audio tape or a roll of film, but will only record
information once. The cost is so largely because the stacked chips contain the same
amount of circuitry as flash cards but use a much smaller area of the extremely expensive
silicon wafers that form the basis for all silicon chips. The chips will also offer a
permanent record of the images and sounds users record. The amount of computing
power the company can ultimately build in to its chips could be limited [6].the company
hopes to eventually build chips for cell phones, or low performance micro processors like
those found in appliances; such chips would be about one tenth as expensive as current
ones.The patent technology opens up the ability to build ICs in three dimensions- “up”
as well as “out” in the horizontal directions as in the case now with conventional chip
designs. The result is a ten fold increase in the potential no of bits on a silicon die,
according to the company .moreover, the 3-D circuits can be produced with todays
standard semiconductor materials, fab equipments and processors the 3-D memory will
be used in memory devices which will be marketed under well known brand names for
portable electronics devices, including digital cameras digital audio players, games,
PDAs and archival digital storage .the 3-D memory can also be used for pre recorded
content such as music, electronics books, digital maps, games, and reference guides.

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In single Si layer (2-D) ICs, chip size is continuously increasing despite reductions in
feature size made possible by advances in IC technology such as lithography and etching.
This is due to the ever growing demand for functionality and high performance, which
causes increased complexity of chip design, requiring more and more transistors to be
closely packed and connected. Small feature sizes have dramatically improved device
performance. The impact of this miniaturization on the performance of interconnect wire,
however, has been less positive. Smaller wire cross sections, smaller wire pitch, and
longer line to traverse larger chips have increase the resistance and capacitance of these
lines, resulting in a significant increase in signal propagation (RC) delay. As interconnect
scaling continues, RC delay is increasingly becoming the dominant factor determining
the performance of advanced IC’s.

As the entire 3D IC technology is focusing on wafer stacking, development efforts around

the globe are striving to resolve challenges associated with the silicon on insulator (SOI)
domain. The industry is also determined to establish an appropriate performance
guideline to enable it to choose between the ‘via first’ and the ‘via last’ approaches. The
ability to handle thin wafer, proper bonding technologies for heterogeneous bonding,
along with reducing the costs associated with the TSV process are some other critical
issues that need to be addressed. “Despite widespread industrial efforts in the 3D IC
domain, fundamental technology challenges continue to exist,” notes the analyst.
“However, the technology space is collaboratively striving to resolve them.” The need of
the hour is to establish clear performance metrics for all the evolving processes. For
instance, in the case of TSV, the industry has explored aspects, such as the cost of
operation (COO) of the process, but lacks a proper standard to gauge the performance of
a specific process established by a development group. This will help participants know
the real capabilities of their offering on a global platform. “The next decade of 3D IC
evolution will significantly rely on the industry’s capability to develop a performance
standard for the various segments of 3D IC domain.

8
 Fig 4: Various ICs types
3D integration suffers from the same problem as multi-chip modules (MCMs), IC boards,
and other integration schemes: one bad component can kill the system[7]. As more
components are integrated, the yield of the final product falls off exponentially. The
solution is to test components before integration, finding so called “known good die”
(KGD) parts. We propose this same approach to pre-bond test for 3D integration. At the
technology granularity, there is little challenge. Each layer is a complete, functional
design that can be tested in a normal planar method (as is done for MCMs). The only
challenge lies in the coexistance of probe pads for test and d2d vias for 3D integration.
But since these designs consume relatively few vias, there is room to spare, so this is
really just an engineering problem to be tackled on a per-design basis.

At 250 nm technology node, Cu with low-k dielectric was introduced to alleviate the
adverse effect of increasing interconnect delay.However,below 130nm technology node,
substantial interconnect delays would result in spite of introducing these new materials,
which in turn will severely limit the chip performance. Further reduction in interconnect
delay is not possible. This problem is especially acute for global interconnects, which
comprise about 10% of total wiring in current architectures[8]. Therefore, it is apparent
that material limitations will ultimately limit the performance improvement as technology
scales. Also, the problem of long lossy lines cannot be fixed by simply widening the metal
lines and by using thicker interlayer dielectric, since this will leas to an increase in the
number of metal layers. This will result in an increase in complexity, reliability and cost.

9
CHAPTER 3
DEVELOPMENT OF 3D ICS

Three-dimensional (3D) packaging is an integrated circuit (IC) packaging technique that

takes IC technology a step ahead in the Moore’s curve. With a lot spoken about difficulty
into progressing ahead along the Moore’s curve, there are a lot of development initiatives
in a number of components of the IC technology. 3D IC technology is definitely a promise
toward higher levels of miniaturization and integration, which focuses on portraying
advances in interconnect technologies and reducing interconnect delays. 3D IC
technologies promise significant increase of functionality and performance of
components by heterogeneous integration of materials, devices, and signals.
Interconnects and bonding technologies are two important aspects of development in the
evolution of 3D technologies. There are numerous efforts around 3D IC technologies and
with the amount of focus it is gaining, evolving technological solutions have to essentially
address critical challenges in this demanding space. The concept 3D IC was first
introduced at the package level, which involves simply stacking multiple semiconductor
chips and electrically connecting them using wires,. The industry then moved a step
forward in introducing what was called through silicon vias (TSV), in an attempt to
increase the number of feasible interconnects and enhance electrical performance. With
the introduction of TSV, a 3D package was slowly evolving to become a 3D IC
technology. TSV has in fact become the focus of the industry to an extent that the whole
evolution of 3D IC is centered on TSV. It is an acceptable fact that TSV evolved as a very
promising solution, but there are a few challenges restraining the industry from moving
forward in actually commercializing 3D IC with TSV[9]. Primarily, TSV demands for a
precise alignment of chips, which eventually requires a highly accurate alignment
controlled bonding technique or the usage of a large TSV pad. Secondly, TSV have not
evolved to be very cost-efficient. In the current scenario, it would not be wrong to say
that TSV is an expensive process. Industrial opinions cite that one must justify the need
for using 3D IC from an application perspective.

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 Fig 5 Three die stacks, each comprised of two layers using three possible bond
styles: (a) face-to-face, (b) face-to-back, and (c) back-to-back.

Figure 5 illustrates the general concept of 3D integration. Two die, previously

manufactured in any VLSI process, are bonded together with short, high-density die-to-
die (d2d) vias. These d2d vias come in two flavors, faceside and backside. Faceside vias,
manufactured on top of the metal interconnect layers, can be produced on a pitch of a few
hundred nanometers [10]. Backside vias, also called through silicon vias (TSVs), are
manufactured through the bulk silicon on a pitch of microns. To keep these TSVs small,
the bulk silicon must be thinned, usually with a CMP process, to a few tens of microns.
D2d vias on different die are then fused together to bond the die together [11]. A face-to-
face bond, Fig 5(a), is best, providing the shortest, highest density interface. However,
stack heights greater than two layers require the use of face-to-back or back-to-back
bonds, shown in Fig 5(b) and Fig 5(c) respectively. Once the stack is complete, normal
C4 solder bumps can be placed either on TSVs (Fig 5(a)) or on top of the metal layers as
in a traditional planar design.

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3.1 3D ARCHITECTURE

Three-dimensional integration to create multilayer Si ICs is a concept that can

significantly improve interconnect performance ,increase transistor packing density, and
reduce chip area and power dissipation. Additionally 3D ICs can be very effective large
scale on chip integration of different systems.

Fig 6: 3D IC Architecture

In 3D design architecture, and entire(2D) chips is divided into a number of blocks is

placed on separate layer of Si that are stacked on top of each other. Each Si layer in the

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3D structure can have multiple layer of interconnects(VILICs) and common global
interconnects.

3.1.1 Advantages of 3D architecture

The 3D architecture offers extra flexibility in system design, placement and routing. For
instance, logic gates on a critical path can be placed very close to each other using
multiple active layers. This would result in a significant reduction in RC delay and can
greatly enhance the performance of logical circuits.

1) The 3D chip design technology can be exploited to build SoCs by placing circuits
with different voltage and performance requirements in different layers.

2) The 3D integration can reduce the wiring ,thereby reducing the capacitance,
power dissipation and chip area and therefore improve chip performance.

3) Additionally the digital and analog components in the mixed-signal systems can
be placed on different Si layers thereby achieving better noise performance due
to lower electromagnetic interference between such circuits blocks.

4) From an integration point of view, mixed-technology assimilation could be made

less complex and more cost effective by fabricating such technologies on separate
substrates followed by physical bonding.

3.2 AREA AND PERFORMANCE ESTIMATION OF 3D ICs

Now we present a methodology that can be used to provide an initial estimate of the area
and performance of high speed logic circuits fabricated using multiple silicon layer IC
technology. The approach is based on the empirical relationship known as Rent’s Rule.

Rent’s Rule: It correlates the number of signal input and output (I/O) pins T, to the
number of gates N, in a random logic network and is given by the following expressions:

T=kNP -------------(i)

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Here k & P denote the average number of fan out per gate and the degree of wiring
complexity (with P=1 representing the most complex wiring network), respectively, and
are empirically derived as constants for a given generation of ICs.

3.2.1 2-D and 3-D wire length distributions

The wire-length distribution can be described by i(l),an interconnect density functions

(i.d.f), or by I(l), the cumulative interconnect distribution function (c.i.d.f) which gives
the total number of interconnects that have length less than or equal to l (measured in gate
pitches) and is defined as

l
I(l)=  i(x)dx -----------(ii)
1

Where x is a variable of integration representing length and l is the length of the

interconnect in gate pitches. The derivation of the wire-length distributed in a Ic is based
on Rent’s Rule. To derive the wire length distribution I(l) of an integrated circuit, the
latter is divided up into N logic gates, where N is related to the total number of transistor
Nt in an integrated circuit by N=Nt/O where O is a function of the average fan-in(f.i0
and fan-out(f.o). The gate pitch is defined as the average separation between the logic
gates and is equal to sqt(Ac/N) where Ac is the area of the chip.

In order to derive the complete wire-length distribution for a chip, the stochastic wire-
length distribution of a single gate must be calculated.

Fig 7: gates block

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The number of connections from the single logic gate in Block A to all other gate that are
located at a distance of l gate pitches is determined using Rent’s Rule. The gates shown
in the figure are grouped into three distinct but adjacent blocks(A,B&C), such that a
closed single path can encircle one, two or three of these blocks. The number of
connections between Block A and Block C is calculated by conserving all I/O terminals
for blocks, A, B, and C, which states that terminals for blocks A, B, and C, are either
interlock connections or external system connections. Hence, applying the principle of
conservation of I/O pins to this system of three logic blocks, shown gives

TA + TB + TC = TA to C + TA to B + TB to C + TABC …………….(iii)

Where TA, TB, TC are the number of I/O blocks A, B, and C respectively. TA to C , TA to B,
TB to C are the number of I/Os between blocks A and C, blocks A and B, and between
blocks B and C, respectively. [12]TABC represents the number of I/Os for the entire
system comprising of all three blocks. From conservation of I/Os, the number of I /Os
between adjacent blocks A and B, and between adjacent blocks A and B and between
adjacent blocks B and C can be expressed as

TA to B = TA + TB - TAB ……………………..…(iv)

TB to C = TB + TC – TBC ..………………………(v)

Substituting (iv) and (v) into (iii) gives

TA to C = TAB + TBC – TB - TABC ………………………(vi)

Now the number of I/O pins for any single block or a group of blocks can be calculated
using Rent’s Rule. If we assume that N, N, and N are the number of gates in blocks A,
B, and C, respectively, then it follows that

TB = k (NB)P ………………………(vii)

TAB = k(NA + NB)P ……..………………..(viii)

TBC = k(NB + NC )P ……….………………(ix)

TABC = k(NA + NB +NC)P ……………………….(x)

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Where N = NA + NB + NC. Substituting (vii) – (x) into (vi) gives

TA to C = k [( NA + NB)P – (NB)P + (NB + NC)P – (NA + NB + NC)P] ……..(xi)

The number of interconnects between Block A and Block C (IA to C) is determined using
the relation

IA to C = αk (TA to C)

Where α is related to the average fan out (f.o.) by

α = f.o. / (1+f.o.)

Applying Rent’s Rule to all the layers, we have

n
T=kNP = (  Ti) – Tint = nk(N/n)P - Tint
i =1

Here, T is the number of I/Os for the entire design, Ti represents the number of I/O ports
connecting n layers. Hence it follows that

Tint = n (1- nP-1) k (N/n)P and

Text,i = Ti – Tint/n = knP-1 (N/n)P

Here, Text,i , is the average of I/O ports per layer.

3.2.2 Estimating 2-D and 3-D chip area

In integrated circuits that are wire-pitch limited in size, the area require by the wiring
network is assumed to be much greater than the area required by the logic gates. For the
purpose of minimizing silicon real estate and signal propagation delays, the wiring
network is segmented into separate tiers that are physically fabricated in multiple layers.

An interconnect tier is categorized by factors such as metal line pitch and cross-section,
maximum allowable signal delay and communication mode (such as intra block, or inter
block). A tier can have more than one layer of metal interconnects if necessary, and each
tier or layer is connected to the rest of the wiring network and the logic gates by vertical
vias. The tier closest to the logic devices (referred to as the local tier) is normally for
short distance intra block communications.

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Metal lines in this tier will normally be the shortest. They will also normally have the
finest pitch. The tier furthest away from the device layer (referred to as global tier) is
responsible for long distance across chip inter block communications, clocking and
power distribution. Since this tier is populated by the longest of wires, the metal pitch is
the largest to minimize signal propagation delays. A typical modern IC interconnects
architecture will define three wiring tiers: local, semi-global, and global. The semi-
global tier is normally responsible for inter block communications across intermediate
distances.

Fig 8: Wiring tiers

The area of the chip is determined by the total wiring requirement. IN terms of gate pitch,
the total area required by the interconnect wiring can be expressed as

Arequired = √Ac (PlocLtotal_loc+PsemiLtotal_semi+PglobLtotal_glob)/N

Where,

Ac Chip area ;

N number of gates;

Ploc local pitch;

Psemi semi global pitch;

Pglobal global pitch;

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 Ltotal_loc total lengths of local interconnects;

Ltotal_semi total length of semi global interconnects;

Ltotal_glob total length of global interconnects;

The total interconnects length for any tier can be found by integrating the wire-length
distribution within the boundaries that define the tier. Hence it follows that

Ltotal_loc= X ∫ li (l) dl

Ltotal_semi=X ∫ li (l) dl

Ltotal_glob = X ∫ li (l) dl

Where X is a correction factor that converts the point –to – point interconnect length to
wiring net length (using a linear net model, X=4/(f.o. + 3)

3.2.3 Two active layer 3-D circuit performance

Here, VILICs are assumed to consume negligible area, interconnect line width is
assumed to equal half the metal pitch at all times, and the total number of metal layers
for 2-D and 3-D case was conserved. A key assumption for the geometrical construction
of each tier of the multilevel interconnect network is that all cross sectional dimensions
are equal within that tier.

As Psemi increase from its value at the minimum Ac the semi global and global pitches
increase resulting in a larger wiring requirement and thus a larger Ac. Furthermore, as
Psemi increases, even longer wires can now satisfy the maximum delay requirement in the
semi global tier. These results in global wires to be rerouted to the semi global tier, which
in turn will require greater chip area. Under such circumstances, the semi global tier
begins to dominate and determine the chip area. Conversely, as Psemi decreases from its
value at the minimum Ac, the longer wires in the semi global tier no longer satisfy the
maximum delay requirement of that tier and they need to be rerouted to the global tier
where they can enjoy a larger pitch. The populations of wires in global tiers increases and
since these wires have a large cross section they have a greater area requirement. Under
such circumstances the global tier begins to dominate and determine the chip area.The
curve for the 3-D case has a minimum similar to the one obtained for the 2-Dcase.it can

18
be observed that the minimum chip area for the 3-D case is about ≈30% smaller than that
of the 2-D case. Moreover, since the total wiring requirement is reduced, the semi global
tier pitch is reduced for the 3-Dchip. The significant reductions in chip area demonstrated
by the 3-D results are a consequence of the fraction of wires that were converted from
horizontal in 2-D to vertical VILICs in 3-D. it is assumed that the area required by VILICs
is negligible.

These results demonstrate, with given assumptions, that a 3-D IC can operate at the same
performance level, as measured by the longest wire delay, as its 2-D counterpart while
using up about 30% less silicon real estate. However, it is possible for 3-D ICs to achieve
greater performance than their 2-Dcounterparts by reducing the interconnect impedance
at the price of increased chip area as discussed next.

Increasing Chip Area and Performance 3-D IC performance can be enhanced to exceed
the performance of 2-D ICs by improving interconnect delay. This is achieved by
increasing the wire pitch, which causes a reduction in the resistance. The effect of
increasing psemi and pglobal on the operating frequency and Ac.This illustrates how the
optimum semi global pitch (i.e., the psemi associated with the minimum Ac) increases to
obtain higher operating frequencies. Also, as the semi global tier pitch increases, chip
area and, therefore, interconnect length also increases. However, we can see that the
increase in chip area still remains well below the area required for the 2-D case[13]. The
figure also helps defines a maximum – performance 3-D chip – a chip with the same area
as the corresponding 2-D chip, which can be obtained by increasing the semi global pitch
beyond that for the 4-GHz case.

Two scenarios are considered 1) global pitch is increased to match the global pitch for
the 2-d case and 2) global pitch is increased to match the chip area (footprint) for the 2-d
case. Note that the delay requirements sets a maximum values of interconnect length are
given tier. Therefore, as interconnect lengths are increased, lines which exceed this
maximum length criterion for that particular tier need to be rerouted on upper ties.
Beyond the maximum performance point for the 3-d chip, the performance gain becomes
increasingly smaller in comparison to the decrease in performance resulting from the
increase in chip area or reconnect delay. Furthermore, as the semi global wires need to
be rerouted on the global tiers, which eventually leads to overcrowding of the global tier.

19
Any further increases in the wiring density in the global tier forces a reduction in the
global pitch.

3.2.4 Effect of increasing number of silicon layers

As the number of silicon layers increases beyond two, the assumption that all interlayer
interconnects (ILICs) are vertical and consume negligible area becomes less tenable. The
area used up by these horizontal ILICs can be estimated from their total length and pitch.

The decrease in interconnect delay becomes progressively smaller as the numbers of

active layers increase. This is due to the fact that the area required by ILICs begins to
offset any area saving due to increasing the number of active layers.

3.2.5 Effect of increasing the number of metal layers

It is likely that there are local and semi global tiers associated with every active layer,
and a common global tier is used . This would result in an increase in the total number of
metal layers for the 3-D case. The effect of using 3-D case. The effect of using 3-D ICs
with constant metal layers and the effect of employing twice the number of metal layers
as in 2-D are summarized in the figure 9.

Fig 9: The effect of using 3-D ICs with constant metal layers

It can be observed that by using twice the number of metal layers the performance of the
3-D chip can be increased by an additional amount of 35% as compared to the 3-d chip

20
with the same total number of metal layers as in 2-d . It can be observed that for the more
aggressive technologies , the decrease in interconnect delay from 2-D to 3-D case is less
impressive. This indicates that more than two active layers are possibly needed for those
advanced nodes. The figure also shows the impact of moving only the repeaters to the
second layer Si layer . It can also be observed that for more aggressive technologies , the
decrease in interconnect delay from 2-D to 3-D case is less impressive [14].This indicates
that more than two active layers are possibly needed for those advanced nodes.

3.2.6 Optimization of interconnect distribution

In estimating chip area, the metal requirement is calculated from the obtained wire-length
distribution. The total metallization requirement is appropriately divided among the
available metal layers in the corresponding technology . Thus each tier , the local , the
semi global and the global has three metal layers . the resulting area of most densely
packed tier determines the chip area.

Consequently, higher tier are routed within a larger than required area . An optimization
for this scenario is possible by rerouting some of the local wires on the semi global tier
and the latter on the global , without violating the maximum allowable Length ( or delay
) per tier. This is achieved by reducing the maximum allowed interconnect length for the
local and semi global tiers. Minimum chip area will achieved when all the tiers are equally
congested. The 2-D chip area is seen to reduce by 9% as a result of this optimization is
also applied to applied to 3-D ICs .

3.3 CHALLENGES FOR 3-D INTEGRATION

3.3.1 Thermal issues in 3-D ICs

An extremely important issue in 3-D ICs is heat dissipation. Thermal effect s are already
known to significantly impact interconnected /device reliability and performance in high-
performance 2-D ICs. The problem is expected to be exacerbated by the reduction in chip
size, assuming that same power generated in a 2-D chip will now be generated in a smaller
3-D chip, resulting in a sharp increase in the power and density Analysis of thermal
problems in 3-D circuits is therefore necessary to comprehend the limitations of this
technology and also to evaluate the thermal robustness of different 3-D technology and
design options.

21
It is well known that most of the heat energy in integrated circuits arises due to transistor
switching. This heat energy is typically conducted through the silicon substrate to the
package and then to the ambient by a heat sink .With multi layer device designs, devices
in the upper layer will also generate a significant fraction of the heat .Furthermore, all the
active layers will be insulated from each other by layers of dielectrics (LTO, HSQ,
polyamide, etc.) which typically have much lower thermal conductivity than Si .Hence
,the heat dissipation issue can become even more acute for 3-D ICs and can cause
degradation in device performance ,and reduction in chip reliability due to increased
junction leakage, electro migration failures ,and by accelerating other failure
mechanisms.

3.3.2 Reliability issues in 3-D ICs

Three dimensional IC s will possibly introduce some new reliability problems. These
reliability issues may arise due to the electro thermal and thermos-mechanical effects
between various active layers and the interfaces between the active layers, which can also
influence existing IC reliability hazards such a electro migration and chip performance.
Additionally, heterogeneous integration of technologies using 3-d architecture will
increase the need to understand mechanical and thermal behavior of new material of new
material interfaces and thin film material thermal and mechanical properties.

3.4 MANUFACTURING METHODS OF 3-D ICs

3.4.1 Beam recrystallization

A very popular method of fabricating a second active layer (Si) on top of an existing
substrate (oxidized Si wafer )is to deposit polysilicon and fabricate thin film transistors
(TFT). To enhance the performance of such transistors ,an intense laser or electron beam
is used to induce recrystallisation of the polysilicon film to reduce or even eliminate most
of the grain boundaries.

22
 Fig 10 : Beam recrystallization

Advantage

1. MOS on transistors fabricated on polysilicon exhibit very low surface mobility

values [of the order of 10 cm/Vs].

2. MOS transistors fabricated on polysilicon have high threshold voltages (several

volts) due to the high density of surface states (several 10 cm ) present at the grain
boundaries.

Disadvantage

1. This technique, however, may not be very practical for 3-D devices because of
the high temperature involved during melting of the polysilicon.

2. Difficulty in controlling the grain size variations.

3.4.2 Silicon epitaxial growth

Another technique for forming additional Si layers is to etch a hole in a passivated wafer
and epitaxially grow a single crystal Si seeded from open window in the ILD. The Si
crystal grows vertically and then laterally to cover the ILD.

23
 Fig 11: Epitaxial growth of 3D ICs

Advantage:

1. The quality of devices fabricated on these epitaxial layer can be as good as those
fabricated underneath on the seed wafer surface, since the grown layer is single
crystal with few defects.

Disadvantage:

1. The high temperatures involved in this process cause significant degradation in the
quality of devices on lower layers.

3.4.3 Processed wafer bonding

An attractive alternative is to bond two fully processed wafers on which devices are
fabricated on the surface ,including some interconnects, such that the wafers completely
overlap.Interchip vias are etched to electrically connect both wafers after metallization
and prior to the bonding process at 400 degree Celsius. For applications where each chip
is required to perform independent processing before communicating with it’s neighbor ,
this technology can prove attractive .

Advantage

24
 1. Devices on all active levels have similar electrical properties.

2. Since all chips can be fabricated separately and later bonded ,there is independence
of processing temperature.

Disadvantage

1. The lack of precision restricts the inter-chip communication to global metal lines

3.4.4 Vertical interlayer interconnect technology options

There is direct relation between improved chip performance and increased utility of
VILICs. It is therefore important to understand how to connect different active layers
with a reliable and compatible process. Upper layer processing needs to be compatible
with metal lines underneath connecting lower layer devices and metal layers. With Cu
technologies, this limits the processing temperatures to <450 c for upper layers.
Otherwise , Cu diffusion through barrier layers , and the reliability and thermal stability
of material interfaces can degrade significantly. [15]Tungsten is a refractory metal that
can be used to withstand higher processing temperatures, but it has higher resistivity.
Current via technology can also be employed to achieve VILIC functionality. The
underlying assumption here requires that interlayer gates are interconnected using regular
horizontal metal wires and vias, while interlayer interconnects can be VILICs connecting
the wiring network for each layer.

Recently, interlayer (VLIC)metallization schemes for 3-d ICs have been demonstrated
using direct wafer bonding. These techniques are based on the bonding of two wafers
with their active layers connected through vias ,which serve as VILICs .One method is
based on the bonding of a thinned top wafer to a bottom wafer with a organic adhesive
layer of polyamide in between.

Interchip vias are etched through the ILD(inter level dielectric ),the thinned top silicon
wafer and through the cured adhesive layer ,with an approx depth of 20 m prior to the
bonding process .the interconnect chip via made of chemical wafer depositor (CVD).Tin
liner and CVD-W plug provides a vertical interconnect (VILIC)between the upper most
metallization levels of both layers . the bonding between the two wafers is done using a
flip-chip bonder with split beam optics at a temperature of 400 degree Celsius

25
A second technique realizes on the thermo compression bonding between the metal parts
in each wafer. In this method, Cu-Ta pads on both wafers save as electrical contacts
between the interchips via on the top thinned silicon wafer and the upper most
interconnects on the bottom silicon wafer. The Cu-Ta pads can also function as small
bond pads for wafer bonding. Additionally, dummy metal patterns can be made to
increase the surface area for wafer bonding. The Cu-Ta bilayer pads with a combined
thickness of 700 nm are fused together by applying a compressive force at 400 degree
Celsius. This technique offers the advantage of a metal –metal interface that will lower
the interface thermal resistance between the two wafers (and, hence, provide better
conduction) and can be beneficial as a partial ground plane for lowering the
electromagnetic effects.

3.5 APPLICATION
Portable electronic digital cameras, digital audio players, PDAs, smart cellular phones,
and handheld gaming devices are among the fastest growing technology market for both
business and consumers. To date, one of the largest constraints to growth has been
affordable storage, creating the marketing opportunity for ultra low cost internal and
external memory. These applications share characters beyond rapid market growth.

Portable devices all require small form factors ,battery efficiency, robustness, and
reliability. Both the devices and consumable media are extremely price sensitive with
high volumes coming only with the ability to hit low price points. Device designers often
trade application richness to meet tight cost targets. Existing mask ROM and NAND flash
non volatile technology force designers and product planners to make the difficult choice
between low cost or field programmability and flexibility. Consumers value the
convenience and ease of views of readily available low cost storage. The potential to
dramatically lower the cost of digital storage weapons many more markets than those
listed above. Manufacturers of memory driven devices can now reach price points
previously inaccessible and develop richer, easier to use products.

26
CHAPTER 4

CONCLUSION AND FUTURE WORKS

4.1 CONCLUSION

This paper reviews various 3D integration technologies, addresses key integration

challenges of the 3D ICs, and describes several optical and electrical test structures
fabricated to verify 3D IC process readiness. A critical need exists for a reliable layer-to-
layer alignment accuracy; several techniques for alignment and overlay measurements
have been presented. The most aggressive alignment tolerance (0.18 lm) for 3D ICs can
be achieved by implementing a transparent substrate, high-quality oxide fusion bonding,
and bow compensation methods. Further process improvement of alignment across the
wafer is needed.

We have described issues related to the fabrication of small, high-aspect-ratio vias

suitable for high-density connections between layers in a 3D IC. Using 0.13-lm MOSFET
and ring oscillator circuits, it was shown that BEOL CMOS process techniques can be
used to fabricate copper-filled, high-aspect-ratio (.8:1) trenches, providing the capability
to create the smallest (sub-lm-size) vias as wafer-to-wafer connections. Electrical
structures for testing the reliability of the connecting vias and bonding interface have been
reviewed. Test structures for characterizing both self- and spread-heating effects in 3D
ICs have also been described. This work is a major step toward the realization of true
wafer-level 3D integration of high-performance CMOS devices.

4.2 FUTURE WORKS

Matrix is working with partners including Microsoft Corp, Thomas Multimedia, Eastman
Kodak and Sony Corp. three product categories are planned: bland memory cards: cards
sold preloaded with content, such as software or music ; and standard memory packages,
for using embedded applications such as PDAs and set-top boxes .

27
Thomson electronics, the European electronic giant, will begin to incorporate 3-D
memory chips from matrix semiconductor in portable storage cards, a strong endorsement
for the chip start –up.

Thomson multimedia will incorporate the 3-D memory in memory cards that can be used
to store digital photos or music. Although the cards plug into cameras Thomson is also
working on card readers that will allow consumers to view digital photos on a television.
The Thomson /matrix cards price makes the difference from completing flash cards from
Sony and Toshiba .the 64 MB Thomson card will cost about as much as camera film does
today. to further strengthen the relationship with film ,the cards will be sold under the
name Technicolor Digital Memory Card.

Similar flash memory cards from other companies cost around Rs.1900 or more-though
consumers can erase and rerecord data on them, unlike the matrix cards. As a result of
their price, consumers buy very few of them. Thomson, by contrast , expects to market
its write-once cards in retail outlet such as Wal-Mart.

The primary process challenges related to thermal budget constraint, high quality silicon
growth, and contamination are discussed, including existing approaches to these issues.
At the design-level, important results on design automation, thermal integrity, and design
for-test are provided with emphasis on unique MONO3D characteristics. Three specific
applications that can potentially benefit from MONO3D technology are also presented.

Lack of experimental results is a primary limitation related to most of the existing work
on MONO3D ICs. Similarly, the fabrication-level constraints and design-level
tools/methodologies are not sufficiently coupled, thereby making these methods less
applicable. A stronger interaction between fabrication and design is anticipated and
required in the future, as the MONO3D process matures and more opportunities arise for
fabrication. These experimental results can also facilitate the detailed characterization
and modeling of inter-tier process variations, which remain a primary concern for
MONO3D technology. Existing cost models for MONO3D circuits can also benefit from
these results. In the mean time, cross-layer design methods that go beyond physical
design automation will enable system-level design space exploration while
simultaneously considering important design objectives such as efficiency, performance,
and thermal integrity.

28
APPENDIX

Fig 12A: Comparison between 2D ICs and Monolithic 3D ICs on footprint

Fig 13A: Comparison of a Monolithic 3D-IC and a 2D-IC at the same technology node

29
 Figure 14A : Costing of 3D ICs

Fig 15A : 3D-ICs Dynamic thermal analysis

30
REFERENCES

[1]B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D.

McCauley, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen,
and C. Webb. Die Stacking (3D) Microarchitecture. In Proceedings of the 39th
International Symposium on Microarchitecture, 2006.

[2] Shamik Das, Anantha Chandrakasan, and Rafael Reif. Design Tools for 3-D
Integrated Circuits. In Asia South Pacific Design Automation Conference (ASP-DAC),
pages 53–56, 2003.

[3] Li Jiang, Lin Huang, and Qiang Xu. Test Architecture Design and Optimization for
Three-Dimensional SoCs. In Proceedings of the Design Automation and Test in Europe,
2009.

[4] Hsien-Hsin S. Lee and Krishnendu Chakrabarty. Test Challenges for 3D Integrated
Circuits. To appear in IEEE Design and Test of Computers, Special Issue on 3D IC
Design and Test, Sep/Oct 2009.

[5] G. H. Loh, Y. Xie, and B. Black. Processor Design in Three-Dimensional Die-

Stacking Technologies. IEEE Micro, May/June 2007.

[6] R. Patti, M. Hilbert, S. Gupta, and S. Hong. Techniques for producing three
dimensional integrated circuits with high density interconnect. In International VLSI
Multilevel Interconnection Conference, 2004.

[7] F. Li, C. Nicopoulos, T. Richardson, Y. Xie, N. Vijaykrishnan, and M. Kandemir.

Design and Management of 3D Chip Multiprocessors using Network-in-Memory. In
Proceedings of the International Symposium on Computer Architecture, 2006.

31
[8]Xiaoxia Wu, Paul Falkenstern, and Yuan Xie. Scan Chain Design for Three-
dimensional Integrated Circuits (3D ICs). In Proceedings of the International Conference
on Computer Design, 2007.

[9]Suntharalingam et al, “Megapixel CMOS Image Sensor Fabricated in

ThreeDimensional Integrated Circuit Technology”, ISSCC Digest of Technical Papers,
Feb. 2005, pp. 356-357.

[10] V. N. Johnson, J. Jozwiak, and A. Moll, “Through Wafer Interconnects on Active

pMOS devices,” IEEE Workshop on Microelectronics and Electron Devices, 2004, pp.
82-84.

[11] R. M. Lea et al, “A 3-D Stacked Chip Packaging Solution for Miniaturized Massively
Parallel Processing,” IEEE Trans. On Advanced Packaging, vol. 22, no. 3, Aug. 1999,
pp. 424-432.

[12] S. Mick, J. Wilson, and P. Franzon, “4 Gbps High-Density AC Coupled

Interconnection,” IEEE Custom Integrated Circuits Conf., May 2002, pp. 133-140.

[13] T. Kim, J. Nath, J. Wilson, S. Mick, P. Franzon, M. Steer and A. Kingon, “A High
K Nanocomposite for High Density Chip-to-Package Interconnections”, Materials
Research Society Symposium Proceedings, Vol. 833, 2005.

[14] N. Miura, D. Mizoguchi, M. Inoue, H. Tsuji, T. Sakurai and T. Kuroda, “A 195Gb/s

1.2W 3D-Stacked Inductive Inter-Chip Wireless Superconnect with Transmit Power
Control Scheme,” ISSCC Digest of Technical Papers, Feb. 2005, pp. 264-265.

[15] S. Das, A. Chandrakasan, and R. Reif. “Design Tools for 3-D Integrated Circutis,”
Proc. of the Asia and South Pacific Design Automation Conference, Jan. 2003, pp. 53-56

[16] J. Stine, The Illinois Institute of Technology System-on-Chip Design Flow, available
online at http://www.ece.iit.edu/~vlsi/scells.

32
[17] C. C. Liu et al., “High-performance integrated fan-out wafer level packaging (InFO-
WLP): Technology and system integration,” in Proc. Int. Electron Devices Meeting,
2012, pp. 14.1.1–14.1.4.

[18] M. A. Kabir, D. Petranovic, and Y. Peng, “Coupling extraction and optimization for
heterogeneous 2.5D chiplet-package co-design,” in Proc. IEEE/ACM Int. Conf. Comput.
Aided Design, 2020, pp. 1–8.

[19] M. Hutner, R. Sethuram, B. Vinnakota, D. Armstrong, and A. Copperhall, “Special

session: Test challenges in a chiplet marketplace,” in Proc. IEEE VLSI Test Symp., 2020,
pp. 1–12.

[20] R. Wang and K. Chakrabarty, “Tackling test challenges for interposerbased 2.5-D
integrated circuits,” IEEE Design Test, vol. 34, no. 5, pp. 72–79, Oct. 2017.

[21] J.-S. Kim et al., “A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 × 128 I/Os
using TSV based stacking,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 107–116, Jan.
2012.

[22] W. Gomes et al., “8.1 lakefield and mobility compute: A 3D stacked 10nm and
22FFL hybrid processor system in 12×12mm2, 1mm package-on-package,” in Proc.
IEEE Int. Solid State Circuits Conf., 2020, pp. 144–146

33