PAF-KARACHI INSTITUTE OF ECONOMICS AND TECHNOLOGY

College of Engineering

DIGITAL LOGIC FUNDAMENTALS

Semester: ____________second_____ Date of Experiment:
__________________
Student nameAimen Mustaqim _________ Faculty Signature:
____________________
Student ID: _______10967
___________ Remarks/Comments: __________________

L.E FINAL LAB EXAM (Digital Logic Fundamentals)

PLO1 – Engineering Knowledge C1 – Recall

PLO’s PLO4 – Investigation Bloom’s P3 – Guided Response

PLO8 – Ethics Taxonomy P2 – Set
PLO9 – Individual and Teamwork A3 – Assume responsibility

ASPECTS OF ASSESSMENT
Excellent Average Poor Marks
CLO’s Aspects of Assessments
(75-100%) (50-75%) (<50%) Obtained
Complete understanding of Understand logics(s) Student lacks clear
Recall: Recall the associated
CLO1 the concepts / actively concepts / participates less understanding of logic
concepts form theory
participate during in class / read conditioning fundamentals/ Unable to
PLO1 regarding various digital
lecture /read & interpret circuits but unable to read and interpret signal
10% logics and signal
signal Conditioning Circuits. interpret accurately. conditioning circuit
Conditioning Circuits.
completely.
Experimental Validation Student efficiently observe / Observe the IC behavior by Logic / Circuit working is
Observe the working of validate working by following schematic validate accurately only
various Logics, and their following Circuit diagram. diagram but with minor with help from the
CLO4 calibration errors. teacher.
PLO4 Accurately does data analysis Conducts computations Able to conduct analysis
18% Data Analysis
/ plotting /correlate with minor error; and on collected data, no
Data Handling / experimental results to reasonably correlates results attempt to correlate
Calculations / Plotting and expected theoretical values. to known theoretical values. experimental results with
Experimental Verifications. known theoretical values.
CLO6 Lab Safety Properly handle Properly handle lab Moderate level lab handling Minor or no safety
PLO8 lab infrastructure/ safety equipment & obey safety and safety measurements measurements has been
1% precautions measures. considered.
Proactively work with other Worked well with team but Very little, if any,
CLO7 Team Work Completion of team members to complete did not offer much positive contributions to group
PLO9 Lab tasks with proper team assigned tasks. feedback. and less contribution in
1% work and contribution. completion of overall lab
tasks.
Total Marks: 30
Q1: MCQ’s (CLO_1) (10 Marks)

Q1: Design a schematic of the given Boolean expression. (CLO_4) (6 Marks)

__________________ _____________
[( A+C + D)⋅(C ⊕ D)] ⋅¿ + ( D ⋅C ) }⊕ {¿) ⋅ D }¿ (CLO_4) (6 Marks)

Q2: Drive the Boolean expression of the given schematic.

Q3: Calculate the mark-time, space-time and duty cycle to design a Astable circuit in order to produce the
square wave while considering the following conditions: (CLO_4) (6 Marks)

1. The first 3 digits of your student id should be the frequency (in “Hz”).
2. The last 2 digits should be the value of capacitor (in “µF”).
3. The middle three digit of your student id should be the value of R1 (in “Ω”)

Example:

Student ID = 12345

Frequency = 123Hz
Capacitance = 45µF
Resistance (R1) = 234 Ω
Safety (CLO_6) (1
Marks)
Individual/Teamwork (CLO_7) (1
Marks)