IMPLEMENTATION AND INVESTIGATION OF A

FULL ADDER DESIGN FOR LOW POWER AND

REDUCED DELAY
A PROJECT REPORT

Submitted by

AASTHA SHARMA (21BEC1102)

SATYAM SINHA (21BEC1149)

SUBHADEEP MONDAL (21BEC1155)

ABUTALIB KHAN (21BEC1168)

ASHISH KUMAR RAI (21BEC1173)

In partial fulfilment for the award of the degree of

BACHELOR OF ENGINEERING

IN
ELECTRONICS AND COMMUNICATION ENGINEERING

Chandigarh University

NOV,2023
 BONAFIDE CERTIFICATE

Certified that this project report “IMPLEMENTATION AND

INVESTIGATION OF A FULL ADDER DESIGN FOR LOW POWER
AND REDUCED DELAY” is the bonafide work of “AASTHA SHARMA,
SATYAM SINHA, SUBHADEEP MONDAL, ABUTALIB KHAN, ASHISH
KUMAR RAI” who carried out the project work under my supervision.

SIGNATURE SIGNATURE

Dr. ASHUTOSH TRIPATHI Dr. TRIPTI SHARMA

HEAD OF THE DEPARTMENT SUPERVISOR

PROFESSOR

ECE ECE

Submitted for the project viva-voice examination held on

INTERNAL EXAMINER EXTERNAL EXAMINER

 ACKNOWLEDGEMENT

CHANDIGARH UNIVERSITY

NOV 28,2023

We would like to express our gratitude towards Dr. Tripti Sharma and our honourable
HOD Prof. Ashutosh Tripathi, of Chandigarh University for their support in
accomplishment of our project on DESIGN OF IMPLEMENTATION AND
INVESTIGATION OF A FULL ADDER DESIGN FOR LOW POWER AND
REDUCED DELAY

I would like to extend my deep appreciation to my group members, without their

support and coordination we would not have been able to complete this project.
 TABLE OF CONTENT

List of Figures i
Abbreviations ii
Graphical Abstract iii
Abstract iv
IEEE/IEC Standards 1
Sustainable Development 2
Goals(SDGs)

Chapter-1 3-10
Introduction 3
Need Identification 5
1.2 Identification of problems 6
1.3 Identification of Tasks 7
1.4 Timeline 9
1.5 Organization of Report 10
Chapter-2 11-25
Literature Review 11-24
2.1 Timeline of the Reported Problem 11
2.2 Bibliometric Analysis and solution from 12
Literature
2.3 Review Summary 23-24
2.4 Problem Definition 24
2.5 Goals/Objectives 25
Chapter3 26-28
Design Flow/Process 26-27
3.1 Problem Formulation and Objectives 26
3.2 Research Methodology 27
Chapter-4 29-43
Implementation, Result Analysis and Validation 30-42
4.1 Proposed Full adder design 29-30
4.2 Calculation Parameters 31-39
4.2.1 Low Power 32-37
4.2.2 Reduced Delay 37-39
4.3 Comparison and Analysis 40-42
Chapter-5 43
Conclusion and Future Scope 43
5.1Conclusion 43
5.2 Future Scope 43
6.References 46-47
7.Appendix 48-58
 LIST OF FIGURES

Fig 1.1 Block diagram and logic Circuit 4

Fig 1.2 Project Timeline 9
Fig 2.1 10-transistor Full Adder Cell 12
Fig 2.2 10-transistor adder cell 13
Fig 2.3 The 10-transistor low-power 1-bit adder 14
Fig 2.4 Conventional 10T full adder design 15
Fig 2.5 10 transistor adders 15
Fig 2.6 10T full adder 16
Fig 2.7 Circuit diagram of the proposed full adder 17
Fig 2.8 Proposed 10 Transistor Full Adder 18
Fig 2.9 10T MGDI Full Adder 19
Fig 2.10 10T Full Adder 20
Fig 2.11 Schematic structure of Full Adder with two 21
logic styles
Fig 2.12 Low power hybrid full adder 23
Fig 2.13 Optimal 10 transistor full adder circuit 23
Fig 3.1 Research Methodology 27
Fig 4.1 Design 1 29
Fig 4.2 Design 2 30
Fig 4.3 Output of Design 1 30
Fig 4.4 Input voltage 32
Fig 4.5 Transient analysis 32
Fig 4.6 Outputs 33
Fig 4.7 Give the input values 33
Fig 4.8 Output in Pulse form 34
Fig 4.9 Save the Program 34
Fig 4.10 Direct plot form 35
Fig 4.11 Power for 1v 35
Fig 4.12 Calculate Powe r 37
Fig 4.13 Final output 36
Fig 4.14 Functional panel 37
Fig 4.15 Giving inputs 38
Fig 4.16 Reduced delay for 0.9v 38
 LIST OF TABLES

Table 2.1 Comparison of papers 23-24

Table 4.1 Truth table of Full Adder 31

Table 4.2 Power for different voltages 37

Table 4.3 Reduced delay for different 39

voltages
Table 4.4 Power Delay Product For 39
proposed design
Table 4.5 Power Consumption varying VDD 40

Table 4.6 Delay varying VDD 41

Table 4.7 Power Delay Product varying 42

VDD
 ABBREVIATIONS

1. IEEE = Institute of Electrical and Electronics Engineers

2. IEC = International Electrotechnical Commission

3. SDG = Sustainable Value Goals

4. VLSI = Very Large-Scale Integration

5. IOT = Internet of Things

6. ALU = Arithmetic logic unit

7. CMOS = Complementary Metal-Oxide-Semiconductor

8. PDAP = Power Delay and Area product

9. TSMC = Taiwan Semiconductor Manufacturing Company Limited

10. PDP = Power-delay Product

11. GDI = Gate diffusion input

12. MVT= Multi Threshold Voltage Technique

13. CPL= Complementary Pass-Transistor Logic

14. EDP= Electronic Data Processing

15. MGDI= Modified Gate Diffusion Input

16. EDA= Electronic design automation

17. OLPFAD= Optimal Low Power Full Adder Design

18. DFEFA=Dynamic Frequency and Energy Efficient Full Adder

19. DTLPCFA=Differential Threshold Level Pass-Transistor Full Adder

20. DPEHFA=Differential Pass-Transistor Full Adder with Enhanced Efficiency

 GRAPHICAL ABSTRACT
INTODUCTION
In this project, we are
developing a new design
for a full adder, a crucial
component in many digital
devices. The aim is to
create a design that is both
power-efficient and fast. To
achieve this, we’re using a
unique design that requires
only ten transistors, fewer
than what’s typically used.
This reduction not only
decreases power
consumption but also
enhances the speed of
operation.
We’re utilizing a specific
type of technology known
as CMOS to implement
this design. The
performance of the design
is then thoroughly
evaluated in terms of its
power efficiency and
speed. The results of this
project could have
significant implications for
the future of digital device
design, particularly for
battery-operated devices
where power efficiency is
critical. By creating a more
efficient full adder design,
we can contribute to the
development of more
sustainable and efficient
digital technologies.
METHODOLGY RESULT
This project has made
significant strides in the
design of a full adder, a key
component in many digital
devices. The goal was to
create a design that uses
less power and operates
faster. By using a unique
design that requires only
ten transistors, we’ve
managed to reduce power
consumption significantly.
This is especially
important for devices that
run on batteries, where
saving power is crucial.
We also focused on
reducing the delay in signal
propagation, which is the
time it takes for a signal to
travel through a circuit. By
using advanced technology
and optimizing the circuit,
we’ve managed to make
the full adder operate
faster. This is particularly
important in devices that
need to process
information quickly. When
we compared our new
design to previous ones,
we found that power
consumption, delay
reduction, and power delay
product improved by
92.3% to 34.80%, 97.2% to
94.5%, and 99.35% to
94.5% respectively. These
results show that our
design is more efficient
and performs better than
previous designs.
 ABSTRACT

The circuit implements a sum and a carry for a full adder, which is an n-bit
addition of the two n-1-bit numbers. One of the fundamental parts in any digital
circuits that have been used in many application areas like microprocessors,
digital signal processors, and arithmetic logic units. Some researchers have
shown some interest to design efficient and fast full adder circuits in several
years. This is as a result increased demand of mobile, battery-operated devices.
To reduce the power consumption of a whole adder circuit, one approach
involves employing fewer transistors in its implementation. In this paper, a new
full adder design using only ten transistors is offered, yielding lower power
dissipation and reduced delay in comparison to previous schemes. CMOS
technology is employed in executing the proposed design. Full Adder was
designed by using CADENCE VIRTUOSO with 90NM technology.
 IEEE/IEC Standards

Adherence to relevant IEEE and IEC standards is imperative to ensure the

robustness and compatibility of the Full Adder design. Key standards include:

IEEE 1149.1 (JTAG): Standard Test Access Port and Boundary-Scan Architecture

This standard provides guidelines for testing and debugging digital circuits,
ensuring that the Full Adder design meets testing requirements.

IEC 60601: Medical Electrical Equipment Standard

If applicable to the project, compliance with IEC 60601 ensures the safety and
performance of the Full Adder in medical applications.

IEEE 754: Standard for Floating-Point Arithmetic

If the Full Adder involves floating-point arithmetic, adherence to IEEE 754

ensures consistent and accurate numerical computations.

1
 Sustainable Development Goals (SDGs)

As a global effort to solve social and environmental problems, low energy,

highspeed all-
collector design can help achieve several development goals (SDGs) set by the
United Nations. The following Sustainable Development Goals are specific:

SDG 7: Affordable and clean energy

The pursuit of lower energy production promotes access to affordable energy C

heap, reliable energy, the goal of modern energy for all.
SDG 9: Jobs, Innovation, and Infrastructure

The development of electric energy is aligned with the goal of creating energy
efficiency, promoting joint ventures and sustainable development, and fostering
innovation.
SDG 13: Climate Action

The program helps mitigate climate change by reducing energy consumption an

d environmental footprint and encourages the implementation of the resolve.

2
 CHAPTER 1

INTRODUCTION

Low power VLSI configuration has attracted tremendous attention in

recent years. With the consistently expanding interest for compact gadgets,
Internet of Things (IoT) applications, and energy-conscious computing
systems, the requirement for low-power and high-speed has increased. In
this specific situation, the design and investigation of a Full Adder circuit
with a focus on achieving both low power consumption and reduced delay
as a vital undertaking. The Full Adder, a central structure block of digital
arithmetic-, plays an essential part in various applications ranging from
processors to memory units. It works with the addition of binary numbers,
forming the backbone of Arithmetic Logic units (ALUs) that support
digital systems. With the expansion of cell phones and the emergence of
energy-constrained environments, the interest for power-efficient circuitry
has raised. The energy crisis and environmental worries have required a
change in perspective towards designing circuits that deliver high
performance while minimizing their ecological footprint.

The propagation delay, described as the time taken for a signal to traverse
a circuit, assumes an essential part in deciding the operational speed of
system. As the world turns out to be more dependent on instant data
processing and consistent communication, the need to mitigate signal delay
turns out to be more fluent. A Full Adder circuit with reduced propagation
delay not only enhances the overall system performance as well as
addresses the interest for quicker reaction times in applications, for
example, communication networks, multimedia processing, and real-time
control systems. the development of power-efficient Full Adder circuits can

3
broaden the operational life of battery-powered gadgets, reducing the
burden of regular recharging and improving the user experience. In the
context of the Internet of Things (IoT),where small scale devices frequently
work in remote or energy-constrained conditions, low-power circuitry can
empower extended device lifetimes and reduce the maintenance overhead.
Besides, in data centres and high-performance computing, where energy
expenses and heat dissipation are substantial concerns, the arrangement of
power efficient Full Adder designs can contribute to significant reductions
in operational expenses and natural effect.

Fig 1.1: Block diagram and logic Circuit.[1]

In this fig 1, full adder circuit is a fundamental digital electronic component

used in arithmetic and logic operations within digital circuits, such as
microprocessors and computers. It is designed to add three binary inputs:
two single-bit binary numbers (A and B) and a carry-in (C_in) from a
previous stage of addition. The full adder generates two outputs: the sum

4
 (S) of the inputs and a carry-out (C_out) that represents whether there is a
carry-over to the next stage of addition.

Full adder circuit can be constructed by using logic gates such as AND,
OR, and EXOR gates.

1.1. NEED IDENTIFICATION

There is the increment in the requests of present-day computing system,
combined with the objectives of energy efficiency and high -speed operation,
have led to a convincing requirement for the implementation and investigation
of a Full Adder design that focuses on low power consumption and reduced
delay.

1.1.1 Energy Efficiency Imperative

In an era marked by ecological concerns and energy shortage, energy-efficient

electronic devices have turned into a social and technological need. Portable
gadgets, for example, cell phones, tablets, etc. It has pervaded each part of
day-to-day existence, yet their limited battery duration stays a persistent issue.
The interest for prolonged battery duration requires the advancement of digital
circuits with reduced power consumption, especially within critical
components like Full Adders, which are universal in arithmetic and
computational operations.

1.1.2 Battery-Powered Devices

Battery-powered devices, integral to communication, calculation, and

entertainment, depend on circuits that enhance power consumption without
compromising performance. The Full Adder, a foundation of arithmetic logic,
directly influences the efficiency of these devices. By accomplishing low power
consumption in Full Adder deigns, the operational existence of battery-powered

5
devices can be fundamentally broadened, reducing the requirement for frequent
recharging, and improving user satisfaction.

1.1.3 IoT and Remote Sensing

Full Adder circuits integrated into these devices must strike a balance between
computational capability and energy consumption to ensure sustainable operation
over extended periods.

1.1.4 Data Centres and High-Performance Computing

Data centres are the foundation of current computing, working with data storage,
processing, and communication. In any case, the energy consumption of these
centres presents significant environmental and financial difficulties. Full Adder
designs that display low power consumption and reduced delay can add to
significant energy savings within data centre infrastructure, lining up with the
developing pattern towards greener computing.

1.1.5 Real-Time and Latency-Sensitive Applications

The increasing demand for real-time data processing in applications such as

multimedia streaming, online gaming, and autonomous vehicles necessitates
circuits with minimal propagation delay. Delays in signal processing can lead to
performance degradation and compromised user experiences. Reducing the
propagation delay in Full Adder circuits is vital for maintaining the
responsiveness and efficiency of these applications.

1.2 IDENTIFICATION OF PROBLEMS

At first Power consumption, has emerged as a main concern because of the

widespread of battery-powered devices and energy-efficient consisting of
standards. Full Adder designs frequently display significant power dispersal,
leading to reduced battery duration, increased heat generation, and ultimately

6
 limiting the operational longevity of portable devices. Addressing this
challenge requires the development of novel design techniques that can
successfully minimize power consumption without compromising the integrity
of arithmetic operations.

Secondly, In the Full Adder circuit, the propagation delay poses a consequential
obstacle to achieving high-speed digital systems. As the requirements for data
processing escalate, the need for reduced signal propagation delay becomes
increasingly crucial. Long propagation delays can obstruct real-time data
processing, latency-sensitive applications, and overall system performance. To
reduce this challenge, it is very important to explore innovative circuit
architectures and design methodologies that enhance the speed of Full Adder
circuits without intensifying power consumption.

Moreover, in this we have to make balance between low power consumption

and reduced propagation delay presents a mind-boggling compromise.
Traditional design strategies frequently require compromises were improving
one aspect negatively impacts the other. The challenge lies in finding a
synergistic arrangement that optimizes both power consumption and
propagation delay simultaneously, a task that requires a deep understanding of
circuit behaviours and efficient use of advanced fabrication technologies.

1.3 IDENTIFICATION OF TASKS

Designing such a circuit involves several steps and considerations.

a) Literature Review: Research existing full adder designs that emphasize low
power consumption and reduced delay. Look into various techniques,
architectures, and technologies that have been used in similar designs.

b) Design Specifications: Define the specific requirements for the full adder
design, such as the input/output configurations, power consumption limits,
maximum allowable delay, and any other constraints.
7
c) Architecture Selection: Choose an appropriate architecture for full adder.
Common architectures include CMOS, pass-transistor, and transmission gate
full adders. Select the one that aligns best with your power and delay goals.

d) Transistor Sizing and Technology Selection: Determine the sizes of

transistors used in your design. Transistor sizing affects both power
consumption and delay. Choose a suitable technology node that balances these
factors.

e) Gate Level Design: Design the full adder circuit at the gate level using the
chosen architecture. This involves creating a schematic of the circuit using
logic gates and transistors.

f) Simulation and Verification: Use simulation tools (For example

CADENCE) to validate the design. Simulate the circuit under different input
conditions to ensure it behaves correctly and meets the specified power and
delay requirements.

g) Power Analysis: Perform power analysis to evaluate how much power your
design consumes. This involves calculating dynamic power, static power, and
any leakage power. Identify areas where power optimization is possible.

h) Delay Analysis: Analyse the propagation delay through design. Identify

critical paths that contribute to delay and consider techniques like pipeline
stages or logical restructuring to minimize delays.

i) Power-Delay Trade-off: Balance the trade-off between power consumption

and delay. Some design choices that reduce power consumption might
increase delay, and vice versa. Find the optimal compromise for the specific
application.

j) Layout and Fabrication: If we are planning to physically implement the

circuit, create a layout based on gate-level design. Ensure proper placement
and routing to minimize parasitic effects and improve performance.

8
k) Post-Fabrication Testing: If we fabricate the circuit, perform post
fabrication testing to validate its performance against simulations. Measure
power consumption, delay, and other relevant metrics.

l) Optimization Iterations: Iterate through the design, simulation, and testing

stages to refine your full adder design further. Experiment with different
transistor sizes, architectures, and techniques to achieve better results.

m) Documentation and Reporting: Document every step of design process,

including methodologies, results, challenges faced, and the final design. This
documentation can be helpful for future reference or sharing with others. 1.4

TIMELINE

Fig 1.2: Project Timeline

9
1.5 ORGANIZATION OF REPORT

The report is organized into five chapters. The chapter wise detail is given
below:

Chapter 1:

This chapter comprises of the introduction about the Implementation and

investigation of a full Adder design for low power and Reduced delay and

through multiple sources and the requirement and motivation to the project.

Chapter 2:

The detailed literature review on the various existing systems with features, and
design parameter specifications are included in this chapter.

Chapter 3:

This chapter includes the project details and methodology with software
requirements and implementation.

Chapter 4:

The results and its validation are also shown in this chapter for the proposed
design.

Chapter 5:

This chapter presents the conclusion and future scope of the work done.

10
 CHAPTER 2

LITERATURE REVIEW

2.1 Timeline of the reported problem

Prolific Literature published in reputed journals are read and comparison of full
adder circuit in terms of speed, power and area is done. We concentrate on the
way each researcher study and bring out the outcome while considering the area
device lacking in. The main logic is to combine up hybrid logics including
transistors and branch based to form a design achieving powerdelayareaproduct
(PDAP) with CMOS using gates for full adder circuits.
Multiple problems like simulation Discrepancies, Power Gating Efficiency,
Area optimization, Fabrication Variability and Clock Gating impact on speed
are reported with few amendments in the circuit to improve its performance.
The focus is to get low power for all the gadgets that make it more portable to
use.

2.2 Bibliometric analysis and Solution from literature

[1] 1999 Hanan A. Mahmoud and Magdy.A. Bayoumi

An author proposed a ten-transistor low power high speed full adder cell in this
paper. The design consists of a ten transistor/one bit/full, fast, and low power
adder cell. It has a fundamental format involving a logic XOR gate, an inverter
and one pass transistors. The average delay time for a 0.6pm model of the
proposed adders is estimated to be about 34ns. The item as well possesses mean
power loss of 0.891*10-4 watt for one GHz rate. The new adder cell will reverse
the carryout polarity of the odd and even position of an n-bit adder circuit. Drivers

11
are inverters in the FA cell structure. Secondly, a decline in the ability of
successive stages to derive will be prevented. It saves on power, region, and time.

A 32-digit ripple carry adder can be built based on the new cell. The 250 MHz
prototype with 384 transistors runs on 2.8 V with average delay at 4.1 ns and very
little power consumption of 2.6 mA.

Fig 2.1: 10-transisitor Full Adder Cell [1]

[2] 2001, Ayman A. Fayed and Magdy A. Bayoumi

In this paper, the author explores and proposes a 10-transistor full adder cell
tailored for embedded systems. This introduced cell offers the distinct advantages
of low power consumption and high operational speed, all within a compact
footprint due to its minimal transistor usage. The strategy employed to achieve
low power consumption involves reducing internal node capacitances,
eliminating direct paths between the voltage supply and ground, and maintaining
alignment with low circuit switching activity. To validate the proposed design, a
prototype circuit was implemented in Cadence using 350nm CMOS technology
and simulated on h-spice. The results indicate that at 500 MHz, the circuit
dissipates a mere 0.752*10^{-6} watts, underscoring its efficiency in power

12
usage. The paper also includes a comparative analysis with a recently developed
and reported 16-transistor adder cell. Furthermore, the applicability of this new
transmission gate adder cell is demonstrated by constructing a bit multiplier for
testing purposes, showcasing the versatility and practicality of the proposed
design in larger system architecture.

Fig 2.2: 10-transistor adder cell[2]

[3] 2001, Lu Junming , Shu Yan , Lin Zhenghui and Wang. Ling

In this paper, the authors present an innovative 10-transistor, one-bit adder cell
characterized by high speed and ultra-low power consumption. The
straightforward design incorporates an inverter, a XOR or XNOR gate, and a
single pass transistor. This cell offers a low-power, compact footprint, and rapid
alternative to the conventional I-digit full-adder cell. The prototype of the
proposed adder cell, implemented on 0.35-micron technology, demonstrates a
remarkably low delay of 0.2417 nanoseconds. Operating at a frequency of 10
MHz, the device exhibits a mean power dissipation of 4.936 *10^(-6) watts. The
simulations presented in this paper illustrate the superior performance of the
proposed adder cell compared to standard implementations, highlighting its
potential for high-speed, low-power applications.

13
 Fig 2.3: The 10-transistor low-power 1-bit full adder[3]

[4] 2007, Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Member, IEEE, and
Cheng-Che Ho

Here, authors presented a new scheme for construction of full adder with just ten
transistors per bit. The proposed full adder design using pass transistor logic has
low operating voltage, high computation speed and low power operation
compared to others for low gate count full adders. In addition, it uses inverter
buffered XOR/XNOR plans to overcome the high threshold voltage loss problem
encountered in standard pass transistor logic design. The partial failure of this
problem usually makes it impossible for the full adder design to operate under low
supply voltage. The full adder design with a limited number of transistors and
buffering circuit incorporated effectively. This increased buffering enables the
design to work at a lower supply voltage than in existing works. Besides, it
considerably increases response time of the cascaded operation and maintains a
high-performance rate for power consumption. Performances of both DC and
proposed design are examined and compared with various full adder designs using
extensive H-SPICE Simulations. Resulting simulation is based on TSMC 2P4M
0.35um model process showing the present model has the lowest voltage supply
and high operating frequency to the system with ten transistor. The second one
also comes low on energy per addition of the three. The energy consumed edge
and the speed of the exhibited part of this proposed plan are increasingly massive
as the words of the adder increase.

14
 Fig 2.4: Conventional 10T full adder design[4]

[5] 2011, Tae-Won Cho, Mohamed G. Ahmed, Ju-Ho Lee, Dong-Keun Song

The author proposed a design of a low power, high speed, energy efficient and
silicon region in this paper. The hybrid logics of pass transistor and the
branchbased logics are investigated as well in a modified full adder. In this
architecture, there are two separate autonomous generators of sum and carry
signals. This design gives a better outcome compared with conventional static
CMOS full adder of achieving ultralow power progression, very short propagation
delay which is also small silicon area. Besides, this design can be integrated into
multibit adder thereby eliminating additional inverses. To conduct thorough
investigations, we used 0.13um CMOS technology.

Fig 2.5: 10 transistor adders[5]

15
[6] 2011, Shivshankar Mishra, V. Narendar, Dr. R. A. Mishra

This paper presents two high-performance full adder designs. In our investigation,
we conducted simulations for both proposed 5-transistor full adder circuits and a
5-transistor full adder (5-TFA) based on an advanced CMOS standard library cell.
These simulations were carried out using the Cadence VIRTUOSO environment
in 0.18um UMC CMOS technology. The comparative analysis of the results
highlights the performance of our proposed circuits. Remarkably, these circuits
demonstrate their suitability for a variety of applications, including arithmetic
circuits and other VLSI applications requiring ultra-low-power operations and
exceptionally high speeds. Tested under a supply voltage of 1.8V, the proposed
designs exhibit promising characteristics for meeting the demands of both
lowpower and high-speed requirements in diverse VLSI applications.

Fig 2.6: 10T Full Adder[6]

[7] 2014, Krishnendu Dhar

In this paper, the author presents a novel design for a Low Power, High-Speed,
and Energy-Efficient Full Adder utilizing a modified Gate Diffusion Input (GDI)
and Multi-Threshold Voltage (MVT) Scheme in the context of 45nm technology.
A comparative analysis with traditional full adders employing CMOS transistors,
transmission gates, and Complementary Pass-Transistor Logic (CPL) individually
demonstrates substantial reductions in various performance metrics. When
compared to the traditional counterparts, the proposed design exhibits significant

16
decreases in average power consumption (Pavg), peak power consumption (Peak),
delay time, power delay product (PDP), energy-delay product (EDP), as well as
transistor count and surface area. Specifically, Pavg is remarkably low at 7.61x107
watts, while Peak is as low as 6.21x10-5 watts. The delay time is measured at 2.05
nanoseconds, and both PDP and EDP are impressively low at 1.56x10-15 Joules
and 3.20x10-24 Joule-seconds, respectively, for a 0.9-volt power supply. To
validate the proposed design, simulations were conducted using HSPICE, and the
layout was implemented in Microwind, emphasizing the practicality and
efficiency of the introduced GDI and MVT Scheme in 45nm technology.

Fig 2.7: Circuit diagram of the proposed full adder[7]

[8] 2016, Akshay Bhaskar , Dheeraj Reddy , Shabhari Saravanan , Jagannadha

Naidu K

Author suggested a circuit design of 10 high speed transistors full adder for low
power using multi-threshold strategy in this paper. The paper presents 10T full
adder of low power working in 45nm Complementary Pass Transistor (CPT)
Technology. A comparison is made between the power scattering and delay in the
proposed transistor full adder circuit design versus the regular 28 transistor full
adder with transistor full adder and MTCMOS full adder-based transistor. The
provided design has power dissipation reduced by 99.528% in comparison with

17
the 28-transistor conventional full adder while PDP decreases by 99.913%. The
proposed circuit requires only about 30 percent of the area that would be occupied
by 64 percent and goes hand in hand with great velocity.

Fig 2.8: Proposed 10 transistor Full Adder[8]

[9] 2016, Haseeb Pasha

In This paper a Design and analysis of full adder cell for low power with
highspeed using modified GDI procedure at 90nm technology is done. They
analyse for different 1-bit full addition cells based on MGDI approach is to
enhance power consumption, propagation time and PDP. The MGDI technique
reduces circuit delay as well as space and is complex in digital design logic. Using
a variety of low-power full adder circuit design techniques, through investigation
to achieve perfection. These full adders aim in providing high speed performance
with low power consumption and good voltage swing. The low power techniques
for reduction of both power and delay can be achieved. The comparison between
various low power full adder cells on power dissipation, time delayed, and Power
Delay product is presented by this work. Then, the complete design for the full
adder simulations is performed following 90 nm technology by using Tanner EDA
instrument.

18
 Fig 2.9: 10T MGDI Full Adder[9]

[10] 2016, MD.Masood Ahmad, Dr K.Manjunathachari, Dr K.Lalkishore

This paper Involves different full adder topology for one-bit, among which the
most exciting one is considered. It is then analysed and compared for peak
leakage, average leakage, peak power, and average power. The research was
performed using appropriately designed simulation runs on a cadence software
the proposed full adder 10 transistor circuit requires 57% of the average power
compared to conventional CMOS logic circuit having 28 transistors. In fact, it has
dissipated 67 per cent of the power required for typical leakage at standard CMOS
with 28 transistors. Proposed 10 transistors CMOS logic has maximum leakage
current of 67% compared to 28 transistors logic while maximum power
dissipation is 70%. A full-type adder for 10 transistors.

19
 Fig 2.10: 10T Full Adder[10]

[11] 2017, P. Sushma Sri Naga Mowlika1 ,V.Srinivasa Rao

This paper addresses an outline of a full adder made by the help of 10 transistor.
In this we are using the lector technique it implies a technique or approach used
in the designing of the full adder to optimize its performance or efficiency. The
proposed design results in lower power as compared to the existing ones. These
designs were simulated using Cadence tools which are used in technology of
CMOS, 180 nm, and 45 nm technology. It was found that they have better quality
characteristics, such as PDP (power delay product), layout area, and power
dissipation. The simulation demonstrates that suggested circuit operates quickly
and dissipates minimum power.

20
 Fig 2.11: Two logic style full adder[11]

[12] 2020, Mansi Jhamb, Manoj Kumar, Vishal

The author made a proposition of full adder for low power applications. A low
power one-bit hybrid FA is presented as spontaneously created via analytical
comparison with other conventional adders. A 1-bit low power hybrid full adder
is regarded as an effective enhancement for circuits compared to regular full adder
circuits. The analysis paper of one- bit low power hybrid FA is implemented by
using electronic design automation and the simulation and comparison are made
for this circuit by generic 90nm CMOS technology and for five volts and
comparison is done with other conventional full adders under different voltages.
As far as comparing a 1-bit low power hybrid full adder with conventional adders
in terms of static and dynamic power, delay, and PDP is concerned, it clearly states
the applicability of a 1-bit low power hybrid full adder to different low power
design areas.

21
 Fig 2.12: - Low power hybrid full adder[12]

[13] 2022, K. Praghash2 · S. Arun Metha1 · B. Sai Tanuja1 · K. Preethi1 · N.

P. N. S. Chandana1

This paper recommended an approach for testing an ideal full adder in a low power
for minimized delay conditions. Here, in our writing project, was supposed to be
focusing on the operation of a full adder circuit to operate at both low power and
delay levels. This task utilizes one product which is MENTOR GRAPHICS based
on the 180 nm technology. To evaluate the effectiveness of this design proposal
for a transistor is done through power consumption, delay, PDP, capacitor load,
delay W.r.t capacitance and PDP w.r.t capacitance. In this case, one should
consider the boundaries established between the proposed design with literature
schemes such as OLPFAD, DFEFA, DTLPCFA, and DPEHFA.
Clearly, our prescribed approach prevails over others.

22
 Fig 2.13: Optimal 10 transistor full adder circuit[13]

2.3 REVIEW SUMMARY

The research paper titled "Implementation and Investigation of a Full Adder

Design for Low Power and Reduced Delay" explores the critical domain of digital
circuit design, with a particular focus on enhancing the efficiency and speed of
full adder circuits.

Table 2.1: Comparisons.

Ref No. Technology Tool No. of Supply Delay

transistors Input
Voltage

[1] 0.6pm H-Spice 10 2.8v 0.084ns

[2] 0.35µm H-Spice 10 2.7v-3.3v 3.452ns

[3] 0.35 µm H-Spice 10 3.3v 4.4617ns

[4] 0.35 µm H-Spice 10 2.8v 22.54ns

23
[5] 0.13 µm H-Spice 10 2.7v 0.2ns

[6] 0.18 µm 10 1.8v 3.63*

Cadence
10-11
Virtuoso

[7] 45nm Cadence 10 2.8v 2.05ns

Virtuoso

[8] 45nm Cadence 10 2.6v-3.2v 0.18ns

Virtuoso

[9] 90nm Cadence 10 1.2v 5.272ns

Virtuoso

[10] 45nm Cadence 10 2.6v 0.52ns

Virtuoso

[11] 180nm and Cadence 10 2.4v 1.28ns and

45nm Virtuoso 0.24ns

[12] 90nm 10 1.1v 89.53ps

Cadence
Virtuoso

[13] 180nm 10 1.8v 57ps

Cadence
Virtuoso

2.4 PROBLEM DEFINITION

In the study of the “10-transistor low-power high-speed full adder cell”, a notable
omission is the lack of discussion surrounding substrate biasing. this technique,
prevalent in transistor design, is instrumental in controlling leakage current and
reducing power dissipation. the absence of substrate biasing in the design could
24
potentially lead to increased power consumption due to heightened leakage
currents. this is particularly significant in low-power applications where energy
efficiency is paramount. Furthermore, without substrate biasing, the design may
not leverage dynamic threshold voltage scaling. this technique allows for dynamic
application of bias, leading to more efficient power usage.

2.5 GOAL/OBJECTIVE

The goal/objective of the research project titled "Implementation and

Investigation of a Full Adder Design for Low Power and Reduced Delay" is likely
to focus on improving the performance of full adder circuits in terms of power
efficiency and propagation delay having low Power Consumption using 10
transistors.

25
 CHAPTER 3

OBJECTIVES & METHODOLOGY

3.1 Problem Formulation and Objectives

The problem has been formulated with an apparent aim to study and evaluate
different types of adder design topologies. Reduced delay and low power are the
principal necessities of an analog circuit design. A Full Adder is a fundamental
building block in digital electronics, used for arithmetic operations in processors,
calculators, and various digital systems. It adds three binary inputs (A, B, and
Carry-In) to produce a sum output (S) and a carry output (Carry-Out). The
techniques and methodologies to minimize the power consumption of the Full
Adder circuit. It’s process to Investigate the ways to decrease the propagation
delay in the Full Adder circuit. It Reduced delay improves the overall performance
of digital systems, enabling faster calculations and responses.

The objectives to be achieved are:

1) Design full adder using 10 transistors.

2) To perform the analysis of the designed adder for low power and high speed.

3) To validate the proposed design with its peer design.

3.2 Research Methodology

The EDA tool utilized for simulation results is Cadence Virtuoso tool. After
completion of schematic design next step is to perform the transient analysis to
check the connection of all the transistor properly. After that transient analysis is
performed to check the waveform with matching the truth table for full adder.
Adjust the pulse width rise and fall time and execute the circuit analysis. The
transient analysis is accomplished to discover the low power, reduced delay etc.
Transient analysis helps in achieving the values of slew rate and settling time.

26
 Start

Study and analysis different full adders

Finding the research gaps and the key

performance for overcoming the
research

Apply possible modifications and learn

the respective tool

Performance evaluation of proposed

design using EDA tool

Comparison of results

Paper writing and publication

END

Fig 3.1: Research Methodology

27
In Figure 3.1 first step is to analyse different adder circuits and find out which
circuit is best for low power, reduced delay and parallelly on the other hand find
out the research gap of the paper to find out the fact that where this particular
technique is lack down. After that learn the tool which is suitable for proper
analysis of the simulation results. All the performances are carried out at Cadence
Virtuoso EDA tool working at 90nm. Lastly compare the results between base
paper and implemented design. In this Chapter research methodology is
discussed. All the simulation works are carried out on Cadence Virtuoso tool by
the help of truth table.

Input Parameters:

Transient analysis:

• Supply Voltage = 1v

• Technology Node= 90nm • Tool Used= Cadence Virtuoso

• Stop time= 100ns.

Output Parameters:

• Delay
• Power Consumption

28
 CHAPTER 4

4.1 Proposed Full adder design

Our main aim behind this is to focus on the design which gives us the accurate
and precise value in comparisons with our base papers. So, for this we had taken
2 designs. These circuits made on the Cadence virtuoso software having 90nm
technology. Both the designs are given in Fig 4.1 Design 1 and Fig 4.2 Design 2.
Out of these two designs we had selected the design1 because in design 2 we had
more fluctuation in the output of sum in comparison to design 1 and in design 1
we get our nearby values in comparison with our base papers.

Fig 4.1: Design 1

29
 Fig 4.2: Design 2

From the above two designs in fig 4.1 and 4.2 we had selected design 1. Reason
for getting selected is given below:

Fig 4.3: Output of Design 1

In the fig 4.3 output of design1 we did not select this due to its fluctuation in the
output of sum.
30
4.2 Calculation Parameters

For the calculation purpose we have taken different parameters at first, we have
to start with the truth table of full adder.

Table 4.1: Truth table of Full Adder

Now by taking K-map output for sum:

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅ ̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅
𝐒𝐔𝐌 = A̅̅̅̅ ̅̅̅̅̅̅̅̅ B̅̅̅̅ ̅̅̅̅̅̅̅̅ C + A̅̅̅̅̅̅̅̅ BC̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ + BA̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ C̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ + ABC

31
 CARRY=BC+AC+AB

4.2.1 Low Power

By the following steps we can calculate the power:

Step1: First, we have set the input voltage.

Fig 4.4: Input voltage (1v)

Step 2: Choose the transient analysis and stop time of 100ns.

Fig 4.5: Transient analysis

32
Step 3: Select the output to be plotted from the schematics.

Fig 4.6: Outputs

Step 4: Give the voltage to A, B and C. Period and pulse width (32n and 16n to A
and B) for C(16n and 8n).

Fig 4.7: Give the input values

33
Step 5: Run the program.

Fig 4.8: Output in Pulse form

Step 6: Save all the program.

Fig 4.9: Save the program

34
Step 7: Goto Direct plot form and select power.

Fig 4.10: Direct plot form

Step 8: Run the program.

Fig 4.11: Power for 1v

35
Step 9: By right clicking in the power pulse select send to calculator.

Fig 4.12: Calculate power

Step 10: By selecting average, the final value obtained.

Fig 4.13: Final output.

36
Step 11: Continue the steps for different voltages (0.9v, 1.1v, 1,2v, 1.3v, 1.4v) and
calculate the power.

Table 4.2: Power for different voltages

4.2.2 Reduced Delay

By following steps, we can calculate the reduced delay:

For calculating this delay, we have to follow the same steps that we had done the
calculations for Low power. From step 1 to 9 we had to do this process for
different voltages ( 1v, 1.1v, 1.2v, 1.3v, 1.4v).

Step 10: Search delay in functional panel.

Fig 4.14: Functional panel

37
Step 11: Take any input and any output copy the code of each in signal 1(for input
and signal 2 (for output) having threshold voltage 1 and 2 (0.5v).

Fig 4.15: Giving inputs

Step 12: Calculate reduced delay.

Fig 4.16: Reduced delay for 0.9v

38
Step 13: Same steps should be done for different voltages for calculating the
reduced delay.

Table 4.3: Reduced delay for different voltages

The above table 4.3 talks about the reduced delay in our proposed design.
Table 4.4: Power Delay Product For proposed design

39
4.3 Comparison and analysis

Table 4.5 , Table 4.6, and Table 4.7 demonstrate energy consumption, delay and
power delay product considering different proposed full adders’ voltages (i.e.,

0.9v – 1.4v) in comparison with the previous design. For 0.9v, power consumption
of the proposed circuit is 1.769µW.

Table 4.5: Power Consumption varying VDD

In this table 4.5 we observed that our proposed delay is shorter it means that
the work can be done quickly and get quick responses.

Table 4.6 illustrates a comparison of the Delay Consumption between the

recently implemented circuit across a supply voltage range from 0.9V to 1.4V
with the provided previous designs . The new layout exhibits a significant
reduction in delay.

40
 Table 4.6: Delay varying VDD

In the Table 4.6 we observed that our proposed delay is better in performance
with our existing delay. It enhances the performance of the applications and
increases the speed.

Table 4.7 illustrates a comparison of the Power-Delay Product (PDP) between

the recently implemented circuit across a supply voltage range from 0.9V to
1.4V with the provided previous designs . The new layout exhibits a
significant reduction in PDP.

41
 Table 4.7 :Power Delay Product varying VDD

In this table 4.7 it implies that our proposed design achieves a balance between
processing speed (lower delay) and energy efficiency (lower power
consumption).

42
 CHAPTER-5

CONCLUSION AND FUTURE SCOPE

5.1 Conclusion

In conclusion, the implementation and investigation of a full adder design aimed

at achieving low power consumption and reduced delay have yielded significant
insights into the realm of digital circuit design. The designed full adder
demonstrates noteworthy success in achieving low power consumption. Through
careful consideration of transistor sizing, gate-level optimization, and power
gating techniques, the power efficiency of the circuit has been significantly
improved. This bodes well for applications where power consumption is a critical
factor, such as in battery-operated devices or energy-efficient computing systems.

Our investigation into delay reduction strategies, including the use of advanced
semiconductor technologies and circuit optimization techniques, the designed full
adder exhibits reduced propagation delay compared to traditional designs. This
improvement is crucial for enhancing the overall speed and performance of digital
systems, particularly in high-frequency applications.

In this paper we observed that in 90nm technology when we compare our new
design to the prior design there is the improvement in power consumption, delay
reduction and power delay product is 92.3% to 34.80%, 97.2% to 94.5% and
99.35% to 94.5%.

5.2 Future Scope

While the current investigation provides valuable insights, there are opportunities
for further exploration and enhancement. Future work could focus on exploring
alternative design methodologies, incorporating emerging technologies, and
evaluating the performance of the full adder in larger digital systems. Eventually,

43
the potential integration of machine learning techniques for automated design
optimization could be a promising avenue for future research.

6. References

[1] On the Design of High-Performance CMOS 1-Bit Full Adder Circuits.

https://www.ijcaonline.org/proceedings/icvci/number5/2663-1285.

[2] A low power 10-transistor full adder cell for embedded architectures.
https://ieeexplore.ieee.org/document/922213/.

[3] Wang, D., Yang, M., Cheng, W., Guan, X., Zhu, Z., & Yang, Y. (2009). Novel
low power full adder cells in 180nm CMOS technology. In: 2009 4th IEEE
Conference on Industrial Electronics and Applications (pp. 430–433). IEEE.

[4] Shams, A. M., Darwish, T. K., & Bayoumi, M. A. (2002). Performance

analysis of low-power 1-bit CMOS full adder cells. IEEE transactions on very
large-scale integration (VLSI) systems, 10(1), 20–29.

[5] Murthy, A. S., Murthy, P. S., Rajesh, V., Ahammad, S. H., & Jagan, B. O.
(2019). Execution of natural random forest machine learning techniques on
multi spectral image compression. International Journal of Pharmaceutical
Research, 11(4), 1241–1255. [6] (PDF) Base | manikumar giddi -
Academia.edu.

[6]. Sudhanshu, J., Shaurakar, D., (2018). Design and performance evaluation of
hybrid full adder for extensive PDP reduction. In: IEEE 2018 3rd international
conference for convergence in technology (I2CT).

[7]. Goel, S., Kumar, A., & Bayoumi, M. A. (2006). Design of robust,
energyefficient full adders for deep sub micrometre design using Hybrid-CMOS
logic style. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems,
14(12), 1309–1321.

44
[8]. Moradi, F., Wisland, D. T., Mahmoodi, H., Aunet, S., Cao, T. V., & Peiravi,
A. (2009). Ultra-low power full adder topologies. In: 2009 IEEE International
Symposium on Circuits and Systems (pp. 3158–3161). IEEE.

[9]. Vijaya, L. A., Nagendra Babu, K. V. T., Sree Ram Deepak, M., Sai, K. A.,
Chandra Sekhar Yadav, G. V. P., Gopi, T. V., & Ghali, V. S. (2019). A machine
learning based approach for defect detection and characterization in non-linear
frequency modulated thermal wave imaging. International Journal of Emerging
Trends in Engineering Research, 7(11), 517–522.

[10]. Murthy, A. S., Murthy, P. S., Rajesh, V., Ahammad, S. H., & Jagan, B. O.
(2019). Execution of natural random forest machine learning techniques on multi
spectral image compression. International Journal of Pharmaceutical Research,
11(4), 1241–1255.

[11]. Sreedhar, B. S., & Bojja, P. (2019). Machine learning algorithms for MR
brian image classifcation.

[12] R.Uma, and P. Dhavachelvan, ―Modified Gate Diffusion Input Technique:

A New Technique for Enhancing Performance in Full Adder Circuits‖ 2nd
International Conference on Communication, Computing & Security
[ICCCS2012].

[13] Raj kumar Sarma and Veerati Raju, ―Design and Performance and Analysis
of Hybrid Adders for High-Speed Arithmetic Circuit‖ International
Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June
2012.

45
 APPENDIX

Technology file 90nm

MODEL NMOS90 NMOS
* Flags
SIGN = 1 TNOM = 27 TG = -1 QOFF = 0
XL = 0 XW = 0 SCALE = 1
NQS_NOI = 1 TH_NOI = 0
AVTO = 0 AGAMMA = 0 AKP = 0
VTO = 0.055 COX = 0.0145 XJ = 2E-008
PHIF = 0.428 GAMMA = 0.155 GAMMAG = 15 N0 = 1.05
VBI = 0 AQMA = 2 AQMI = 0.5 ETAQM = 0.75
KP = 0.00095 E0 = 1.4E+008 E1 = 1E+010 ETA = 1
ZC = 1E-006 THC = 0
FPROUT = 3E+006 PDITS = 6E-005 PDITSL = 0
PDITSD = 0.2 DDITS = 10
KA = 0.4 LA = 3E-007 KB = 0.5 LB = 2E-008
WKP1 = 2.4E-007 WKP2 = 0.6 WKP3 = 0.5
LVT = 1 WVT = 0.0001 AVT = 0.035
LGAM = 1 WGAM = 0.0001 AGAM = 0.025
NFVTA = 0 NFVTB = 1E+004
DL = 2.5E-008 DW = -1E-008 DLC = 0 DWC = 1.5E-008
RLX = 7.5E-005 RSX = -1 RGX = -1 RBX = -1
LL = 0 LLN = 1 WDL = 7E-015 LDW = 2.5E-015
LR = 6.708E-008 QLR = 0.0033 NLR = 0.075 FLR = 1
WR = 1E-007 QWR = 5E-006 NWR = 0.0005
NCS = 1.5 LETA0 = 1E+006 LETA = 1.05 LETA2 = -2.5E-008
WETA = 0.2 UCRIT=3.8E+006 LAMBDA = 0.48 DELTA = 2 ACLM = 0.83
ETAD = 1.1 SIGMAD = 0.3 LOV = 2.1E-008 GAMMAOV = 4 VFBOV = 0 VOV = 1
CGSO = 0 CGDO = 0 CGBO = 0 KJF = 0 CJF = 0 VFR = 0 DFR = 0.001
IBA = 0 IBB = 9E+008 IBN = 0.1 KG = 1.5E-005 XB = 6 EB = 4E+010 LOVIG = 2.5E-008
AGIDL = 0 BGIDL = 2.3E+009 CGIDL = 0.5 EGIDL = 0.8 AF = 1 KGFN=0
NT = 7.7E+017 ALPHAC= 1E+005 HOOGE = 1E-020 SAREF = 1.46E-006 SBREF = 1.46E-006 WLOD = 0 KKP
=0

LKKP = 0 WKKP = 0 PKKP = 0 TKKP = 0 LLODKKP = 1 WLODKKP = 1 KVTO = 0 LKVTO = 0

46
WKVTO = 0 PKVTO = 0 LLODKVTO = 1 WLODKVTO = 1 TCV = 0.0003 BEX = -1.2 TETA = 0 UCEX = 1.5
TLAMBDA = 0.2 TE0EX = 0 TE1EX = 0 IBBT = 0.0009 TCVL = 0 TCVW = 8E-011 TCVWL = 0
TR = 0 TR2 = 0 ND = 1 JS = 0 JSW = 0 JSWG = 0 MJ = 0.5 MJSW = 0.33 MJSWG = 0.33
PB = 1 PBSW = 1 PBSWG = 1 CJ = 0 CJSW = 0 CJSWG = 0 NJTS = 20 NJTSSW = 20 NJTSSWG = 20
VTS = 10 VTSSW = 10 VTSSWG = 10 MIN = 1E-011 XJBV = 1 BV = 10 XTI = 3
TCJ = 0 TCJSW = 0 TCJSWG = 0 TPB = 0 TPBSW = 0 TPBSWG = 0 TNJTS = 0 TNJTSSW = 0 TNJTSSWG = 0
RSH = 0 LDIF = 0 HDIF = 2.4E-007 RS = 0 RD = 0 WE0= 5E-008 WE1 = 0 WRLX = 5E-008
WUCRIT=-4E-008 WLAMBDA = 0 WETAD = 0 WUCEX = 0 WLR = 0 WQLR = 0 WNLR = 1.3E-007
LWR = 0 LQWR = 1.5E-006 LNWR = 0 DGAMMAEDGE = 0 DPHIEDGE = 0 WEDGE = 0 LDPHIEDGE = 0
WDPHIEDGE = 0
WLDPHIEDGE = 0 WLDGAMMAEDGE = 0 RGSH = 53 GC = 1 RDSBSH = 1500 RBWSH = 1000 RBN =
0 RSBWSH = 50 RSBN = 0 RDBWSH = 50 RDBN = 0 RINGTYPE = 1
*
**********************************************************************************
*******

* EKV3.0 model card for PMOS devices indicative of an 90nm CMOS technology
**********************************************************************************
******
*
.MODEL PMOS90 PMOS

* Flags
SIGN = -1 TNOM = 27 TG = -1
QOFF = 0 XL = 0 XW = 0 SCALE = 1
NQS_NOI = 1 TH_NOI = 0 AVTO = 0 AGAMMA = 0 AKP = 0
VTO = -0.068 COX = 0.0135 XJ = 1.041E-008
PHIF = 0.42 GAMMA = 0.02596 GAMMAG = 5.5 N0 = 1.1
VBI = 0 AQMA = 0.5908 AQMI = 0.3926 ETAQM = 0.75
KP = 0.000293 E0 = 9.5E+007 E1 = 8.259E+009 ETA = 1.311
ZC = 1E-006 THC = 0 FPROUT = 1E+007 PDITS = 1.5E-005 PDITSL = 0
PDITSD = 0.8 DDITS = 10 KA = 0 LA = 3E-006 KB = 0 LB = 1.7E-007
WKP1 = 3E-007 WKP2 = -0.27 WKP3 = 1.5 LVT = 1 WVT = 0.0001 AVT = 0.15
LGAM = 1.5E-006 WGAM = 1 AGAM = -0.2
NFVTA = 0 NFVTB = 1E+004 DL = 8.5E-008 DW = 0 DLC = 0 DWC = 1E-007 RLX
= 5E-005 RSX = -1 RGX = -1 RBX = -1 LL = 0 LLN = 1 WDL = 0 LDW = 0

LR = 3.826E-008 QLR = 0.0083 NLR = 7.494 FLR = 0 WR = 4E-008 QWR = 0.0003 NWR = -0.03

47
NCS = 2 LETA0 = 2.7E+006 LETA = 1.5 LETA2 = 0 WETA = 0
UCRIT=1.65E+007 LAMBDA = 1.45 DELTA = 1 ACLM = 0.83 ETAD = 1.75 SIGMAD = 1
LOV = 2.4E-008 GAMMAOV = 3 VFBOV = 0 VOV = 1 CGSO = 0 CGDO = 0 CGBO = 0
KJF = 0 CJF = 0 VFR = 0 DFR = 0.001 IBA = 0 IBB = 4E+008 IBN = 1
KG = 2.461E-005 XB = 4.28 EB = 2.842E+010 LOVIG = 2.806E-008 AGIDL = 0
BGIDL = 2.3E+009 CGIDL = 0.5 EGIDL = 0.8 AF = 1 KGFN = 0
NT = 7.7E+017 ALPHAC= 1E+005 HOOGE = 1E-020 SAREF = 1.46E-006 SBREF = 1.46E-006 WLOD = 0 KKP
=0
LKKP = 0 WKKP = 0 PKKP = 0 TKKP = 0 LLODKKP = 1 WLODKKP = 1 KVTO = 0 LKVTO = 0
WKVTO = 0 PKVTO = 0 LLODKVTO = 1 WLODKVTO = 1
TCV = -0.0005 BEX = -1.1 TETA = 0 UCEX = 3.5 TLAMBDA = 1.5 TE0EX = 0.5 TE1EX = 1 IBBT = 0.0007
TCVL = -3E-011 TCVW = 3E-011 TCVWL = 0 TR = -0.005 TR2 = 0
ND = 1 JS = 0 JSW = 0 JSWG = 0 MJ = 0.9 MJSW = 0.7 MJSWG = 0.7
PB = 0.8 PBSW = 0.6 PBSWG = 0.6 CJ = 0 CJSW = 0 CJSWG = 0
NJTS = 1 NJTSSW = 1 NJTSSWG = 1 VTS = 0 VTSSW = 0 VTSSWG = 0
GMIN = 0 XJBV = 0 BV = 10 XTI = 3
TCJ = 0 TCJSW = 0 TCJSWG = 0 TPB = 0 TPBSW = 0 TPBSWG = 0
TNJTS = 0 TNJTSSW = 0 TNJTSSWG = 0 RSH = 0 LDIF = 0 HDIF = 2.4E-007 RS
= 0 RD = 0 WE0= 1.5E-007 WE1 = 0 WRLX = 0
WUCRIT=1.3E-007 WLAMBDA = 2.5E-008 WETAD = -4E-008 WUCEX = 0
WLR = 0 WQLR = -2E-008 WNLR = -1.7E-007 LWR = 0 LQWR = 0 LNWR = -5E-008
DGAMMAEDGE = 0 DPHIEDGE = 0 WEDGE = 0 LDPHIEDGE = 0 WDPHIEDGE = 0
WLDPHIEDGE = 0 WLDGAMMAEDGE = 0 RGSH = 50 GC = 1 RDSBSH = 1E+004 RBWSH = 1000
RBN = 0 RSBWSH = 75 RSBN = 0 RDBWSH = 75 RDBN = 0 RINGTYPE = 1

CHARACTERISTICS FOR NMOS

. o p t i o n nowarn = 9 0 2 ! Turn o f warn ing ”Model param et er i g n o r e d ”

. o p t i o n aex ! A l low fo r s a v i n g e x t r a c t e d v a l u e s t o f i l e

. o p t i o n o a s c i ! Turn o f f a s c i i −bas ed p l o t t i n g o f r e s u l t s i n . ch i−f i l e

. o p t i o n jwdb ! C r e a t e . wdb output

. o p t i o n nocou ! Do not c r e a t e . cou output

. prob e v

. temp 2 7 . 0 0 0 0

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 t t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s t a t . mod

48
 . l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s s . mod . l i b / dak /90 nm 4 0b 1 e

ld o / cm o s 0 9 0 s s a . mod nmos0 l = 0 .1 w=1.2 nmos1 l = 0 .2 w=1.0 nmos2 l = 0

.5 w=4.0 nmos3 l = 1 .0 w=4.0 xnmos0 vd n vg n v s n vb n n s v t l e a k l = 0 .

1 w= 1 . 2 n f i n g =1 mult=10 xnmos1 v d f l o a t 1 vg n v s n vb n n s v t l e a k l = 0

.2 w= 1 .0 n f i n g =1 mult=10 xnmos2 v d f l o a t 2 vg n v s n vb n n s v t l e a k l

= 0 .5 w= 4 .0 n f i n g =1 mult=10 xnmos3 v d f l o a t 3 vg n v s n vb n n s v t l e a k l =

1 .0 w= 4 .0 n f i n g =1 mult=10 vd vd n 0 dc 1 . 0 vs v s n 0 dc 0 vg vg n 0 dc 1 . 0 vb

vb n 0 dc 0

. s t e p vb 0 −0 . 2 −0 . 1

. s t e p vd 0 1 . 0 0 . 0 5

. dc vg − 1 . 0 1 . 0 0 . 0 5

. p l o t i d ( xnmos0 .m1)

. p l o t i b ( xnmos0 .m1)

NOTICE : t h i s 9 0nm model i s o f l e v e l bsim3 , h en c e th e g a t e l e a k a g e c a l c u l a t i o n

i s bas ed on a . sub ck t −−> i g−e x t r a c t i o n can not be a c c omp l i sh ed a s a p a r t o f th e M1

MOSFET p a r am e t e r s . I n s t e a d an amperemeter must be used .

. p l o t i g ( xnmos0 .m1) . p

l o t i ( vg )

. p l o t gm( xnmos0 .m1)

. p l o t gds ( xnmos0 .m1)

. e x t r a c t l a b e l=vg f i l e =e x t r a c t s . t x t vg ( xnmos0 .m1) .

e x t r a c t l a b e l=vd f i l e =e x t r a c t s . t x t vd ( xnmos0 .m1) .

e x t r a c t l a b e l=vs f i l e =e x t r a c t s . t x t vs ( xnmos0 .m1)

49
. e x t r a c t l a b e l=vb f i l e =e x t r a c t s . t x t vb ( xnmos0 .m1)

. e x t r a c t l a b e l=vth f i l e =e x t r a c t s . t x t vt ( xnmos0 .m1)

. e x t r a c t l a b e l=gm max f i l e =e x t r a c t s . t x t max(gm( xnmos0 .m1) )

. e x t r a c t l a b e l=gm min f i l e =e x t r a c t s . t x t min (gm( xnmos0 .m1) )

. e x t r a c t l a b e l=gds max f i l e =e x t r a c t s . t x t max( gds ( xnmos0 .m1) )

. e x t r a c t l a b e l=gds m in f i l e =e x t r a c t s . t x t min ( gds ( xnmos0 .m1 ) )

. e x t r a c t l a b e l=i g f i l e =e x t r a c t s . t x t i g ( xnmos0 .m1)

. end

CHARACTERISTICS FOR PMOS

. o p t i o n nowarn = 9 0 2 ! Turn o f f warn ing ”Model param et er i g n o r e d ”

. o p t i o n aex ! A l low fo r s a v i n g e x t r a c t e d v a l u e s t o f i l e

. o p t i o n n o a s c i i ! Turn o f f a s c i i −bas ed p l o t t i n g o f r e s u l t s i n . ch i−f i l e

. o p t i o n jwdb ! C r e a t e . wdb output

. o p t i o n nocou ! Do not c r e a t e . cou output

. prob e v

. temp 2 7 . 0 0 0 0

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 t t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s t a t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s a . mod .

l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s s . mod . l i b / dak /90 nm 4 0b 1 e

ld o / cm o s 0 9 0 s s a . mod pmos0 l = 0 .1 w=3.0 pmos1 l = 0 .2 w=1.0 pmos2 l

= 0 .5 w=8.0 pmos3 l = 1 .0 w=8.0 xpmos0 vd n vg n v s n vb n p s v t l e a k l = 0 . 1

w= 3 . 0 n f i n g =1 mult=10 xpmos1 v d f l o a t 1 vg n v s n vb n p s v t l e a k l = 0

.2 w= 1 .0 n f i n g =1 mult=10 xpmos2 v d f l o a t 2 vg n v s n vb n p s v t l e a k l =

50
0 .5 w= 8 .0 n f i n g =1 mult=10 xpmos3 v d f l o a t 3 vg n v s n vb n p s v t l e a k l =

1 .0 w= 8 .0 n f i n g =1 mult=10 vd vd n 0 dc −1 .0 vs v s n 0 dc 0 vg vg n 0 dc

−1 .0 vb vb n 0 dc 0

N o t i c e t h a t vb i s s t epp ed a l s o t o 0 . 3V fo r pmos .

I n v e s t i g a t e th e d i f f e r e n c e between th e l a s t vb=0.2 b l o c k and th e l a s t but one

vb=0.2 b l o c k

( when s t epp ed t o on l y 0 . 2V) t o und e r s t and why .

. s t e p vb 0 0 . 3 0 . 1

. s t e p vd 0 −1 . 0 −0 . 0 5

. dc vg 1 . 0 −1 . 0 −0 . 0 5

. p l o t i d ( xpmos0 .m1)

. p l o t i b ( xpmos0 .m1)

NOTICE : t h i s 9 0nm model i s o f l e v e l bsim3 , h en c e th e g a t e l e a k a g e c a l c u l a t i o n

i s bas ed on a . sub ck t −−> i g−e x t r a c t i o n can not be a c c omp l i sh ed a s a p a r t o f th e

M1 MOSFET p a r am e t e r s . I n s t e a d an amperemeter must be used . . p l o t i g ( xpmos0 .m1)

. p l o t i ( vg )

. p l o t gm( xpmos0 .m1)

. p l o t gds ( xpmos0 .m1)

. e x t r a c t l a b e l=vg f i l e =e x t r a c t s . t x t vg ( xpmos0 .m1) .

e x t r a c t l a b e l=vd f i l e =e x t r a c t s . t x t vd ( xpmos0 .m1) .

e x t r a c t l a b e l=vs f i l e =e x t r a c t s . t x t vs ( xpmos0 .m1)

. e x t r a c t l a b e l=vb f i l e =e x t r a c t s . t x t vb ( xpmos0 .m1)

. e x t r a c t l a b e l=vth f i l e =e x t r a c t s . t x t vt ( xpmos0 .m1)

. e x t r a c t l a b e l=gm max f i l e =e x t r a c t s . t x t max(gm( xpmos0 .m1) )

. e x t r a c t l a b e l=gm min f i l e =e x t r a c t s . t x t min (gm( xpmos0 .m1) )

. e x t r a c t l a b e l=gds max f i l e =e x t r a c t s . t x t max( gds ( xpmos0 .m1) )

. e x t r a c t l a b e l=gds m in f i l e =e x t r a c t s . t x t min ( gds ( xpmos0 .m1 ) )

. e x t r a c t l a b e l=i g f i l e =e x t r a c t s . t x t i g ( xpmos0 .m1)

. end

CV CHARACTERISTICS FOR NMOS

51
. o p t i o n nowarn = 9 0 2 ! Turn o f f warn ing ”Model param et er i g n o r e d ”

. o p t i o n aex ! A l low fo r s a v i n g e x t r a c t e d v a l u e s t o f i l e

. o p t i o n n o a s c i i ! Turn o f f a c s i i −bas ed p l o t t i n g o f r e s u l t s i n . ch i−f i l e

. o p t i o n jwdb ! C r e a t e . wdb output

. o p t i o n nocou ! Do not c r e a t e . cou output

. prob e v

. temp 2 7 . 0 0 0 0

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 t t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s t a t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s s . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s s a . mod nmos0 : w= 1 . 2 l

=0.1 nmos1 : w= 1 . 0 l =0.2 nmos2 : w= 4 . 0 l =0.5 nmos3 : w= 4 . 0 l

=1.0 xnmos0 vd n vg n v s n vb n n s v t l e a k w= 1 .2 l =

0 .1 n f i n g =1 mult=10 xnmos1 vd n vg n v s n vb n n s v t l e a k w= 1 .0 l =

0 .2 n f i n g =1 mult=10 xnmos2 vd n vg n v s n vb n n s v t l e a k w= 4 .0 l = 0 .5 n f i n g

=1 mult=10 xnmos3 vd n vg n v s n vb n n s v t l e a k w= 4 .0 l =

1 .0 n f i n g =1 mult=10 vs v s n 0 dc 0 . 0 vg vg n 0 dc 0 . 0 vd vd n 0 dc 0 .

0 vb vb n 0 dc 0 . 0

. dc vg −1 1 0 . 0 0 5

. de fwave cbb nmos0 abs=abs ( cbb ( xnmos0 .m1 ) )

. de fwave cbd nmos0 abs=abs ( cbd ( xnmos0 .m1 ) )

. de fwave cb s nm o s 0 ab s=abs ( cb s ( xnmos0 .m1) )

. de fwave cb g nm o s 0 ab s=abs ( cbg ( xnmos0 .m1) )

52
. de fwave c g g nm o s 0 ab s=abs ( cgg ( xnmos0 .m1) )

. de fwave c gb nm o s 0 ab s=abs ( cgb ( xnmos0 .m1) )

. de fwave c g s nm o s 0 a b s=abs ( c g s ( xnmos0 .m1) )

. de fwave c gd nm o s 0 ab s=abs ( cgd ( xnmos0 .m1) )

. de fwave c g nm o s 0 a b s=abs ( cgb ( xnmos0 .m1)+ c g s ( xnmos0 .m1)+cgd ( xnmos0 .m1 ) ) ! e q u

a l s c g g nm o s 0 ab s

. de fwave c b nm o s 0 a b s=abs ( cbg ( xnmos0 .m1)+ cb s ( xnmos0 .m1)+cbd ( xnmos0 .m1 ) ) ! e q u a

l s cbb nmos0 abs

. de fwave c g b t o t a b s=abs ( cgb ( xnmos0 .m1)+cgb ( xnmos1 .m1)+cgb ( xnmos2 .m1)+cgb (

xnmos3 .m1) )

. de fwave c g s t o t a b s=abs ( c g s ( xnmos0 .m1)+ c g s ( xnmos1 .m1)+ c g s ( xnmos2 .m1)+ c g s (

xnmos3 .m1) )

. de fwave c g d t o t a b s=abs ( cgd ( xnmos0 .m1)+cgd ( xnmos1 .m1)+cgd ( xnmos2 .m1)+cgd (

xnmos3 .m1) )

. de fwave c g g t o t a b s=abs ( cgg ( xnmos0 .m1)+ cgg ( xnmos1 .m1)+ cgg ( xnmos2 .m1)+ cgg (
xnmos3 .m1) )

. de fwave c b g t o t a b s=abs ( cbg ( xnmos0 .m1)+cbg ( xnmos1 .m1)+cbg ( xnmos2 .m1)+cbg (

xnmos3 .m1) )

. de fwave c b s t o t a b s=abs ( cb s ( xnmos0 .m1)+ cb s ( xnmos1 .m1)+ cb s ( xnmos2 .m1)+ cb s (

xnmos3 .m1) )

. de fwave c b d t o t a b s=abs ( cbd ( xnmos0 .m1)+cbd ( xnmos1 .m1)+cbd ( xnmos2 .m1)+cbd (

xnmos3 .m1) )

. de fwave c b b t o t a b s=abs ( cbb ( xnmos0 .m1)+cbb ( xnmos1 .m1)+cbb ( xnmos2 .m1)+cbb (

xnmos3 .m1) )

. de fwave c s g t o t a b s=abs ( c s g ( xnmos0 .m1)+ c s g ( xnmos1 .m1)+ c s g ( xnmos2 .m1)+ c s g (

xnmos3 .m1) )

. de fwave c d g t o t a b s=abs ( cdg ( xnmos0 .m1)+cdg ( xnmos1 .m1)+cdg ( xnmos2 .m1)+cdg (

xnmos3 .m1) )

. p l o t w( cbb nmos0 abs )

. p l o t w( cbd nmos0 abs )

. p l o t w( cb s nm o s 0 ab s )

. p l o t w( cb g nm o s 0 ab s )

. p l o t w( c g g nm o s 0 ab s )

. p l o t w( c gb nm o s 0 ab s )

. p l o t w( c g s nm o s 0 a b s )

. p l o t w( c gd nm o s 0 ab s )

53
. p l o t w( c g nm o s 0 a b s )

. p l o t w( c b nm o s 0 a b s )

. p l o t w( c g b t o t a b s )

. p l o t w( c g s t o t a b s )

. p l o t w( c g d t o t a b s )

. p l o t w( c g g t o t a b s )

. p l o t w( c b g t o t a b s )

. p l o t w( c b s t o t a b s )

. p l o t w( c b d t o t a b s )

. p l o t w( c b b t o t a b s )

. p l o t w( c s g t o t a b s )

. p l o t w( c d g t o t a b s )

. end

CV CHARACTERISTICS FOR PMOS

. o p t i o n nowarn = 9 0 2 ! Turn o f f warn ing ”Model param et er i g n o r e d ”

. o p t i o n aex ! A l low fo r s a v i n g e x t r a c t e d v a l u e s t o f i l e

. o p t i o n n o a s c i i ! Turn o f f a c s i i −bas ed p l o t t i n g o f r e s u l t s i n . ch i−f i l e

. o p t i o n jwdb ! C r e a t e . wdb output

. o p t i o n nocou ! Do not c r e a t . cou output

. prob e v

. temp 2 7 . 0 0 0 0

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 t t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s t a t . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 f s a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s f a . mod

. l i b / dak /90 nm 4 0b 1 e ld o / cm o s 0 9 0 s s . mod . l i b / dak /90 nm 4

54
0b 1 e ld o / cm o s 0 9 0 s s a . mod pmos0 : w= 3 . 0 l =0.1 pmos1 : w= 1 . 0 l

=0.2 pmos2 : w= 8 . 0 l =0.5 pmos3 : w= 8 . 0 l =1.0 xpmos0 vd n1 vg n v s n

vb n1 p s v t l e a k w= 3 .0 l = 0 . 1 n f i n g =1 mult=10 xpmos1 vd n2 vg n v s n

vb n1 p s v t l e a k w= 1 .0 l = 0 . 2 n f i n g =1 mult=10 xpmos2 vd n3 vg n v s

n vb n1 p s v t l e a k w= 8 .0 l = 0 . 5 n f i n g =1 mult=10 xpmos3 vd n4 vg n v s n

vb n1 p s v t l e a k w= 8 .0 l = 1 . 0 n f i n g =1 mult=10 vs v s n 0 dc 0 . 0 vg vg n

0 dc 0 . 0 vd vd n 0 dc 0 . 0 vb vb n 0 dc 0 . 0

. dc vg −1 1 0 . 0 0 5

. de fwave cbb pmos0 abs=abs ( cbb ( xpmos0 .m1 ) )

. de fwave cbd pmos0 abs=abs ( cbd ( xpmos0 .m1 ) )

. de fwave cb s pm o s 0 ab s=abs ( cb s ( xpmos0 .m1) )

. de fwave cb g pm o s 0 ab s=abs ( cbg ( xpmos0 .m1) )

. de fwave c g g pm o s 0 ab s=abs ( cgg ( xpmos0 .m1) )

. de fwave c gb pm o s 0 ab s=abs ( cgb ( xpmos0 .m1) )

. de fwave c g s pm o s 0 a b s=abs ( c g s ( xpmos0 .m1) )

. de fwave c gd pm o s 0 ab s=abs ( cgd ( xpmos0 .m1) )

. de fwave c g pm o s 0 a b s=abs ( cgb ( xpmos0 .m1)+ c g s ( xpmos0 .m1)+cgd ( xpmos0 .m1 ) ) ! e q u

a l s c g g pm o s 0 ab s

. de fwave c b pm o s 0 a b s=abs ( cbg ( xpmos0 .m1)+ cb s ( xpmos0 .m1)+cbd ( xpmos0 .m1 ) ) ! e q u a

l s cbb pmos0 abs

. de fwave c g b t o t a b s=abs ( cgb ( xpmos0 .m1)+cgb ( xpmos1 .m1)+cgb ( xpmos2 .m1)+cgb (

xpmos3 .m1) )

. de fwave c g s t o t a b s=abs ( c g s ( xpmos0 .m1)+ c g s ( xpmos1 .m1)+ c g s ( xpmos2 .m1)+ c g s (

xpmos3 .m1) )

. de fwave c g d t o t a b s=abs ( cgd ( xpmos0 .m1)+cgd ( xpmos1 .m1)+cgd ( xpmos2 .m1)+cgd (

xpmos3 .m1) )

. de fwave c g g t o t a b s=abs ( cgg ( xpmos0 .m1)+ cgg ( xpmos1 .m1)+ cgg ( xpmos2 .m1)+ cgg (
xpmos3 .m1) )

. de fwave c b g t o t a b s=abs ( cbg ( xpmos0 .m1)+cbg ( xpmos1 .m1)+cbg ( xpmos2 .m1)+cbg (

xpmos3 .m1) )

. de fwave c b s t o t a b s=abs ( cb s ( xpmos0 .m1)+ cb s ( xpmos1 .m1)+ cb s ( xpmos2 .m1)+ cb s (

xpmos3 .m1) )

. de fwave c b d t o t a b s=abs ( cbd ( xpmos0 .m1)+cbd ( xpmos1 .m1)+cbd ( xpmos2 .m1)+cbd (

xpmos3 .m1) )

55
. de fwave c b b t o t a b s=abs ( cbb ( xpmos0 .m1)+cbb ( xpmos1 .m1)+cbb ( xpmos2 .m1)+cbb (
xpmos3 .m1) )

. de fwave c s g t o t a b s=abs ( c s g ( xpmos0 .m1)+ c s g ( xpmos1 .m1)+ c s g ( xpmos2 .m1)+ c s g (

xpmos3 .m1) )

. de fwave c d g t o t a b s=abs ( cdg ( xpmos0 .m1)+cdg ( xpmos1 .m1)+cdg ( xpmos2 .m1)+cdg (

xpmos3 .m1) )

. p l o t w( cbb pmos0 abs )

. p l o t w( cbd pmos0 abs ) . p

l o t w( cb s pm o s 0 ab s ) . p l

o t w( cb g pm o s 0 ab s )

. p l o t w( c g g pm o s 0 ab s )

. p l o t w( c gb pm o s 0 ab s )

. p l o t w( c g s pm o s 0 a b s )

. p l o t w( c gd pm o s 0 ab s )

. p l o t w( c g pm o s 0 a b s )

. p l o t w( c b pm o s 0 a b s )

. p l o t w( c g b t o t a b s )

. p l o t w( c g s t o t a b s ) .

p l o t w( c g d t o t a b s ) . p

l o t w( c g g t o t a b s ) . p l

o t w( c b g t o t a b s )

. p l o t w( c b s t o t a b s )

. p l o t w( c b d t o t a b s )

. p l o t w( c b b t o t a b s )

. p l o t w( c s g t o t a b s )

. p l o t w( c d g t o t a b s )

. end

56