Uu Tien 1

No.
CHAPTER 1
1 Computer technology is changing at a pace.

a. slow
b. slow to medium
c. rapid
d. non-existent
2 Computer refers to those attributes that have a direct impact on the logical execution of a
program.
a. organization
b. specifics
c. design
d. architecture
3 Architectural attributes include .

a. I/O mechanisms
b. control signals
c. interfaces
d. memory technology used
4 attributes include hardware details transparent to the programmer.

a. Interface
b. Organizational
c. Memory
d. Architectural
5 It is a(n) design issue whether a computer will have a multiply instruction.

a. architectural
b. memory
c. elementary
d. organizational
6 It is a(n) issue whether the multiply instruction will be implemented by a special multiply unit or
by a mechanism that makes repeated use of the add unit of the system.
a. architectural
b. memory
c. mechanical
d. organizational
7 A system is a set of interrelated subsystems.
a. secondary
b. hierarchical
c. complex
d. functional
8 An I/O device is referred to as a .

a. CPU
b. control device
c. peripheral
d. register
9 When data are moved over longer distances, to or from a remote device, the process is known as
.
a. data communications
b. registering
c. structuring
d. data transport
10 The stores data.

a. system bus
b. I/O
c. main memory
d. control unit
11 A common example of system interconnection is by means of a .

a. register
b. system bus
c. data transport
d. control device
12 The moves data between the computer and its external environment.
a. data transport
b. I/O
c. register
d. CPU interconnection
13 A is a mechanism that provides for communication among CPU, main memory, and I/O.
a. system interconnection
b. CPU interconnection
c. peripheral
d. processor
14 provide storage internal to the CPU.

a. Control units
b. ALUs
c. Main memory
d. Registers
15 The performs the computer's data processing functions.
a. Register
b. CPU interconnection
c. ALU
d. system bus
16 The ALU makes use of to store the immediate results
a. Accumulators
b. Registers
c. Heap
d. Stack
17 Computer architecture refers to (Select all correct answers):
A. Design idea
B. Install specific hardware
C. The operational units in the computer and their interconnections
D. The attributes that have a direct impact on the logical execution of a program
18 Computer organization refers to (Select all correct answers):

A. Design idea
19 When considering whether a computer has a multiply instruction, we are referring to:
A. Computer organization
B. Computer architecture
C. Computer hardware
D. Computer software
20 When considering the memory technology used, we are referring to:

A. Computer hardware
B. Computer software
C. Computer organization
D. Computer architecture
21 Software compatibility, in point of view of the architecture, want to mention that:

A. Ability to use old software on new machines
B. Ability to use new software on old machines
C. Ability to use old software on new machines that belong to the same architecture as the old one
D. Ability to use new software on old machines that belong to the same architecture with new machines
22 Who are interested in computers with architectural look?

A. Application Programmer
B. System Programmer
C. HLL Programmers
D. All of the others
23 Who are interested in computers with organizational look?

A. Computer Designer
B. Compiler Designer
C. System Programmer
D. None of the others
24 Statement I: Structure is the way in which the components are interrelated.

Statement II: Function is the operation of each individual component as part of the structure.
Which of the above statements are true?
A. Statement I is true
B. Statement II is true
C. Both the statements are true
D. Both the statements are false
25 The basic functions of the computer:

A. Data storage, run programs, connect to peripherals, access memory
B. Data movement, control, execute instructions, data processing
C. Data storage, data movement, data processing, control
D. Control, data storage, perform calculations, connect to the internet
26 The basic components of the computer:

A. RAM, CPU, hard drive, system interconnection
B. Memory system, system interconnection, ROM, keyboard
C. Memory system, CPU, monitor, mouse
D. Memory system, CPU, I/O, system interconnection
27 The main structured components of a processor (Not including internal interconnection):
A. Control unit, registers, I/O ports
B. Control unit , ALU, registers
C. Registers, DACs, control unit
D. ALU, registers, I/O ports
28 The memory system of computers include:

A. Cache, external memory
B. External memory, ROM
C. Optical disc, internal memory
D. Internal memory, external memory
29 A common example of system interconnection is by means of a ..........., consisting of a number of

conducting wires to which all the other components attach.
A. Address Bus
B. Data Bus
C. System Bus
D. Control Bus
30 In the computer, there are the following types of system interconnections:

A. Instruction, function, control
B. Control, data, address
C. Data, dependent, control
D. Data, control, auxiliary
31 Another word for the CPU is
a. Executer
b. Microprocessor
c. Microchip
d. Decoder
CHAPTER 2
1 The was the world's first general-purpose electronic digital computer.

a. UNIVAC
b. MARK IV
c. ENIAC
d. Hollerith's Counting Machine
2 The Electronic Numerical Integrator and Computer project was a response to U.S. needs during
.
a. the Civil War

b. the French-American War
c. World War I
d. World War II
3 The ENIAC used .

a. vacuum tubes
b. integrated circuits
c. IAS
4 The ENIAC is an example of a generation computer.

a. first
b. second
c. third
d. fourth
5 The interprets the instructions in memory and causes them to be executed.

a. main memory
b. control unit
c. I/O
d. arithmetic and logic unit
6 The memory of the IAS consists of 1000 storage locations called .

a. opcodes
b. wafers
c. VLSIs
d. words
7 The contains the 8-bit opcode instruction being executed.

a. memory buffer register
b. instruction buffer register
c. instruction register
d. memory address register
8 During the the opcode of the next instruction is loaded into the IR and the address portion is
loaded into the MAR.
a. execute cycle
b. fetch cycle
c. instruction cycle
d. clock cycle
9 Second generation computers used .

b. integrated circuits
c. Transistors
d. vacuum tubes
e. large-scale integration
10 The defines the third generation of computers.

a. integrated circuit
b. vacuum tube
c. transistor
d. VLSI
11 The use of multiple processors on the same chip is referred to as and provides the potential to
increase performance without increasing the clock rate.
a. multicore
b. GPU
c. data channels
d. MPC
12 With the , Intel introduced the use of superscalar techniques that allow multiple instructions to
execute in parallel.
a. Core
b. 8080
c. 80486
d. Pentium
13 The measures the ability of a computer to complete a single task.

a. clock speed
b. speed metric
c. execute cycle
d. cycle time
14 ARM processors are designed to meet the needs of .

a. embedded real-time systems
b. application platforms
c. secure applications
d. all of the above
15 One increment, or pulse, of the system clock is referred to as a .
a. clock tick
b. cycle time
c. clock rate
d. cycle speed
16 In the concept of "stored program", the computer fetches instructions ........

A. from memory
B. from opening/closing of electrical switches
C. from program
D. from hard disk
17 The concept of "stored program" allows:

A. The program can be altered directly through the values stored in memory
B. Many algorithms can be implemented inside the machine without having to rewire
C. Reduce time of program execution
18 Von Neumann is computer: (Select all correct answers)

1. Only one processor, execute sequential instructions
2. Perform the program located inside the memory
3. Can execute multiple instructions simultaneously (in parallel)
4. All of the others
19 So far, computers have grown through:

A. 3 generations
B. 4 generations
C. 5 generations
D. 6 generations
20 During the development process of the computer, which of the following statements is true:
A. The first generation uses a vacuum tube
B. The third generation uses transistors
C. The fourth-generation uses SSI and MSI
21 During the development process of the computer, which of the following statements is false:
A. The second generation uses transistors
B. The first generation uses vacuum tube
C. The fourth generation uses integrated circuit
D. The third generation uses transistor
22 When did the first transistor be invented?

A. 1947
B. 1958
C. 1969
D. 1971
23 According to Moore's Law, the number of transistors will double after each:
A. 16 months
B. 18 months
C. 20 months
D. 22 months
24 The invention of integrated circuit brought us .......... of computers.

A. The second generation
B. The third generation
C. The fourth generation
D. The fifth-generation
25 A silicon piece with electronic circuits on it is called .......
A. Circuit
B. Logic gate
C. Chip
D. Circuit network
26 Which parameters in a computer family are similar or identical?

A. Instruction set
B. Number of I/O ports
C. Speed
D. Operation system
27 Which parameters in a computer family are increased from the old machine to the newer one?
A. Speed
B. Memory size
C. Cost
D. All of the above
28 Which of the following are the basic factors in the commercial success of a computer? (Select all correct
answers)
1. Performance
2. Cost
3. Speed
4. Memory size
29 What are the main goals of a computer system?
A. To provide the best performance at a low cost
B. To provide speedy operation at low power consumption
C. To provide optimal power operation
30 This figure show what is the current processor development trend? (Select all correct answers)
1. Increasing number of transistors on a single chip
2. Multicore (placing multiple processors on the same chip)
3. Building a more complex processor
4. Increasing clock rate
31 In the given figure, black rectangles are ........

A. Vacuum tubes
B. Transistors
C. Integrated circuits
32 Balance of performance is to ........

A. Make the processor run faster
B. Make the processor operate
more efficiently
C. Make the processor and other important components of computers run faster
D. Make the processor and other important components of computers operate more efficiently
33 Which of the following is not a solution to balance performance?

A. Reduce the frequency of memory access
B. Increase the number of bits that are retrieved at one time
C. Increase the interconnect bandwidth between processors and memory
34 An approach to increase the speed of the processor is ........

A. Dedicate a part of the processor chip for the cache
B. Increase the clock rate
C. Use pipelining
D. All of the above
35 Which of the following is not a reason for moving to multicore organizations?

A. The benefits of applying pipeline technology as well as increasing levels of cache on the processor
B. Effect of the resistor and parasitic capacitance between the transistors on a chip
C. Problem of dissipating heat on high density chips
D. None of the above
CHAPTER 3
1 Virtually all contemporary computer designs are based on concepts developed by at the
Institute for Advanced Studies, Princeton
a. John Maulchy
b. John von Neumann
c. Herman Hollerith
d. John Eckert
2 The von Neumann architecture is based on which concept?
a. data and instructions are stored in a single read-write memory

b. the contents of this memory are addressable by location
c. execution occurs in a sequential fashion
d. all of the above
3 A sequence of codes or instructions is called .
a. software
b. memory
c. an interconnect
d. a register
4 The processing required for a single instruction is called a(n) cycle.
a. execute
b. fetch
c. instruction
d. packet
5 A(n) is generated by a failure such as power failure or memory parity error.
a. I/O interrupt
b. hardware failure interrupt
c. timer interrupt
d. program interrupt
6 A(n) is generated by some condition that occurs as a result of an instruction execution.
a. timer interrupt
b. I/O interrupt
c. program interrupt
d. hardware failure interrupt
7 The interconnection structure must support which transfer?
a. memory to processor
b. processor to memory
c. I/O to or from memory
d. all of the above
8 A bus that connects major computer components (processor, memory, I/O) is called a .
a. system bus
b. address bus
c. data bus
d. control bus
9 The are used to designate the source or destination of the data on the data bus.
a. system lines
b. data lines
c. control lines
d. address lines
10 The data lines provide a path for moving data among system modules and are collectively called the
.
a. control bus
b. address bus
c. data bus
d. system bus
11 The internal components of the processor are connected by
a. Process intra-connectivity circuitry

b. Processor bus
c. Memory bus
d. Rambus
12 A is the high-level set of rules for exchanging packets of data between devices.
a. bus
b. protocol
c. packet
d. QPI
13 Each data path consists of a pair of wires (referred to as a ) that transmits data one bit at a
time.
a. lane
b. path
c. line
d. bus
14 The device which is used to connect a peripheral to a bus is called
a. Control Register
b. Interface
c. Communication Protocol
d. None of the above
15 The receives read and write requests from the software above the TL and creates request
packets for transmission to a destination via the link layer.
a. transaction layer
b. root layer
c. configuration layer
d. transport layer
16 The TL supports which of the following address spaces?
a. memory
b. I/O
c. message
d. all of the above
17 The QPI layer is used to determine the course that a packet will traverse across the available
system interconnects.
a. link
b. protocol
c. routing
d. physical
18 Which of the following registers connects to the memory through the address bus?
A. I/O AR
B. I/O BR
C. MAR
D. MBR
19 The time required to fetch an instruction from memory and execute it is called ........
A. Fetch Cycle
B. Execution Cycle
C. Load Cycle
D. Instruction Cycle
20 The CPU of a computer takes instructions from memory and executes them. This process is called
a. Load
b. Time Sequence
c. Execution
d. Fetch-Execute Cycle
21 In the process of executing a program, which of the following are initialized first?
A. MAR
B. MBR
C. IR
D. PC
22 The decoded instruction is stored in
a. IR
b. PC
c. Registers
d. MDR
23 The basic structure of instruction has .........
A. Operand and Opcode
B. Decoder and Accumulator
C. Sequence register and Decoder
24 Interrupts can be generated to response to ........
A. Input/ Output activities
B. Detected program errors such as arithmetic overflow or division by zero
C. Detected hardware faults
D. All of the above
25 Which of the following is used to overcome the difference in data transfer rates of different devices?
A. Speed enhancing circuitry
B. Buffer registers
C. Multiple buses
D. Bridge circuits
26 Which types of transfers are supported by a computer's interconnection structure?
A. Memory to or from processor, I/O to or from processor, I/O to or from memory
B. I/O to or from processor, I/O to I/O, memory to or from processor
C. Memory to memory, memory to or from processor, I/O to or from processor
D, None of the others
27 The width of the address bus determines ........
A. The overall performance of the system
B. The number of bits can be transferred at a time
C. The maximum possible memory capacity of the system
28 The key advantage of multi-bus organizations is ........
A. Reduction in the number of cycles for execution
B. Increase in size of the registers
C. Better connectivity
29 To connect peripheral devices which require a direct connection with the processor we use .........
A. SCSI bus
B. PCI bus
D. ISA bus
D. Controllers
30 How much memory access would be needed to transfer a 64-bit instruction from memory to the CPU if the
CPU uses 8-bit data and 32-bit address?
A. 2
B. 4
C. 6
D. 8
31 With the given figure, which of the following statements is true?
A. For a write operation, the processor puts the data on the data lines at the start of the second cycle
B. For a read operation, the processor issues a read command at the start of the second cycle
C. The processor places a memory address on the address lines during the first clock cycle
D. All of the above
32 With the given figure, which of the following statements is false?
A. The memory decodes the address and responds by placing the data on the data line
B. The memory module asserts the acknowledged line to signal the processor that the data are available
C. The processor places address on the address line at the same time that it issues a read command
CHAPTER 4
1 refers to whether memory is internal or external to the computer.
a. Location
b. Access
c. Hierarchy
d. Tag
2 What is the high speed memory between the main memory and the CPU called?
a. Register Memory
b. Cache Memory
c. Storage Memory
d. Virtual Memory
3 The cache bridges the speed gap between … and …
a. RAM and ROM

b. RAM and Secondary memory
c. Processor and RAM
4 Which of the following storages may have an associative access method?
a. Main memory
b. Disks
c. Virtual Memory
d. Cache
5 Cache Memory refers to:
a. A cheap memory that can be plugged into the motherboard to expand main memory
b. A fast memory that is used to store recently accessed data
c. A reserved portion of main memory is used to save important data
d. A special area of memory on the chip that is used to save frequently uses constant
6 The reason for the implementation of the cache memory is
a. To increase the internal memory of the system

b. The difference in speeds of operation of the processor and memory
c. To reduce the memory access and cycle time
d. All of the above
7 The effectiveness of the cache memory is based on the property of
a. Locality of reference
b. Memory localization
c. Memory size
8 The temporal aspect of the locality of reference means
a. That the recently executed instruction will be executed soon

b. That the recently executed instruction is temporarily not referenced
c. That the recently executed instruction will be executed soon again
9 The spatial aspect of the locality of reference means
a. That the recently executed instruction is executed again next
b. That the recently executed will be executed again
c. That the recently executed instruction will be executed later time
d. That the instruction in close proximity of the instruction executed will be executed in future
10 Internal memory capacity is typically expressed in terms of .
a. hertz
b. nano
c. bytes
d. LOR
11 For internal memory, the is equal to the number of electrical lines into and out of the memory
module.
a. access time
b. unit of transfer
c. capacity
d. memory ratio
12 In the context of memory hierarchy which statement is correct?
a. Greater memory capacity, faster access time
b. Greater memory capacity, greater cost per pit
c. Faster access time, greater cost per pit
d. Faster access time, lower cost per pit
13 "Memory is organized into records and access must be made in a specific linear sequence" is a description
of .
a. sequential access
b. direct access
c. random access
d. associative
14 Individual blocks or records have a unique address based on physical location with .
a. associative
b. physical access
c. direct access
d. sequential access
15 For random-access memory, is the time it takes to perform a read or write operation, that is
the time from the instant that an address is presented to the memory to the instant that data have been
stored or made available for use.
a. memory cycle time

b. direct access
c. transfer rate
d. access time
16 The transfer between CPU and Cache is
a. Block transfer
b. Word transfer
c. Set transfer
d. Associative transfer
17 The transfer between main memory and disk is
a. Block transfer
b. Word transfer
c. Page transfer
d. Associative transfer
18 The consists of the access time plus any additional time required before a second access can
commence.
a. latency
b. memory cycle time
c. direct access
d. transfer rate
19 is the rate at which data can be transferred into or out of a memory unit. For random access
memory, it is equal to 1/(cycle time)
a. latency
c. direct access
d. transfer rate
20 The algorithm to remove and place new contents into the cache is called
a. Replacement algorithm
b. Renewal algorithm
c. Update
21 A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred
to as a .
a. disk cache
b. latency
c. virtual address
d. miss
22 A line includes a that identifies which particular block is currently being stored.
a. cache
b. hit
c. tag
d. locality
23 Whenever the data is found in the cache memory it is called as
a. hit
b. miss
c. error
d. found
24 is the simplest mapping technique and maps each block of main memory into only one
possible cache line.
a. Direct mapping
b. Associative mapping
c. Set associative mapping
25 overcomes the disadvantage of direct mapping by permitting each main memory block to be
loaded into any line of the cache.
a. Direct mapping
26 is a compromise that exhibits the strengths of both the direct and associative approaches while
reducing their disadvantages.
a. Direct mapping
27 When using the technique all write operations made to main memory are made to the cache
as well.
a. write back
b. LRU
c. write through
d. unified cache
28 In mapping, the data can be mapped anywhere in the Cache Memory.
a. Associative
b. Direct
c. Set Associative
d. Indirect
29 updates are made only in the cache. Portions of main memory are invalid and hence accesses by
I/O modules can be allowed only through the cache
a. write back
b. LRU
c. write through
d. unified cache
30 The key advantage of the design is that it eliminates contention for the cache between the
instruction fetch/decode unit and the execution unit.
a. logical cache
b. split cache
c. unified cache
d. physical cache
31 The Pentium 4 component executes micro-operations, fetching the required data from the L1
data cache and temporarily storing results in registers.
a. fetch/decode unit
b. out-of-order execution logic
c. execution unit
d. memory subsystem
32 In reference to access time to a two-level memory, a occurs if an accessed word is not found in
the faster memory.
a. miss
b. hit
c. line
d. tag
33 A logical cache stores data using .
a. physical addresses
b. virtual addresses
c. random addresses
d. none of the above
34 The virtual memory bridges the size and speed gap between … and …
a. RAM and ROM

b. Processor and RAM
c. RAM and Secondary Memory
35 The processor accesses the cache directly without going through the MMU and a physical cache stores
data using main memory
a. physical addresses
b. virtual addresses
c. random addresses
36 To get the physical address from the logical address generated by CPU we use
a. MAR
b. MMU
c. Overlays
d. TLB
No. CHAPTER 5
1 Which properties do all semiconductor memory cells share?
a. they exhibit two stable states which can be used to represent binary 1 and 0
b. they are capable of being written into to set the state
c. they are capable of being read to sense the state
d. all of the above
2 One distinguishing characteristic of memory that is designated as is that it is possible to both to
read data from the memory and to write new data into the memory easily and rapidly.
a. RAM
b. ROM
c. EPROM
d. EEPROM
3 With RAM, which of the following statements is true:
a. It is not volatile
b. DRAM is not from flip-flops
c. SRAM is made from capacitors
d. A place to store information that the computer is processing
4 What are the key properties of the semiconductor memory cell?
A. They exhibit two states, which can be represented by 0 or 1

B. They are capable of being written into to set the state
C. They can be read to sense the state
D. All of the above
5 With RAM, which of the following statements is false:
a. DRAM is made from flip-flops

b. DRAM is made from capacitors
c. SRAM is made from flip-flops
d. SRAM does not need to be refreshed
6 RAM is called DRAM (Dynamic RAM) when …
a. It is always moving around data

b. It requires periodic refreshing
c. It can do several things simultaneously
7
The standard SRAM chips are costly as …
A. They use highly advanced micro-electronic devices.
B. They house 6 transistor per chip.
C. They require specially designed PCB’s.
8 The computer input/output system does not include simultaneously the following devices:
a. ROM, RAM, registers
b. Monitor, RAM, printer
c. CPU, mouse, photo scanner
d. Magnetic discs, speakers, CD-ROM
9 Which of the following memory types are nonvolatile?
a. erasable PROM
b. programmable ROM
c. flash memory
d. all of the above
10 In a , binary values are stored using traditional flip-flop logic-gate configurations and it is used
for cache memory
a. ROM
b. SRAM
c. DRAM
d. RAM
11
With SRAM memory chips 16Kx8bit, which of the following statements is wrong:
A. There are 14 address lines
B. There are 8 data lines
C. The address lines are: A0 – A13
D. The address lines are: A0 – A14
12 With the SRAM memory 64K x 4-bit, which of the following statements is true:
a. The address lines are: A0 -> A15

b. The address lines are: D0 -> D15
c. The data lines are: A0 -> A3
d. The data lines are: D0 -> D8
13 SDRAM stands for
a. Static dynamic random access memory
b. System dynamic random access memory
c. Synchronous dynamic random access memory
d. Syndrome dynamic random access memory
14 A contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot
have new data written into it.
a. RAM
b. SRAM
c. ROM
d. flash memory
15 ROMs are used to
a. Record large size data, unchanged over time

b. Record small size data, updated regularly
c. Record the system subroutine
d. Contain the computer control program
16 When only a small number of ROMs with a particular memory content are needed and less expensive
alternative is .
a. RAM
b. SRAM
c. PROM
d. flash memory
17 A requires periodic change refreshing to maintain data storage and is used for main memory.
a. ROM
b. SRAM
c. DRAM
d. RAM
18
Part of the operating system is usually stored in ROM so that it can be used to boot up the computer. ROM
is used rather than RAM because:
A. ROM chips are faster than RAM
B. ROM chips are not volatile
C. ROM chips are cheaper than RAM chips
19 With the microchip is organized so that a section of memory cells are erased in a single action.
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
20 is read and written electrically as with PROM. However, before a write operation, all storage cells
must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation.
a. flash memory
b. SDRAM
c. EPROM
d. EEPROM
21 A more attractive form of read-mostly memory is . This is a read-mostly memory that can be written
into at any time without erasing prior contents; only the byte or bytes addressed are updated
a. flash memory
b. SDRAM
c. EPROM
d. EEPROM
22 can be caused by harsh environmental abuse, manufacturing defects, and wear.
a. SEC errors
b. Hard errors
c. Syndrome errors
d. Soft errors
23
With ROM, which of the following statements is false:
A. There are all 5 types of ROMs
B. Can be use ultraviolet light to erase EPROM
C. EPROM be written into without erasing prior contents
24 can be caused by power supply problems or alpha particles.
a. Soft errors
b. AGT errors
c. Hard errors
d. SEC errors
25
If the syndrome for the Hamming code contains one and only one bit set to 1:
A. No error has been detected

B. An error has occurred in one of the 4-check bits, and no correction is necessary
C. An error is occurred and the numerical value of the syndrome indicates the position of the data bit in
error
26
If the syndrome for the Hamming code contains more than one bit set to 1:

C. An error is occurred and the numerical value of the syndrome indicates the position of the data bit in
error
E. None of the above
27 The exchanges data with the processor synchronized to an external clock signal and running at
the full speed of the processor/memory bus without imposing wait states.
a. DDR-DRAM
b. SDRAM
c. CDRAM
28 , developed by Mitsubishi [HIDA90, ZHAN01], integrates
a small SRAM cache (16 Kb) onto a generic DRAM chip.
a. DDR-DRAM
b. SDRAM
c. CDRAM
29 can send data to the processor twice per clock cycle.
a. CDRAM
b. SDRAM
c. DDR-DRAM
d. RDRAM
30 increases the data transfer rate by increasing the operational frequency of the RAM chip and
by increasing the prefetch buffer from 2 bits to 4 bits per chip.
a. DDR2
b. RDRAM
c. CDRAM
d. DDR3
31 increases the prefetch buffer size to 8 bits.
a. CDRAM
b. RDRAM
c. DDR3
d. all of the above
32 Theoretically, a DDR module can transfer data at a clock rate in the range of MHz.
a. 200 to 600
b. 400 to 1066
c. 600 to 1400
d. 800 to 1600
33 A module transfers data at a clock rate of 400 to 1066 MHz
a. DDR
b. DDR3
c. DDR2
d. DDR SDRAM
34 A DDR3 module transfers data at a clock rate of MHz.
a. 600 to 1200
b. 800 to 1600
c. 1000 to 2000
d. 1500 to 3000
35
A computer’s memory is composed of 4K words of 64 bits each. How many total bits in memory?
A. 128000
B. 256000
C. 262144
D. 131072
36
If a system is 32-bit machine, then the length of each word will be ...........
A. 4 bytes
B. 8 bytes
C. 16 bytes
D. 12 bytes
37
A 16 bit address generates an address space of ............... locations
A. 1024
B. 65,356
C. 2 ^ 32
D. 16,777,216
38
In order to execute a program instructions must be transferred from memory along a bus to the CPU. If the
bus has 8 data lines, at most one 8-bit byte can be transferred at a time. How many memory access would
be needed in this case to transfer a 16-bit instruction from memory to the CPU.
A. 1
B. 2
C. 3
D. 4
39
The maximum addressing capacity of a microprocessor which uses 8-bit data & 16 bit address is
A. 64 KB
B. 4 GB
C. 16 MB
40 The enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible.
a. flash memory
b. Hamming code
c. Ram Bus
d. buffer( dem)
CHAPTER 6
1 Greater ability to withstand shock and damage, improvement in the uniformity of the magnet film surface to
increase disk reliability, and a significant reduction in overall surface defects to help reduce read-write
errors, are all benefits of .
a. magnetic read and write mechanisms

b. platters
c. the glass substrate
d. a solid state drive
2 Adjacent tracks are separated by .
a. sectors
b. gaps
c. pits
d. heads
3 Data are transferred to and from the disk in .
a. heads
b. gaps
c. pits
d. sectors
4 a relatively small device capable of reading from or writing to a portion of the platter rotating beneath
it
a. sectors
b. gaps
c. tracks
d. heads
5 The organization of data on the platter in a concentric set of rings, called .
a. tracks
b. gaps
c. sectors
d. heads
6 In most contemporary systems fixed-length sectors are used, with bytes being the nearly
universal sector size.
a. 64
b. 128
c. 256
d. 512
7 Scanning information at the same rate by rotating the disk at a fixed speed is known as the .
a. constant angular velocity

b. magneto-resistive
c. rotational delay
d. constant linear velocity
8 The disadvantage of is that the amount of data that can be stored on the long outer tracks is
only the same as what can be stored on the short inner tracks.
a. SSD
b. CAV
c. ROM
d. CLV
9 A disk is permanently mounted in the disk drive, such as the hard disk in a personal computer.
a. non-removable
b. movable-head
c. double sided
d. removable
10 When the magnetizable coating is applied to both sides of the platter the disk is then referred to as
.
a. multiple sided
b. substrate
c. double sided
d. all of the above
11 The set of all the tracks in the same relative position on the platter is referred to as a .
a. floppy disk
b. single-sided disk
c. sector
d. cylinder
12 The sum of the seek time and the rotational delay equals the , which is the time it takes to get
into position to read or write.
a. access time
b. gap time
c. transfer time
d. constant angular velocity
13 Once the head is in position, the read or writes operation is then performed as the sector moves under the
head; this is the data transfer portion of the operation; the time required for the transfer is
a. access time
b. gap time
c. transfer time
d. rotational delay
14 The time it takes for the beginning of the sector to reach the head is known as
a. access time
b. rotational delay
c. transfer time
d. gap time
15 is the standardized scheme for multiple-disk database design.
a. RAID
b. CAV
c. CLV
d. SSD
16 is a memory device made with solid-state components that can be used as a replacement for a hard
disk drive.
a. RAID
b. RAM
c. HDD
d. SSD
17 RAID level has the highest disk overhead of all RAID types.
a. 0
b. 1
c. 3
d. 5
18 A is a high-definition video disk that can store 25 G-bytes on a single layer on a single side.
a. DVD
b. DVD-R
c. DVD-RW
d. Blu-ray DVD
19 compressed representation of video information, as well as large volumes of other digital data and
the basic its, is read-only and it can store 17 G-bytes on a double-sided.
a. Blu-ray DVD
b. DVD-RW
c. DVD
d. CD-ROM
20 is when the disk rotates more slowly for accesses near the outer edge than for those near the
center.
a. Constant angular velocity (CAV)

b. Magneto- resistive
c. Constant linear velocity (CLV)
d. Seek time
21 The areas between pits are called .
a. lands
b. sectors
c. cylinders
d. strips
22
RAID level ....................... refers to disk arrays with striping but without any redundancy.
A. 0 B. 1
C. 2 D. 3
23
RAID level ........................ is also known as block-interleaved parity organization and uses block-level
striping and keeps a parity block on a separate disk.
A. 1 B. 2
C. 3 D. 4
24
RAID level ........................ consists of byte-level striping with dedicated parity.
A. 0 B. 1
C. 2 D. 3
25
RAID level 5 is also known as:
A. Bit-interleaved parity organization
B. Block-interleaved parity organization
C. Block-interleaved distributed parity
D. Memory-style ECC organization
26 The data can be accessed from the disk using ...........

A. Surface number B. Sector number
C. Track number D. All of the others
27
.................. is used to detect and correct the errors that may occur during data transfers.
A. ECC B. CRC
C. Checksum D. None of the others
28
The set of corresponding tracks on all surfaces of a stack of disks form a ...........
A. Cluster B. Cylinder
C. Group D. Set
29
The digital information is stored on the hard disk by ..........
B. Applying a suitable electric pulse.
C. Applying a suitable magnetic field.
D. Applying a suitable nuclear field.
E. By using optic waves.
CHAPTER 7
1 The contains logic for performing a communication function between the peripheral and the
bus.
a. I/O channel
b. I/O module
c. I/O processor
d. I/O command
2 The most common means of computer/user interaction is a .
a. keyboard/monitor
b. mouse/printer
c. modem/printer
d. monitor/printer
3 The I/O function includes a requirement to coordinate the flow of traffic between internal
resources and external devices.
a. cycle
b. status reporting
c. control and timing
d. data
4 An I/O module that takes on most of the detailed processing burden, presenting a high-level interface to the
processor, is usually referred to as an .
a. I/O channel
b. I/O command
c. I/O controller
d. device controller
5 An I/O module that is quite primitive and requires detailed control is usually referred to as an .
a. I/O command
b. I/O controller
c. I/O channel
d. I/O processor
6 The command causes the I/O module to take an item of data from the data bus and
subsequently transmit that data item to the peripheral.
a. control
b. test
c. read
d. write
7 The command is used to activate a peripheral and tell it what to do.
a. control
b. test
c. read
d. write
8 is when the DMA module must force the processor to suspend operation temporarily.
a. Interrupt
b. Thunderbolt
c. Cycle stealing
d. Lock down
9 The 8237 DMA is known as a DMA controller.
a. command
b. cycle stealing
c. interrupt
d. fly-by
10 is a digital display interface standard now widely adopted for computer monitors, laptop displays,
and other graphics and video interfaces.
a. DisplayPort
b. PCI Express
c. Thunderbolt
d. Infini Band
11 The layer is the key to the operation of Thunderbolt and what makes it attractive as a high-speed
peripheral I/O technology.
a. cable
b. application
c. common transport
d. physical
12 The Thunderbolt protocol layer is responsible for link maintenance including hot-plug detection
and data encoding to provide highly efficient data transfer.
a. cable
b. application
c. common transport
d. physical
13 The contains I/O protocols that are mapped on to the transport layer.
a. cable
b. application
c. common transport
d. physical
14 A is used to connect storage systems, routers, and other peripheral devices to an InfiniBand
switch.
a. target channel adapter

b. InfiniBand switch
c. host channel adapter
d. subnet
15 A connects InfiniBand subnets, or connects an InfiniBand switch to a network such as a local
area network, wide area network, or storage area network.
a. memory controller
b. TCA
c. HCA
d. router
16
………. register keeps tracks of the instructions stored in program stored in memory.
A. AR (Address Register) B. XR (Index Register)
C. PC (Program Counter) D. AC (Accumulator)
17
An interface that provides a method for transferring binary information between internal storage and
external devices is called as …
A. I/O interface B. Input interface
C. Output interface D. I/O bus
18
An interface that provides I/O transfer of data directly to or form the memory unit and peripheral is termed
as …
A. DDA B. Serial interface
C. BR D. DMA
19
External, or peripheral, devices include:
A. Human readable B. Machine readable
C. Communication D. All of the others
20
With the functions of an I/O module which of the following statements is false:
A. Control and timing
B. A module only connects to a peripheral device
C. Exchange information with the processor, with peripherals
D. Data buffers, error detection
21
I/O addressing methods:
A. Memory-mapped I/O
B. Isolated I/O
C. Both memory-mapped I/O and isolated I/O
22
In memory-mapped I/O…
A. The I/O devices and the memory share the same address space
B. The I/O devices have a separate address space
C. The memory and I/O devices have an associated address space
D. A part of the memory is specifically set aside for the I/O operation
23
With isolated I/O, ..
B. The I/O devices have a separate address space
24
There are three methods for performing I/O:
A. Interrupt-driven I/O, System-driven I/O, DMA
B. Interrupt-driven I/O, System-driven I/O, Programmed I/O
C. Programmed I/O, Interrupt-driven I/O, DMA
D. Programmed I/O, System-driven I/O, DMA
25
The method of accessing the I/O devices by repeatedly checking the status flags is …
A. Programmed I/O B. Memory-mapped I/O
C. I/O mapped D. None of the others
26
The method of synchronizing the processor with the I/O device in which the device sends a signal when it is
ready is …
A. Exceptions B. Signal handling
C. Interrupt-driven I/O D. DMA
27
The process where in the processor constantly checks the status flags is called as …
A. Polling B. Inspection
C. Reviewing D. Echoing
28
With Programmed I/O which of the following statements is false:
A. Use input/output commands in the program to exchange data with the I/O ports
B. Peripherals are active objects in data exchange
C. When executing the program, encountering input/output commands, the CPU controls data
exchange with peripherals
D. Peripherals are passive objects in data exchange
29
With Programmed I/O which of the following statements is true:
A. This is the simplest method to exchange data
B. This is the fastest method to data exchange
C. Complex circuit design
30
With Interrupt-driven I/O, which of the following statements is false:
A. Peripherals are the active object in data exchange
B. CPU does not have to wait for the availability of peripherals
C. CPU have to wait for the availability of I/O module
D. I/O module interrupt CPU when it is in ready state
31
With Interrupt-driven I/O, which of the following statements is true:
B. The method is fully processed by hardware
C. CPU is an active object in data exchange
D. The method is fully processed by software
32
The DMA differs from the interrupt mode by …
A. The involvement of the processor for the operation
B. The method accessing the I/O devices
C. The amount of data transfer possible
D. Both the involvement of the processor for the operation and the amount of data transfer possible
33
The DMA transfers are performed by a control circuit called as …
A. Device interface B. DMA controller
C. Data controller D. Over looker
34
In DMA transfers, the required signals and addresses are given by the …
A. Processor B. Device drivers
C. DMA controller D. The program itself
35
The technique whereby the DMA controller steals the access cycles of the processor to operate is called as
…
A. Fast conning B. Memory Con
C. Cycle stealing D. Memory stealing
CHAPTER 8
01. The operating system is an example of a computer ……….
A. Object B. File system
C. Program D. Desktop
02. Which of the following is the primary purpose of an operating system?
A. To make the most efficient use of the computer hardware
B. To allow people to use the computer
C. To keep systems programmers employed
D. To make computers easier to use
03. The key services provided by an OS:
A. Create and execute programs
B. Control access to I/O devices, files and system resources
C. Accounting, error detection and response
04. One of the function of operating system is it serves an interface between user and ……….
A. Software B. Hardware
C. Utilities D. Data ware
05. In an .............. system the user/programmer interacts directly with the computer, usually through a
keyboard/display terminal to request the execution of a job or to perform a transaction.
A. Batch B. Multiprogramming
C. Interactive D. None of the others
06. Which of the following is NOT a function of operating system?
A. Resource Manager B. Storage Manager
C. Process Manager D. Software Manager
07. Long-term scheduling is:
A. The decision to add which programs to the system for processes
B. The decision to add to the number of processes that are partially or fully in main memory
C. The decision as to which available process will be executed by the processor.
D. The decision as to which process's pending I/O request shall be handled by an available I/O device.
08. Medium-term scheduling is:
A. The decision as to which process's pending I/O request shall be handled by an available I/O device.
B. The decision as to which available process will be executed by the processor.
C. The decision to add to the number of processes that are partially or fully in main memory
D. The decision to add which programs to the system for processes
09. Short-term scheduling is:
10. What is a process?
A. A program in execution
B. A *.exe file
C. A executable file stored in external memory
11. What is the purpose of the process?
A. Multiprocessing B. Multiprogramming
C. Multicore D. All of the others
12. In the process state transition diagram, which state corresponding to a program is admitted by
the Long-term scheduler?
A. New B. Ready
C. Running D. Halted
13. In the process state transition diagram,............. will initialize the process, moving it to the ready
state.
A. Long-term scheduler B. Medium-term scheduler
C. Short-term scheduler D. None of the others
14. In the process state transition diagram, the transition from the READY state to the RUNNING
state indicates that:
A. A process was preempted by another process
B. A process has blocked for a semaphore or other operation
C. A process is done waiting for an I/O operation
D. A process was just created
15. The state corresponding to the process has terminated and will be destroyed by the OS is
called:
A. New B. Ready
16. Copying a process from memory to disk to allow space for other processes is called?
A. Page Fault B. Deadlock
C. Demand Paging D. Swapping
17. The purpose of swapping is:
A. To remove processes not in a ready state
B. To provide for efficient use of main memory for processes execution
C. To add processes in a ready state to main memory
18. Swapping is executed by ..........
19. If a process may be dynamically assigned to different locations in main memory, what is
implication for the addressing mechanism?
A. The addressing mechanism must keep track of the physical addresses of the process
B. The addressing mechanism must keep track of the logical addresses used for swapping out the
process
C. The addressing mechanism must keep track of the physical addresses of the process, as well as
the logical addresses used for swapping out the process
20. The purpose of a TLB is:
A. To cache page translation information
B. To cache frequently used data
C. To hold register values while a process is waiting to be run
D. To hold the start and length of the page table
2 The scheduler determines which programs are admitted to the system for processing.
a. long-term
b. medium-term
c. short-term
d. I/O
3 The OS maintains a for each process that shows the frame location for each page of the
process.
a. kernel
b. page table
c. TLB
d. logical address
4 A is a collection of memory regions.
a. APX
b. nucleus
c. domain
d. page table
5 With the virtual address is the same as the physical address.
a. unsegmented unpaged memory

b. unsegmented paged memory
c. segmented unpaged memory
d. segmented paged memory
6 Virtual memory schemes make use of a special cache called a for page table entries.
a. TLB
b. HLL
c. VMC
d. SPB
7 is when the processor spends most of its time swapping pages rather than executing
instructions.
a. Swapping
b. Thrashing
c. Paging
d. Multitasking
8 A is an actual location in main memory.
a. logical address
b. partition address
c. base address
d. physical address
9 The scheduler is also known as the dispatcher.
a. long-term
b. medium-term
c. short-term
d. I/O
10 A is a special type of programming language used to provide instructions to the monitor.
a. job control language

b. multi-program
c. kernel
d. utility
11 A system works only one program at a time.
a. batch
b. uni-programming
c. kernel
d. privileged instruction
12 The gives a program access to the hardware resources and services available in a system
through the user instruction set architecture supplemented with high-level language library calls.
a. JCL
b. ISA
c. ABI
d. API
13 The defines the system call interface to the operating system and the hardware resources and
services available in a system through the user instruction set architecture.
a. HLL
b. API
c. ABI
d. ISA
14 The defines the repertoire of machine language instructions that a computer can follow.
a. ABI
b. API
c. HLL
d. ISA
15 Facilities and services provided by the OS that assist the programmer in creating programs are in the form
of programs that are not actually part of the OS but are accessible through the OS.
a. utility
b. multitasking
c. JCL
d. logical address
16 The is a program that controls the execution of application programs and acts as an interface
between applications and the computer hardware.
a. job control language

b. operating system
c. batch system
d. nucleus
CHAPTER 11
1 The operand yields true if and only if both of its operands are true.
a. XOR
b. OR
c. AND
d. NOT
2
It is the bitwise operation and also includes AND, OR and NOT, XOR, and XNOR gates.
A. Operands B. Arithmetic
C. Characters D. Logical
3 The operation yields true if either or both of its operands are true.
a. NOT
b. AND
c. NAND
d. OR
4 A is an electronic circuit that produces an output signal that is a simple Boolean operation on its
input signals.
a. gate
b. decoder
c. counter
d. flip-flop
5 Which of the following is a functionally complete set?
a. AND, NOT
b. NOR
c. AND, OR, NOT
d. all of the above
6 For more than four variables an alternative approach is a tabular technique referred to as the
method.
a. DeMorgan
b. Quine-McCluskey
c. Karnaugh map
d. Boole-Shannon
7 are used in digital circuits to control signal and data routing.
a. Multiplexers
b. Program counters
c. Flip-flops
d. Gates
8 is implemented with combinational circuits.
a. Nano memory
b. Random access memory
c. Read only memory
d. No memory
9 The exists in one of two states and, in the absence of input, remains in that state.
a. assert
b. complex PLD
c. decoder
d. flip-flop
10 The flip-flop has two inputs and all possible combinations of input values are valid.
a. J-K
b. D
c. S-R
d. clocked S-R
11 A accepts and/or transfers information serially.
a. S-R latch
b. shift register
c. FPGA
d. parallel register
12 Counters can be designated as .
a. asynchronous
b. synchronous
c. both asynchronous and synchronous
d. neither asynchronous or synchronous
13 CPUs make use of counters, in which all of the flip-flops of the counter change at the same
time.
a. synchronous
b. asynchronous
c. clocked S-R
d. timed ripple
14 The table provides the value of the next output when the inputs and the present output are
known, which is exactly the information needed to design the counter or any sequential circuit.
a. excitation
b. Kenough
c. J-K flip-flop
d. FPGA
No. CHAPTER 12
1
It's all about the instruction length (in bits), number of addresses, size of various fields, and so on.
B. Operation Repertoire B. Instruction Format
C. Opcodes D. Logic Instructions
2
It is a collection of different instructions that the processor can execute, it also provides the
commands to the processor, to tell it what it needs to do.
A. Instruction Set B. Operation Code
C. Immediate D. Processor Register
3
The one which is inputted in an operation and are also represented symbolically.
A. Numbers B. Absolute
C. Mnemonics D. Operands
4
It's an operation that adds 1 to the operand.
A. Increment B. Negate
C. Decrement D. Registers
5
This is the common form of data which is text or character strings.
A. Addresses B. Numbers
C. Characters D. Conversion
6
Which category of microprocessor instructions detect the status conditions in registers and
accordingly exhibit the variations in program sequence on the basis of detected results?
A. Transfer Instructions B. Operation Instructions
C. Control Instructions D. All of the others
7
The push and pop instructions belonging to the category of transfer instructions of microprocessor
perform data transformation between .
A. Two registers
B. Processor register and memory stack
C. Processor register and interface register
D. Interface register and memory word
8
The addressing mode, which uses the PC instead of a general purpose register is
A. Indexed with offset B. Relative
C. Direct D. Both Indexed with offset & Direct
9
The addressing mode, where you directly specify the operand value is .
A. Immediate B. Direct
C. Definite D. Relative
10
The addressing mode which makes use of in-direction pointers is
A. Indirect addressing mode B. Index addressing mode
C. Relative addressing mode D. Offset addressing mode
11
Which addressing mode execute its instructions within CPU without the necessity of reference
memory for operands?
A. Implied Mode B. Immediate Mode
C. Direct Mode D. Register Mode
12
Which register holds the address for a stack whose value is supposed to be directed at the topmost
position?
A. Stack Pointer B. Stack Register
C. Both Stack Pointer & Stack Register D. None of the others
13
What is another name of memory stack especially given for the fundamental function performed byit?
A. Last-in-first-out (LIFO) B. First-in-last-out (FILO)
C. First-in-first-out (FIFO) D. Last-in-last-out (LILO)
14
What does the last instruction of each subroutine that transfer the control to the instruction in the
calling program with temporary address storage called as?
A. Jump to subroutine B. Branch to subroutine
C. Return from subroutine D. Call subroutine
15
refers to the process of initiating instruction execution in the processor's functional units.
A. Instruction issue B. In-order issue
C. Out-of-order issue D. Procedural issue
16
Which parameter of computer determines its power to do various operations on data items?
A. Instruction set B. Memory size
C. Assembly language D. Application language
17 The specifies the operation to be performed.
a. source operand reference

b. opcode
c. next instruction reference
d. processor register
18 A(n) expresses operations in a concise algebraic form using variables.
a. opcode
b. high-level language
c. machine language
d. register
19 There must be instructions for moving data between memory and the registers.
a. branch
b. logic
c. memory
d. I/O
20 instructions operate on the bits of a word as bits rather than as numbers, providing capabilities
for processing any other type of data the user may wish to employ.
a. Logic
b. Arithmetic
c. Memory
d. Test
21 instructions provide computational capabilities for processing number data.
a. Boolean
b. Logic
c. Memory
d. Arithmetic
22 instructions are needed to transfer programs and data into memory and the results of
computations back out to the user.
a. I/O
b. Transfer
c. Control
d. Branch
23 The x86 data type that is a signed binary value contained in a byte, word, or double-word, using twos
complement representation is .
a. general
b. ordinal
c. integer
d. packed BCD
24 The most fundamental type of machine instruction is the instruction.
a. conversion
b. data transfer
c. arithmetic
d. logical
25 The instruction includes an implied address.
a. skip
b. rotate
c. stack
d. push
26 Which of the following is a true statement?
a. a procedure can be called from more than one location

b. a procedure call can appear in a procedure
c. each procedure call is matched by a return in the called program
d. all of the above
27 The entire set of parameters, including return address, which is stored for a procedure invocation is referred
to as a .
a. branch
b. stack frame
c. pop
d. push
28 Which ARM operation category includes logical instructions (AND, OR, XOR), add and subtract
instructions, and test and compare instructions?
a. data-processing instructions
b. branch instructions
c. load and store instructions
d. extend instructions
29 Which data type is defined in MMX?
a. packed byte
b. packed word
c. packed double-word
d. all of the above
30 A branch instruction in which the branch is always taken is .
a. conditional branch
b. unconditional branch
c. jump
d. bi-endian
CHAPTER 13
1 The advantage of is that no memory reference other than the instruction fetch is required to
obtain the operand.
a. direct addressing
b. immediate addressing
c. register addressing
d. stack addressing
2 The principal advantage of addressing is that it is a very simple form of addressing.
a. displacement
b. register
c. stack
d. direct
3 has the advantage of large address space, however it has the disadvantage of multiple
memory references.
a. Indirect addressing
b. Direct addressing
c. Immediate addressing
d. Stack addressing
4 The advantages of addressing are that only a small address field is needed in the instruction
and no time-consuming memory references are required.
a. direct
b. indirect
c. register
d. displacement
5 has the advantage of flexibility, but the disadvantage of complexity.
a. Stack addressing
b. Displacement addressing
c. Direct addressing
d. Register addressing
6 For , the address field references a main memory address and the referenced register contains
a positive displacement from that address.
a. indexing
b. base-register addressing
c. relative addressing
d. all of the above
7 Indexing performed after the indirection is .
a. relative addressing
b. auto-indexing
c. post-indexing
d. pre-indexing
8 For the mode, the operand is included in the instruction.
a. immediate
b. base
c. register
d. displacement
9 The only form of addressing for branch instructions is addressing.
a. register
b. relative
c. base
d. immediate
10 Which of the following interrelated factors go into determining the use of the addressing bits?
a. number of operands
b. number of register sets
c. address range
d. all of the above
11 is a principle by which two variables are independent of each other.

a. Opcode
b. Orthogonality
c. Completeness
d. Auto-indexing
12 The was designed to provide a powerful and flexible instruction set within the constraints of a
16-bit minicomputer.
a. PDP-1
b. PDP-8
c. PDP-11
d. PDP-10
13 The byte consists of three fields: the Scale field, the Index field and the Base field.
a. SIB
b. VAX
c. PDP-11
d. Mod-R/M
14 All instructions in the ARM architecture are bits long and follow a regular format.
a. 8
b. 16
c. 32
d. 64
15 is a design principle employed in designing the PDP-10 instruction set.
a. Orthogonality
b. Completeness
c. Direct addressing
d. All of the above
16 Addressing mode used in instruction SUB r1, r2 is .

A. Immediate B. Indirect
C. Base D. Register
17 In immediate addressing mode the operand is placed .
A. In the CPU register

B. After OP code in the instruction
C. In memory
D. In stack
18 How many address lines are needed to address each memory location in a 2048 X 4 memory chip?
A. 10 B. 11
C. 8 D. 12
19
converts the programs written in assembly language into machine instructions
A. Machine compiler B. Interpreter
C. Assembler D. Converter
20 To get the physical address from the logical address generated by CPU we use ...........
A. MAR B. MMU
C. Overlays D. TLB
21
22
23
24
CHAPTER 14
1 are a set of storage locations.
a. Processors
b. PSWs
c. Registers
d. Control units
2 The controls the movement of data and instructions into and out of the processor.
a. control unit
b. ALU
c. shifter
d. branch
3 are bits set by the processor hardware as the result of operations.
a. MIPS
b. Condition codes
c. Stacks
d. PSWs
4 registers may be used only to hold data and cannot be employed in the calculation of an operand
address.
a. General purpose
b. Data
c. Address
d. Condition code
5 The contains the address of an instruction to be fetched.
a. instruction register
b. memory address register
c. memory buffer register
d. program counter
6 The determines the opcode and the operand specifiers.
a. decode instruction
b. fetch operands
c. calculate operands
d. execute instruction
7 is a pipeline hazard.
a. Control
b. Resource
c. Data
d. All of the above
8 A hazard occurs when there is a conflict in the access of an operand location.
a. resource
b. data
c. structural
d. control
9 A is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline
and containing the n most recently fetched instructions in sequence.
a. loop buffer
b. delayed branch
c. multiple stream
d. branch prediction
10 The is a small cache memory associated with the instruction fetch stage of the pipeline.
a. dynamic branch
b. loop table
c. branch history table
d. flag
11 The stage includes ALU operations, cache access, and register update.
a. decode
b. execute
c. fetch
d. write back
12 is used for debugging.
a. Direction flag
b. Alignment check
c. Trap flag
d. Identification flag
13 The ARM architecture supports execution modes.
a. 2
b. 8
c. 11
d. 7
14 The OS usually runs in .
a. supervisor mode
b. abort mode
c. undefined mode
d. fast interrupt mode
15 The contains a word of data to be written to memory or the word most recently read.
a. MAR
b. PC
c. MBR
d. IR
16
The situation in which the second instruction needs data produced by the first instruction to executeis
referred to as .
A. True data dependency B. Output dependency
C. Procedural dependency D. Anti-dependency
17
The instructions following a branch have a on the branch and cannot be executed until
thebranch is executed.
A. Anti-dependency B. Procedural dependency
C. Output dependency D. True data dependency
18 Instead of the first instruction producing a value that the second instruction uses, with
the second instruction destroys a value that the first instruction uses.
A. In-order issue B. Resource conflict
C. Anti-dependency D. Out-of-order completion
19
Which of the following is a hardware technique that can be used in a superscalar processor to
enhance performance?
A. Duplication of resources B. Out-of-order issue
C. Renaming registers D. All of the others
20
- Statement I: Register renaming eliminates anti-dependencies and output dependencies.
- Statement II: Out-of-order completion requires more complex instruction issue logic than in-order
completion.
A. Both the statements are true B. Statement I is true
C. Statement II is true D. Both the statements are false
21 A processor performing fetch or decoding of different instruction during the execution of another
instruction is called .
A. Super-scaling B. Pipe-lining
C. Parallel Computation D. None of the others
22
The periods of time when the pipeline, or some portion of the pipeline, is idle is called as .
A. Hazards B. Stalls
C. Bubbles D. Stalls or Bubbles
23 exists when instructions in a sequence are independent and thus can be executed inparallel by
overlapping.
A. Flow dependency B. Instruction-level parallelism
C. Machine parallelism D. Instruction issue
CHAPTER 15
1 determines the control and pipeline organization.
a. Calculation
b. Execution sequencing
c. Operations performed
d. Operands used
2 The Patterson study examined the dynamic behavior of programs, independent of the
underlying architecture.
a. HLL
b. RISC
c. CISC
d. all of the above
3 is the fastest available storage device.
a. Main memory
b. Cache
c. Register storage
d. HLL
4 The first commercial RISC product was .
a. SPARC
b. CISC
c. VAX
d. the Pyramid
5 instructions are used to position quantities in registers temporarily for computational operations.
a. Load-and-store
b. Window
c. Complex
d. Branch
6 The instruction location immediately following the delayed branch is referred to as the .
a. delay load
b. delay file
c. delay slot
d. delay register
7 A instruction can be used to account for data and branch delays.
a. SUB
b. NOOP
c. JUMP
d. all of the above
8 A tactic similar to the delayed branch is the , which can be used on LOAD instructions.
a. delayed load
b. delayed program
c. delayed slot
d. delayed register
9 The MIPS R4000 uses bits for all internal and external data paths and for addresses, registers,
and the ALU.
a. 16
b. 32
c. 64
d. 128
10 All MIPS R series processor instructions are encoded in a single word format.
a. 4-bit
b. 8-bit
c. 16-bit
d. 32-bit
11 A architecture is one that makes use of more, and more fine-grained pipeline stages.
a. parallel
b. super-pipelined
c. superscalar
d. hybrid
12 The R4000 can have as many as instructions in the pipeline at the same time.
a. 8
b. 10
c. 5
d. 3
13 SPARC refers to an architecture defined by .
a. Microsoft
b. Apple
c. Sun Microsystems
d. IBM
14 The R4000 pipeline stage where the instruction result is written back to the register file is the
stage.
a. write back
b. tag check
c. data cache
d. instruction execute
15
Which types of programmers should be aware of instruction set architecture? (Select all correct
answers)
A. Application Programmer B. System Programmer
C. Compiler Designer D. HLL
16
Programs written in assembly language
A. Are not portable
B. Make use of mnemonics
C. Run faster and require less storage space than those written in HLLs
17
Which of the following is/are used in translating HLLs?
A. Compilers only
B. Compilers, Interpreters and Assemblers
C. Compilers and Interpreters
D. Compilers and Assemblers
18
If a HLL program is to be run a number of times, .
A. An interpreter can produce object code that may be saved and run straight away
B. An interpreter would have to translate it each time it is run
C. It is best to use an assembler
D. An interpreter would translate it once and then produce object code that can be saved and
afterwardsrun directly (without needing further translation)
19
The essence of the approach is the ability to execute instructions independently
andconcurrently in different pipelines.
A. Scalar B. Branch
C. Superscalar D. Flow dependency
20
The Sun microsystems processors usually follow architecture.
A. CISC B. ISA
C. ULTRA SPARC D. RISC
21
Which computer architecture was the first to implement pipe-lining?
A. ISA B. CISC
C. RISC D. ANNA
22
Which computer architecture aimed at reducing the number of instructions per program?
A. CISC B. RISC
C. ISA D. ANNA
23
Both CISC and RISC architectures have been developed to minimize what?
A. Cost B. Time delay
C. Semantic gap D. All of the others
24
is a way of increasing the efficiency of the pipeline by making use of a branch that does nottake effect
until after execution of the following instruction.
A. Delayed branch B. Delayed load
C. Unrolling D. None of the others
25
can improve performance by reducing loop overhead, increasing instruction parallelism byimproving
pipeline performance, and improving register, data cache, or TLB locality.
26
CISC stands for ..
A. Complete Instruction Sequential Compilation
B. Computer Integrated Sequential Compiler
C. Complex Instruction Set Computer
D. Complex Instruction Sequential Compilation
01. Computer architecture refers to (Select all correct answers):

A. Design idea
02. Computer organization refers to (Select all correct answers):
A. Design idea
03. When considering whether a computer has a multiply instruction, we are referring to:
A. Computer organization B. Computer architecture
C. Computer hardware D. Computer software
04. When considering the memory technology used, we are referring to:
A. Computer hardware B. Computer software
C. Computer organization D. Computer architecture
05. Software compatibility, in point of view of the architecture, want to mention that:
A. Ability to use old software on new machines
B. Ability to use new software on old machines
C. Ability to use old software on new machines that belong to the same architecture as the old one
D. Ability to use new software on old machines that belong to the same architecture with new machines
06. Who are interested in computers with architectural look?
C. HLL Programmers D. All of the others
07. Who are interested in computers with organizational look?
A. Computer Designer B. Compiler Designer
C. System Programmer D. None of the others
08. - Statement I: Structure is the way in which the components are interrelated.
- Statement II: Function is the operation of each individual component as part of the structure.
A. Statement I is true B. Statement II is true
C. Both the statements are true D. Both the statements are false
09. The basic functions of the computer:

A. Data storage, run programs, connect to peripherals, access memory
B. Data movement, control, execute instructions, data processing
C. Data storage, data movement, data processing, control
D. Control, data storage, perform calculations, connect to the internet
10. The basic components of the computer:
A. RAM, CPU, hard drive, system interconnection
B. Memory system, system interconnection, ROM, keyboard
C. Memory system, CPU, monitor, mouse
D. Memory system, CPU, I/O, system interconnection
11. The main structured components of a processor (Not including internal interconnection):
A. Control unit, registers, I/O ports
B. Control unit , ALU, registers
C. Registers, DACs, control unit
D. ALU, registers, I/O ports
12. The memory system of computers include:
A. Cache, external memory
B. External memory, ROM
C. Optical disc, internal memory
D. Internal memory, external memory
E. The computer input/output system do not include simultaneously the following devices:
F. ROM, RAM, registers
G. Monitor, RAM, printer
H. CPU, mouse, photo scanner
I. Magnetic discs, speakers, CD-ROM
13. A common example of system interconnection is by means of a .......... , consisting of a number of
conducting wires to which all the other components attach.
A. Address Bus B. Data Bus
C. System Bus D. Control Bus
14. In the computer, there are the following types of system interconnections:
A. Instruction, function, control
B. Control, data, address
C. Data, dependen, control
D. Data, control, auxiliary
01. Another word for the CPU is …

A. Executer B. Microprocessor
C. Microchip D. Decoder
02. Which was an early mainframe computer?
A. ENIAC B. UNIC
C. BRAINIA D. FUNTRIA
03. In the concept of "stored program", the computer fetches instructions from:
A. Memory B. The opening/closing of electrical switches made by
theoperator
C. Hard disk D. Program
04. The concept of "stored program" allows:
A. Many algorithms can be implemented inside the machine without having to rewiring
B. The program can be altered directly through the values stored in memory
C. Reduce time of program execution
05. So far, computers have grown through:
A. 6 generations B. 5 generations
C. 4 generations D. 3 generations
06. During the development process of the computer, which of the following statements is true:
A. The first generation uses transistors
B. The third generation uses transistor
C. The first generation uses vacuum tube
D. The fourth generation uses SSI and MSI
07. During the development process of the computer, which of the following statements is false:
A. The second generation uses transistors
B. The third generation uses transistor
C. The first generation uses vacuum tube
D. The fourth generation uses integrated circuit
08. Circuit consisting of different electronic components and connections in them is called as:
A. Integrated circuit B. Interrelated circuit
C. Inverting circuit D. Reversing circuit
09. A silicon piece with a circuit on it is called:
A. Chip B. Circuit
C. Logical gate D. Circuit network
10. According to Moore's Law, the number of transistors will double after each:
A. 16 months B. 18 months
C. 20 months D. 22 months
11. Which parameters in a computer family are similar or identical? (Select all correct answers)
A. Instruction set B. Operating system
C. Speed D. Number of I/O ports
12. Which parameters in a computer family are increased from old to new machines?
A. Speed B. Memory size
C. Cost D. All of the others
13. The key factor/s in commercial success of a computer is/are............ (Select all correct answers)
A. Performance B. Cost
C. Speed D. All of the others
14. The main objective of the computer system is:
A. To provide optimal power operation.
B. To provide best performance at low cost.
C. To provide speedy operation at low power consumption.
D. All of the others.
15. To continue to increase performance, what is the current processor development trend? (Select
allcorrect answers)
A. Increasing clock rate
B. Increasing number of transistors on a single chip
C. Building a more complex processor
D. Multicore (placing multiple processors on the same chip)
01. The main structured components of a processor (not including internal interconnection):
A. Control unit, registers, I/O ports B. Control unit , ALU, registers
C. Registers, DACs, control unit D. ALU, registers, I/O ports
02. Hardware devices that are not part of the main computer system and are often added later to
thesystem:
A. Peripheral B. Clipart
C. Highlight D. Execute
03. The device which is used to connect a peripheral to a bus is called:
A. Control Register B. Interface
C. Communication Protocol D. None of the others
04. The internal components of the processor are connected by …
A. Processor intra-connectivity circuitry
B. Processor bus
C. Memory bus
D. Rambus
05. The CPU of a computer takes instructions from memory and executes them. This process is called:
A. Load B. Time Sequence
C. Execution D. Fetch-Execute Cycle
06. A basic instruction that can be interpreted by computer has:
A. Operand and opcode B. Decoder and Accumulator
C. Sequence register and decoder D. None of the others
07. Instruction for computer should specify:
A. What operation to be performed
B. Where to fetch instructions and operands
C. Where to store results
08. In which cycle the memory is read and the contents of memory at the address contained in the
PCregtister are loaded into into IR?
A. Execution Cycle B. Memory Cycle
C. Fetch Cycle D. Decode Cycle
09. The decoded instruction is stored in …
A. IR B. PC
C. Registers D. MDR
10. If any instruction consists any arithmetic operation, data is transferred to:
A. Quantitative unit B. Qualitative unit
C. Arithmetic and logical unit D. Central processing unit
11. Interrupts can be generated in response to …
A. Detected program errors such as arithmetic overflow or division by zero
B. Detected hardware faults
C. Input/Output activities
12. When the processor is executing the program, if there are interrupts (not prohibited) sent to it,
thenit:
A. Complete the program, then execute the interrupt
B. Interrupt rejection, not serving
C. Serve interrupts immediately, then execute the program
D. Complete the current instruction, then execute the interrupt, finally return to continue the program
13. Types of transfers are supported by a computer's interconnection structure:
A. Memory to memory, memory to or from processor, I/O to or from processor
B. Memory to or from processor, I/O to or from processor, I/O to or from memory
C. I/O to or from processor, I/O to I/O, memory to or from processor
14. The main advantage of multiple bus organisation over single bus is:
A. Reduction in the number of cycles for execution
B. Increase in size of the registers
C. Better Connectivity
15. are used to over come the difference in data transfer speeds of various devices.
A. Speed enhancing circuitory B. Bridge circuits
C. Multiple Buses D. Buffer registers
Explanation: By using buffer registers, the processor sends the data to the I/O device at the processor
speedand the data gets stored in the buffer. After that the data gets sent to or from the buffer to the
devices at the device speed.
02. Cache memory refers to:

A. A cheap memory that can be plugged into the mother board to expand main memory
B. A fast memory that is used to store recently accessed data
C. A reserved portion of main memory used to save important data
D. A special area of memory on the chip that is used to save frequently used constants
03. The reason for the implementation of the cache memory is:
A. To increase the internal memory of the system
B. The difference in speeds of operation of the processor and memory
C. To reduce the memory access and cycle time
04. The effectiveness of the cache memory is based on the property of
…
A. Locality of reference B. Memory localisation
C. Memory size D. None of the others
Explanation: This means that the cache depends on the location in the memory that is referenced often.
05. The temporal aspect of the locality of reference means:
A. That the recently executed instruction wont be executed soon
B. That the recently executed instruction is temporarily not referenced
C. That the recently executed instruction will be executed soon again
06. The spatial aspect of the locality of reference means:
A. That the recently executed instruction is executed again next
B. That the recently executed wont be executed again
C. That the instruction executed will be executed at a later time
D. That the instruction in close proximity of the instruction executed will be executed in future
Explanation: The spatial aspect of locality of reference tells that the nearby instruction is more likely to
be executed in future.
07. An address in main memory is called:
A. Physical address B. Logical address
C. Memory address D. Word address
08. The cache bridges the speed gap between ………. and ……….
A. RAM and ROM B. RAM and Secondary memory
C. Processor and RAM D. None of the others
Explanation: <numeric> The Cache is a hardware implementation to reduce the access time
forprocessor operations.
09. The virtual memory bridges the size and speed gap between ………. and ……….
A. RAM and ROM B. RAM and Secondary memory
C. Processor and RAM D. None of the others
Explanation: <numeric> The virtual memory basically works as an extension of the RAM.
10. To get the physical address from the logical address generated by CPU we use ……….
A. MAR B. MMU
C. Overlays D. TLB
Explanation: Memory Management Unit, is used to add the offset to the logical address generated
bythe CPU to get the physical address.
10. The correspondence between the main memory blocks and the cache memory lines is given by …
A. Hash function B. Mapping function
C. Locale function D. Assign function
Explanation: The mapping function is used to map the contents of the memory to the cache.
11. The method of mapping the consecutive memory blocks to consecutive cache lines is called
………….
A. Set associative B. Associative
C. Direct D. Indirect
Explanation: This method is most simple to implement as it involves direct mapping of memory blocks.
12. The method of mapping each block of main memory to any line of the cache is called ………….
A. Set associative B. Associative
C. Direct D. Indirect
13. In direct mapping the presence of the block in memory is checked with the help of ......field.
A. Tag B. Line
C. Block D. Word
Explanation: The tag field is usd to check the presence of a mem block.
14. The algorithm to remove and place new contents into the cache is called …
A. Replacement algorithm B. Renewal algorithm
C. Updation D. None of the others
Explanation: As the cache gets full, older contents of the cache are swapped out with newer
contents.This decision is taken by the algorithm.
15. The write-through procedure is used:
A. To write onto the memory directly
B. To write and read from memory simultaneously
C. To write directly on the memory and the cache simultaneously
Explanation: When write operation is issued then the corresponding operation is performed.
01. What are the key properties of the semiconductor memory cell?
A. They exhibit two states, which can be represented by 0 or 1
C. They can be read to sense the state
02. With RAM, which of the following statements is true:
A. It is not volatile
B. DRAM is made from flip-flops
C. SRAM is made from capacitors
D. A place to store information that the computer is processing
03. With RAM, which of the following statements is false:
A. DRAM is made from flip-flops
B. DRAM is made from capacitors
C. SRAM is made from flip-flops
D. SRAM does not need to be refreshed
04. RAM is called DRAM (Dynamic RAM) when …
A. It is always moving around data
B. It requires periodic refreshing
C. It can do several things simultaneously
05. DRAM is used for:
A. Internal memory B. External Memory
C. Cache memory D. Main memory
06. The standard SRAM chips are costly as …
A. They use highly advanced micro-electronic devices.
B. They house 6 transistor per chip.
C. They require specially designed PCB’s.
Explanation: As they require a large number of transistors, their cost per bit increases.
07. With the SRAM memory 64Kx4bit, which of the following statements is true:
A. The address lines are: A0 -> A15
B. The address lines are: D0 -> D15
C. The data lines are: A0 -> A3
D. The data lines are: D0 -> D8
08. With SRAM memory chips 16Kx8bit, which of the following statements is wrong:
A. There are 14 address lines
B. There are 8 data lines
C. The address lines are: A0 – A13
D. The address lines are: A0 – A14
09. SRAM is used for:
A. Main memory B. Cache memory
B. Internal memory C. External Memory
10. ROMs are used to ...
A. Record large size data, unchanged over time
B. Record small size data, updated regularly
C. Record the system subroutine
D. Contain the computer control program
11. Part of the operating system is usually stored in ROM so that it can be used to boot up the
computer.ROM is used rather than RAM because:
A. ROM chips are faster than RAM
B. ROM chips are not volatile
C. ROM chips are cheaper than RAM chips
12. With ROM, which of the following statements is true:
A. Can use electricity to erase PROM
B. PROM is a type of ROM that can be erased and recorded many times
C. EPROM is a type of ROM that can be erased and recorded many times
D. Can use electricity to erase EPROM
13. With ROM, which of the following statements is false:
A. There are all 5 types of ROMs
B. Can be use ultraviolet light to erase EPROM
C. EEPROM be written into without erasing prior contents
D. EPROM be written into without erasing prior contents
14. If the syndrome for the Hamming code contains one and only one bit set to 1:
C. An error is occurred and the numerical value of the syndrome indicates the position of the data bit
inerror
15. If the syndrome for the Hamming code contains more than one bit set to 1:
C. An error is occurred and the numerical value of the syndrome indicates the position of the data bit
inerror
16. The maximum addressing capacity of a microprocessor which uses 8 bit data & 16 bit address is
A. 64 KB B. 4 GB
C. 16 MB D. None of the others
17. An 16 bit address generates an address space of............locations
A. 1024 B. 65,356
C. 2 ^ 32 D. 16,777,216
Explanation: The number of addressable locations in the system is called as address space.
18. If a system is 32 bit machine, then the length of each word will be ……….
A. 4 bytes B. 8 bytes
C. 16 bytes D. 12 bytes
Explanation: A 32 bit system means, that at a time 32 bit instruction can be executed.
19. A computer’s memory is composed of 4K words of 64 bits each. How many total bits in memory?
A. 128000 B. 256000
C. 262144 D. 131072
20. In order to execute a program instructions must be transferred from memory along a bus to the
CPU.If the bus has 8 data lines, at most one 8 bit byte can be transferred at a time. How many memory
access would be needed in this case to transfer a 16 bit instruction from memory to the CPU.
A. 1 B. 2
C. 3 D. 4
01. If a magnetic disc drive has 100 cylinders, each containing 10 tracks of 10 sectors, and each sector
cancontain 128 bytes, what is the maximum capacity of the disc drive in KB?
A. 160,000 B. 1,280
C. 1,250 D. 1,280,000
The maximum capacity of the disk is 1280000 bytes.
Given data :
1 sector contains 128 bytes.
There are 10 sectors in one track.
One cylinder contains 10 tracks.
There are 100 cylinders.
• The total number of tracks
= Number of cylinders × Tracks in one cylinder
= 100×10
= 1000
• Number of sectors
= Number of tracks × Sectors in one track
= 1000×10
= 10000
• Total amount of data
= Total number of sector × data present in one sector
= 10000×128
= 1280000 bytes
The total capacity of data in terms of bytes is 1280000 bytes

02. According to the specifications of a particular hard disk, a seek time takes 0.3 milliseconds
betweenadjacent tracks. If the disk has 100 cylinders how long will it take for the head to move from
the innermost cylinder to the outermost cylinder.
A. 30 milliseconds B. 300 microseconds
C. 3000 microseconds D 0.3 seconds
03. A computer that is advertised as having a 96K byte DRAM memory and a 2.1 Gigabyte hard
drivehas
A. 96K bytes of secondary memory and 2.1 Gigabytes of primary memory
B. 2.1 Gigabytes of auxiliary memory and 96 K bytes of primary memory
C. 96K bytes of cache, 2.1 Gigabytes of primary memory
D. 2.1 Gigabytes of auxiliary memory, 96 K bytes of primary memory and 96 bytes of cache
04. The average time required to reach a storage location in memory and obtain its contents is called the
A. Seek time B. Turnaround time
C. Access time D. Transfer time
05. The amount of time required to read a block of data from a disk into memory is composed of
seektime, rotational latency, and transfer time. Rotational latency refers to
A. The time it takes for the platter to make a full rotation
B. The time it takes for the read-write head to move into position over the appropriate track
C. The time it takes for the platter to rotate the correct sector under the head
06. The method of placing the heads and the discs in an air tight environment is called as ……..
A. RAID Arrays B. ATP tech
C. Winchester technology D. Fleming reduction
Explanation: <numeric> The Disks and the heads operate faster due to the absence of the dust
particles.
07. Which of the following is a component of the disk system?
A. Disk B. Disk drive
C. Disk controller D. All of the others
08. If the drive has 20 surfaces, how many heads will it have?
A. 1 B. 5
C. 10 D. 20
Explanation: <numeric> Each surface will have its own head to perform read/write operation.
09. The ................process divides the disk into sectors and tracks.
A. Creation B. Initiation
C. Formatting D. Modification
Explanation: <numeric> The formatting process deletes the data present and does the creation
ofsectors and tracks.
10. The data can be accessed from the disk using ……….
11. The ...............is the minimum storage unit of a hard drive.
A. Track B. Sector
C. Cluster D. Cylinder
12. To distinguish between two sectors we make use of ……….
A. Inter sector gap B. Splitting bit
C. Numbering bit D. None of the others
Explanation: <numeric> This means that we leave <để lại> a little gap between each sectors
todifferentiate between them.
13 ................. is used to deal with the difference in the transfer rates between the drive and the bus.
A. Data repeaters B. Enhancers
C. Data buffers D. None of the others
Explanation: <numeric> The buffers are added to store the data from the fast device and to send it
tothe slower device at its rate.
14. What common characteristics are shared by all RAID levels?
A. Set of physical disk drives viewed by the operating system as a single logical drive
B. Data are distributed across the physical drives of an array in a scheme known as striping
C. Redundant disk capacity is used to store parity information, which guarantees data recoverability
incase of a disk failure
15. The solution to the problem of reliability is the introduction of ……….
A. Aging B. Scheduling
C. Redundancy D. Disks
16. RAID splits file(s) into many segments, and sends the segments to several disks. Files that have
beensegmented in this way are called:
A. Striped File B. Striped Data
C. Striped Array D. None of the others
17. Which of the following is the RAID level no redundant?
A. 0 B. 1
C. 2 D. 3
18. Which of the following is the RAID level refers to memory-style ECC organization?
A. 1 B. 2
C. 3 D. 4
19. Which of the following is the RAID level distributes parity and data across all the disks?
A. 3 B. 4
C. 5 D. 6
20. RAID level 1+0 is used because RAID level 1 provides ………. whereas RAID level 0 provides ……….
A. Performance, Redundancy B. Performance, Reliability
C. Redundancy, Performance D. Reliability, Performance
01. register keeps tracks of the instructions stored in program stored in memory.
A. AR (Address Register) B. XR (Index Register)
C. PC (Program Counter) D. AC (Accumulator)
02. An interface that provides a method for transferring binary information between internal storage
andexternal devices is called as …
A. I/O interface B. Input interface
C. Output interface D. I/O bus
03. An interface that provides I/O transfer of data directly to or form the memory unit and peripheral is
termed as …
A. DDA B. Serial interface
C. BR D. DMA
04. External, or peripheral, devices include:
A. Human readable B. Machine readable
C. Communication D. All of the others
05. With the functions of an I/O module, which of the following statements is false:
A. Control and timing
B. A module only connects to a peripheral device
C. Exchange information with the processor, with peripherals
D. Data buffers, error detection
06. I/O addressing methods:
A. Memory-mapped I/O
B. Isolated I/O
C. Both memory-mapped I/O and isolated I/O
07. In memory-mapped I/O…
B. The I/O devices have a seperate address space
Explanation: It’s the different modes of accessing the i/o devices.
08. With isolated I/O, ...
B. The I/O devices have a seperate address space
Explanation: It’s the different modes of accessing the i/o devices.
09. There are three methods for performing I/O:
A. Interrupt-driven I/O, System-driven I/O, DMA
B. Interrupt-driven I/O, System-driven I/O, Programmed I/O
C. Programmed I/O, Interrupt-driven I/O, DMA
D. Programmed I/O, System-driven I/O, DMA
10. The method of accessing the I/O devices by repeatedly checking the status flags is …
A. Programmed I/O B. Memory-mapped I/O
C. I/O mapped D. None of the others
Explanation: In this method the processor constantly checks the status flags , and when it finds that
theflag is set it performs the appropriate operation.
11. The method of synchronising the processor with the I/O device in which the device sends a
signalwhen it is ready is …
A. Exceptions B. Signal handling
C. Interrupt-driven I/O D. DMA
Explanation: This is a method of accessing the I/O devices which gives the complete power to
thedevices, enabling them to intimate the processor when they’re ready for transfer.
12. The process where in the processor constantly checks the status flags is called as …
A. Polling B. Inspection
C. Reviewing D. Echoing
13. With Programmed I/O, which of the following statements is false:
A. Use input/output commands in the program to exchange data with the I/O ports
B. Peripherals are active objects in data exchange
C. When executing the program, encountering input/output commands, the CPU controls data
exchangewith peripherals
D. Peripherals are passive objects in data exchange
14. With Programmed I/O, which of the following statements is true:
A. This is the simplest method to exchange data
B. This is the fastest method to data exchange
C. Complex circuit design
15. With Interrupt-driven I/O, which of the following statements is false:
B. CPU does not have to wait for the availability of peripherals
C. CPU have to wait for the availability of I/O module
D. I/O module interrupt CPU when it is in ready state
16. With Interrupt-driven I/O, which of the following statements is true:
B. The method is fully processed by hardware
C. CPU is an active object in data exchange
D. The method is fully processed by software
17. The DMA differs from the interrupt mode by …
A. The involvement of the processor for the operation
B. The method accessing the I/O devices
C. The amount of data transfer possible
D. Both the involvement of the processor for the operation and the amount of data transfer possible
Explanation: DMA is an approach of performing data transfers in bulk between memory and
theexternal device without the intervention of the processor.
18. The DMA transfers are performed by a control circuit called as …
A. Device interface B. DMA controller
C. Data controller D. Overlooker
Explanation: The Controller performs the functions that would normally be carried out by the
processor.
19. In DMA transfers, the required signals and addresses are given by the …
A. Processor B. Device drivers
C. DMA controller D. The program itself
Explanation: The DMA controller acts like a processor for DMA transfers and overlooks <bỏ qua> the
entire process.
20. The technique whereby the DMA controller steals the access cycles of the processor to
operate iscalled as …
A. Fast conning B. Memory Con
C. Cycle stealing D. Memory stealing
Explanation: The controller takes over the processor’s access cycles and performs memory operations.
01. The operating system is an example of a computer ……….

A. Object B. File system
C. Program D. Desktop
02. Which of the following is the primary purpose of an operating system?
A. To make the most efficient use of the computer hardware
B. To allow people to use the computer
C. To keep systems programmers employed
D. To make computers easier to use
03. The key services provided by an OS:
A. Create and execute programs
B. Control access to I/O devices, files and system resources
C. Accounting, error detection and response
04. One of the function of operating system is it serves an interface between user and ……….
A. Software B. Hardware
C. Utilities D. Data ware
05. In an................ system the user/programmer interacts directly with the computer, usually through a
keyboard/display terminal to request the execution of a job or to perform a transaction.
A. Batch B. Multiprogramming
C. Interactive D. None of the others
06. Which of the following is NOT a function of operating system?
A. Resource Manager B. Storage Manager
C. Process Manager D. Software Manager
07. Long-term scheduling is:
B. The decision to add to the number of processes that are partially or fully in main memory
C. The decision as to which available process will be executed by the processor.
08. Medium-term scheduling is:
A. The decision as to which process's pending I/O request shall be handled by an available I/O device.
D. The decision to add which programs to the system for processes
09. Short-term scheduling is:
10. What is a process?
A. A program in execution
B. A *.exe file
C. A executable file stored in external memory
11. What is the purpose of the process?
A. Multiprocessing B. Multiprogramming
C. Multicore D. All of the others
12. In the process state transition diagram, which state corresponding to a program is admitted by
theLong-term scheduler?
A. New B. Ready
13. In the process state transition diagram, ........... will initialize the process, moving it to the ready state.
14. In the process state transition diagram, the transition from the READY state to the RUNNING state
indicates that:
A. A process was preempted by another process
B. A process has blocked for a semaphore or other operation
C. A process is done waiting for an I/O operation
D. A process was just created
15. The state corresponding to the process has terminated and will be destroyed by the OS is called:
A. New B. Ready
16. Copying a process from memory to disk to allow space for other processes is called?
A. Page Fault B. Deadlock
C. Demand Paging D. Swapping
17. The purpose of swapping is:
A. To remove processes not in a ready state
B. To provide for efficient use of main memory for processes execution
C. To add processes in a ready state to main memory
18. Swapping is executed by ..........
19. If a process may be dynamically assigned to different locations in main memory, what is
implicationfor the addressing mechanism?
A. The addressing mechanism must keep track of the physical addresses of the process
B. The addressing mechanism must keep track of the logical addresses used for swapping out
theprocess
C. The addressing mechanism must keep track of the physical addresses of the process, as well as
thelogical addresses used for swapping out the process
20. The purpose of a TLB is:
A. To cache page translation information
B. To cache frequently used data
C. To hold register values while a process is waiting to be run
D. To hold the start and length of the page table
02. The approach is essentially the ability to execute instructions independently
andsimultaneously in different pipelines.
A. Scalar B. Branch
03. Which of the following is a situation which parallel executions can not apply?
A. Procedural dependency B. Resource conflicts
C. Anti-dependency D. All of the others
04. The situation in which the second instruction needs data produced by the first instruction to
executeis referred to as .
05. The instructions following a branch have a on the branch and cannot be executed until
06. refers to the process of initiating instruction execution in the processor's functional units.
07. Instead of the first instruction producing a value that the second instruction uses, with
08. exists when instructions in a sequence are independent and thus can be executed
inparallel by overlapping.
09. is determined by the number of instructions that can be fetched and executed at the
sametime and by the speed and sophistication of the mechanisms that the processor uses to find
independent instructions.
A. Machine parallelism B. Instruction-level parallelism
C. Output dependency D. Procedural dependency
10. Which of the following is a hardware technique that can be used in a superscalar processor
toenhance performance?
A. Duplication of resources B. Out-of-order issue
C. Renaming registers D. All of the others
11. - Statement I : Register renaming eliminates anti-dependencies and output dependencies.
- Statement II : Out-of-order completion requires more complex instruction issue logic than in-
order completion.
12. Uniprocessors fit into which category of computer systems?
A. MIMD B. SIMD
C. SISD D. MISD
13. Vector and array processors fit into which category of computer systems?
A. MIMD B. SIMD
C. SISD D. MISD
14. Symmetric multiprocessors (SMPs) fall into which category of computer systems?
A. MIMD B. SIMD
C. SISD D. MISD
15. In an SMP computer, the largest disadvantage of the bus organization is .
A. Reliability B. Performance
C. Cache coherence D. All of the others
16. A cache coherence problems can occur when .
A. A word is altered in one cache
B. Processors are allowed to update their own copies
C. Processors are allowed to update their own copies freely
17. - Statement I : The cache coherence problem is typically addressed in hardware.
- Statement II : Snoopy protocols are suitable for a bus-based multiprocessor.
18. A is an instance of a program running on a computer.
A. Thread B. Multithreading
C. Process D. SMT
19. With the instruction stream is divided into several smaller streams, known as threads,
suchthat the threads can be executed in parallel.
A. Process switch B. Multithreading
C. Thread D. Process
20. With instructions are simultaneously issued from multiple threads to the execution
units ofa superscalar processor.
A. SMT B. Single-threaded scalar
C. Coarse-grained multithreading D. Chip multiprocessing
21. Replicating the entire processor on a single chip with each processor handling separate threads is
.
A. Interleaved multithreading B. Blocked multithreading
C. Simultaneous multithreading D. Chip multiprocessing
01. Which representation is most efficient to perform arithmetic operations on the numbers?
A. Sign-magnitude B. 1’s complement
C. 2’s complement D. None of the others
02. When we perform the addition on -7 and 1 the answer in 2’s complement form is .
A. 1010 B. 1110
C. 0110 D. 1000
03. When we perform the multiplication on 110101 and 1111 the result of the operation is .
A. 1100011011 B. 1100111011
C. 1101001011 D. 1101011011
04. When 1101 is used to divide 1110110 the remainder is .
A. 0 B. 1
C. 10 D. 100
05. registers enable the machine or assembly language programmer to minimize main
memoryreferences by optimizing use of registers.
A. General purpose B. Control and status
C. User-visible D. None of the others
06. Which register of the following connects to the address bus directly?
A. PC B. MAR
C. MBR D. None of the others
07. Addressing mode used in instruction SUB r1, r2 is .
A. Immediate B. Indirect
C. Base D. Register
08. In immediate addressing mode the operand is placed .
A. In the CPU register
B. After OP code in the instruction
C. In memory
D. In stack
09. How many address lines are needed to address each memory location in a 2048 X 4 memory chip?
A. 10 B. 11
C. 8 D. 12
11. A processor performing fetch or decoding of different instruction during the execution of
anotherinstruction is called .
A. Super-scaling B. Pipe-lining
C. Parallel Computation D. None of the others
Explanation: Pipe-lining is the process of improving the performance of the system by processing
differentinstructions at the same time, with only one instruction performing one specific operation.
12. The periods of time when the pipeline, or some portion of the pipeline, is idle is called as .
A. Hazards B. Stalls
C. Bubbles D. Stalls or Bubbles
Explanation: <numeric> The stalls are a type of hazards that affect a pipelined system.
13. Which computer architecture aimed at reducing the number of instructions per program?
A. CISC B. RISC
C. ISA D. ANNA
14. Which computer architecture aimed at reducing the time of execution of instructions?
A. ANNA B. RISC
C. CISC D. ISA
Explanation: <numeric> The Risc machine aims at reducing the instruction set of the computer.
15. Which computer architecture was the first to implement pipe-lining?
A. ISA B. CISC
C. RISC D. ANNA
Explanation: <numeric> The RISC machine architecture was the first to implement pipe-lining.
16. The Sun microsystems processors usually follow architecture.
A. CISC B. ISA
C. ULTRA SPARC D. RISC
17. Which of the following is typical distinguishing characteristics of RISC organization?
A. A limited instruction set with a fixed format
B. A large number of registers or the use of a compiler that optimizer register usage
C. An emphasis on optimizing the instruction pipeline
18. Both CISC and RISC architectures have been developed to minimize what?
A. Cost B. Time delay
C. Semantic gap D. All of the others
19. - Statement I : The major cost in the life cycle of a system is hardware.
- Statement II : Almost all RISC instructions use simple register addressing. Which of the
abovestatements are true?
20. is a way of increasing the efficiency of the pipeline by making use of a branch that does
nottake effect until after execution of the following instruction.
21. can improve performance by reducing loop overhead, increasing instruction parallelism
byimproving pipeline performance, and improving register, data cache, or TLB locality.
22. is the fastest available storage device.
A. Main memory B. Cache
C. Register storage D. HLLs
23. The essence of the approach is the ability to execute instructions independently
andconcurrently in different pipelines.
A. Scalar B. Branch
24. Which of the following is a fundamental limitation to parallelism with which the system must cope?
A. Procedural dependency B. Resource conflicts
C. Anti-dependency D. All of the others
25. The situation where the second instruction needs data produced by the first instruction to execute
isreferred to as .
26. The instructions following a branch have a on the branch and cannot be executed until
27. refers to the process of initiating instruction execution in the processor's functional units.
28. Instead of the first instruction producing a value that the second instruction uses, with
29. exists when instructions in a sequence are independent and thus can be executed
inparallel by overlapping.
30. is determined by the number of instructions that can be fetched and executed at the
sametime and by the speed and sophistication of the mechanisms that the processor uses to find
independent instructions.
A. Machine parallelism B. Instruction-level parallelism
C. Output dependency D. Procedural dependency
31. Which of the following is a hardware technique that can be used in a superscalar
processor toenhance performance?
A. duplication of resources B. out-of-order issue
C. renaming D. all of the others
02. Microprocessors that are used for one particular job are classified
as
A. Dedicated microprocessors B. Dedicated computers
C. Dedicated microcomputers D. Dedicated mega computers
03. At the integrated circuit level, what are the three principal constituents of a computer system?
A. Wafers, chips, and interconnections among them
B. Chips, memory cells, and interconnections among them
C. Gates, memory cells, and interconnections among them
04. CISC stands for ...
A. Complete Instruction Sequential Compilation
B. Computer Integrated Sequential Compiler
C. Complex Instruction Set Computer
D. Complex Instruction Sequential Compilation
05. Which types of programmers should be aware of instruction set architecture? (Select all
correctanswers)
C. Compiler Designer D. HLL Programmers
06. Compact discs, (according to the original CD specifications) hold how many minutes of music?
A. 74 mins B. 56 mins
C. 60 mins D. 90 mins
07. During the execution of a program which gets initialized first?
A. MBR B. IR
C. PC D. MAR
08. The fetch and execution cycles are interleaved with the help of …
A. Modification in processor architecture
B. Clock
C. Special unit
D. Control unit
09. Any computer must at least consist of:
A. Data bus B. Address bus
C. Control bus D. All of the others
10. The main virtue <ưu điểm, tính hấp dẫn, …> for using single bus structure is:
A. Fast data transfers
B. Cost effective connectivity and speed
C. Cost effective connectivity and ease of attaching peripheral devices
Explanation: By using single BUS structure we can minimize the amount hardware (wire) required and
therebyreducing the cost.
11. To extend the connectivity of the processor bus we use …
A. PCI bus B. SCSI bus
C. Controllers D. Multiple bus
Explanation: PCI bus is used to connect other peripheral devices which require a direct connection with
theprocessor.
12. PCI stands for …

A. Peripheral Component Interconnect
B. Peripheral Computer Interconnect
C. Peripheral Component In circuit
13. Memory system of computers includes:
A. Cache, External Memory
B. External Memory, ROM
C. Optical Disk, Internal Memory
D. Internal Memory, External Memory
14. The fastest data access is provided using …
A. Cache memory B. DRAM
C. SRAM D. Registers
Explanation: The fastest data access is provided using registers as these memory locations are
situatedinside the processor.
15. The last on the hierarchy scale of memory devices is …
A. Cache memory B. Secondary memory
C. Registers D. RAM
Explanation: The secondary memory is the slowest memory device.
16. A memory management technique used to improve computer performance is:
A. Selecting memory chips based on their cost
B. Storing as much data as possible on disk
C. Using the cache to store data that will most likely be needed soon
D. Preventing data from being moved from the cache to primary memory
17. The technique of searching for a block by going through all the tags is ………
A. Linear search B. Binary search
C. Associative search D. None of the others
18. What is a Flash memory?
A. Is intermediate between EPROM and EEPROM
B. Uses an electrical erasing technology
C. Does not provide byte-level erasure
19. Which of the following is non-volatile memory?
A. SRAM B. EEPROM
C. DRAM D. None of the others
20. A computer’s memory is composed of 8K words of 32 bits each. How many bits are required
formemory address if the smallest addressable memory unit is a word?
A. 13 B. 8
C. 10 D. 6
21. The digital information is stored on the hard disk by ……….
A. Applying a suitable electric pulse.
B. Applying a suitable magnetic field.
C. Applying a suitable nuclear field.
D. By using optic waves.
Explanation: <numeric> The digital data is sorted on the magnetized discs by magnetizing <sự từ
hóa>the areas.
22. For the synchronization of the read head, we make use of a ……….
A. Framing bit B. Synchronization bit
C. Clock D. Dirty bit
Explanation: <numeric> The clock makes it easy to distinguish between different values red by head.
23. The set of corresponding tracks on all surfaces of a stack of disks form a ……….
A. Cluster B. Cylinder
C. Group D. Set
Explanation: <numeric> The data is stored in the these sections called as cylinders.
24. The data can be accessed from the disk using ……….
24 ................ is used to detect and correct the errors that may occur during data transfers.
A. ECC B. CRC
C. Checksum D. None of the others
Explanation: <numeric> ECC stands for Error Correcting Code.
26. RAID level ................ refers to disk arrays with striping but without any redundancy.
A. 0 B. 1
C. 2 D. 3
27. RAID level ................. consists of byte-level striping with dedicated parity.
A. 0 B. 1
C. 2 D. 3
28. RAID level ................. is also known as block-interleaved parity organization and uses block-level
striping and keeps a parity block on a seperate disk.
A. 1 B. 2
C. 3 D. 4
29. RAID level 5 is also known as :
A. Bit-interleaved parity organization
B. Block-interleaved parity organization
C. Block-interleaved distributed parity
D. Memory-style ECC organization
30. It is the represented abbreviations of an Opcode which also indicates the operation.
A. Control B. Mnemonics
C. Increment D. Logical
31. It is the bitwise operation and also includes AND, OR and NOT, XOR, and XNOR gates.
A. Operands B. Arithmetic
C. Characters D. Logical
32. This is the common form of data which is text or character strings.
A. Addresses B. Numbers
C. Characters D. Conversion
33. It's all about the instruction length (in bits), number of addresses, size of various fields, and so on.
A. Operation Repertoire B. Instruction Format
C. Opcodes D. Logic Instructions
34. It is a collection of different instructions that the processor can execute, it also provides
thecommands to the processor, to tell it what it needs to do.
A. Instruction Set B. Operation Code
C. Immediate D. Processor Register
35. The one which is inputted in an operation and are also represented symbolically.
A. Numbers B. Absolute
C. Mnemonics D. Operands
36. It's an operation that adds 1 to the operand.
A. Increment B. Negate
C. Decrement D. Registers
37. Which category of microprocessor instructions detect the status conditions in registers
andaccordingly exhibit the variations in program sequence on the basis of detected
results?
A. Transfer Instructions B. Operation Instructions
C. Control Instructions D. All of the others
38. The push and pop instructions belonging to the category of transfer instructions of
microprocessorperform data transformation between .
A. Two registers
B. Processor register and memory stack
C. Processor register and interface register
D. Interface register and memory word
39. The addressing mode, which uses the PC instead of a general purpose register is
A. Indexed with offset B. Relative
C. Direct D. Both Indexed with offset And
Direct
Explanation: In this the contents of the PC are directly incremented.
40. The addressing mode, where you directly specify the operand value is .
A. Immediate B. Direct
C. Definite D. Relative
41. The addressing mode which makes use of in-direction pointers is
A. Indirect addressing mode B. Index addressing mode
C. Relative addressing mode D. Offset addressing mode
Explanation: In this addressing mode, the value of the register serves as another memory location and
hencewe use pointers to get the data.
42. Which addressing mode execute its instructions within CPU without the necessity of
referencememory for operands?
A. Implied Mode B. Immediate Mode
C. Direct Mode D. Register Mode
43. Which register holds the address for a stack whose value is supposed to be directed at the
topmostposition?
A. Stack Pointer B. Stack Register
C. Both Stack Pointer & Stack Register D. None of the others
44. What is another name of memory stack especially given for the fundamental function performed
byit?
A. Last-in-first-out (LIFO) B. First-in-last-out (FILO)
C. First-in-first-out (FIFO) D. Last-in-last-out (LILO)
45. What does the last instruction of each subroutine that transfer the control to the instruction in
thecalling program with temporary address storage , called as?
A. Jump to subroutine B. Branch to subroutine
C. Return from subroutine D. Call subroutine
46. converts the programs written in assembly language into machine instructions
A. Machine compiler B. Interpreter
C. Assembler D. Converter
Explanation: The assembler is a software used to convert the programs into machine instructions.
47. Programs written in assembly language
A. Are not portable
B. Make use of mnemonics
C. Run faster and require less storage space than those written in HLLs
48. In the Assembly Language instruction LDA X
A. LDA is the opcode and X is the operand
B. LDA is the operand and X is the opcode
C. LDA is a symbolic address
D. X is a direct address
49. Consider the program segment:
Age DB 100
MOV Age,123
What is the memory-addressing mode of the first operand in the MOV instruction?
A. Immediate addressing mode B. direct addressing mode
C. Indirect addressing mode D. None of the others
50. The instruction DEC N inform the assembler to
A. Decrement the content of N
B. Decrement the data addressed by N
C. Convert signed decimal number to binary
51. The assembler stores the object code in
A. Main memory B. Cache
C. RAM D. Magnetic disk
Explanation: After compiling the object code, the assembler stores it in the magnetic disk and waits for further
execution.
01. Which of the following has a variable ability to conduct electricity depending on conditions?
A. Conductor B. Insulator
C. Semiconductor D. None of the others
The semiconductive material silicon is used to make most microchips because changes in conditions (such
ascurrent and voltage) can be used to control how conductive of electrons it is at a given moment, allowing
controlled flow of electricity.
02. Which of the following is the fundamental conceptual unit in a computer?
A. CPU B. Hard Drive
C. Operating System D. Transistor
03. There’s a concept that states: the number of transistors that manufacturers can pack into a chip
ofthe same size doubles every years. What is it called?
A. Godwin's Law B. Moore's Law
C. Fermat's Last Theorem D. None of the others
More of an estimate that has held somewhat true than a law, the idea was first put forth in 1965 by Gordon E.
Moore, co-founder of Intel, who at first predicted the number would double every year. The term is still used in
computing circles, but the time frame gets revised periodically.
04. What does a transistor do?
A. Stores electricity
B. Acts as a switch to control the flow of electric current
C. Reduces the flow of electric current
A processor contains many millions of transistors etched right into the silicon. Electrical signals are applied to
make the transistor either allow or disallow the flow of electricity.
05. Which of the following is a component of a computer systems that executes programs,
communicateswith and usually controls the operation of other computer components?
A. CPU B. Control Unit
C. ALU D. None of the others
06. What is a CPU’s clock speed?
A. The accuracy of time-keeping function
B. The number of times a second it refreshes its memory
C. The rate at which it can execute instructions
The clock speed indicates how quickly the CPU can execute instructions. The frequency is measured
inmegahertz or gigahertz.
07. What part of the CPU performs arithmetic and logic operations?
A. The logic gate B. The ALU
C. The system bus D. None of the others
The arithmetic logic unit (ALU) performs arithmetic operations like addition, subtraction, multiplication and
division and logic operations such as AND, OR, NOT, NAND, NOR and XOR.
08. When was the first commercial microprocessor
introduced?
A. 1958 B. 1965
C. 1971 D. 1981
The first commercial microprocessor, the Intel 4004, was introduced in 1971. Although it couldn't do much -- it
could only add and subtract four bits at a time -- it powered one of the first portable calculators.
09. Computer chips made from what materials?
A. Plastic B. Silicon
C. Olestra D. All of the others
Computer chips are small pieces of silicon onto which transistors are etched. Much of the
microprocessor-producing industry is located in the San Francisco Bay Area in Southern California and
has earned the nickname of "Silicon Valley."
11. Which of the following is not part of a job of computer chips?
A. Performing mathematical operations
B. Moving data from one memory location to another
C. Starting up the computer
D. All of the others are jobs of computer chips
Although CPUs have many complicated tasks to run, they do three basic things: perform mathematical
operations, move data between memory locations and follow sets of instructions. The job of starting up
thecomputer specifically involves the bootstrap loader.
12. The main purpose of having memory hierarchy is to .
A. Reduce access time
B. Provide large capacity
C. Reduce propagation time
D. Both Reduce access time And Provide large capacity
13. The main reason for the discontinuation of semiconductor based storage devices for providing
largestorage space is .
A. Lack of sufficient resources B. High cost per bit value
C. Lack of speed of operation D. None of the others
Explanation: <numeric> In case of semiconductor based memory technology, we get speed but the increase
inthe integration of various devices the cost is high.
14. ROM stands for .
A. Read only memory B. Random only memory
C. Readily oral memory D. Random available memory
15. On the PC, ROM BIOS is used to do what?
A. Load the operating system
B. Test hardware in the machine
C. Both Load the operating system And Test hardware in the machine
When the microprocessor starts up, it looks towards the BIOS for several instructions. Among other things such
as storing the boot sector in RAM after it's read, BIOS instructions check the machine's hardware for errors and
then load the operating system.
16. The memory that a CPU can use directly is .
A. Cache memory B. Clock memory
C. Direct access memory D. All of the others
However instantanous the actions of a computer seem to be sometimes, every little operation takes time.
Retrieving data from the cache, however, is much faster than retreiving from system memory.
17. About how much address space that a 64-bit processor can access?
A. 4 GB B. 1,000 GB
C. One milion GB D. One billion GB
While 32-bit microprocessors can only address between 2 and 4 gigabytes of RAM, 64-bit microprocessors
canaddress as much as one billion gigabytes of RAM if needed. Although that may seem excessive for
something like home computers, such extra space may be necessary in the future for overloaded servers.
18. What is another name for a microchip?
A. Integrated circuit B. SCSI card
C. Circuit board D. None of the others
Integrated circuits were conceived of in the late 1950s when engineers realized you could make
computingcomponents smaller by etching transistors, resistors and capacitors into a solid block of silicon
rather than stringing them together with wires. And thus the modern microchip was born.
19. What is the term for a single chip that integrates all the computing components necessary to
run adevice?
A. System-on-a-chip B. Nanochip
C. Multi-core processor D. None of the others
Many of our smaller computing devices, such as smartphones and smart watches, use system-on-a-chip
(SoC)processors to pack a ton of computing capability into a tiny package. These chips may include the CPU,
GPU,RAM, ROM and other components all on one integrated circuit.
20. During transfer of data between the processor and memory we use .
A. Cache B. TLB
C. Buffers D. Registers
21. What part of the CPU stores the location of the instruction to be executed?
A. Cache B. Program counter
C. Data bus D. None of the others
The program counter is a type of register that contains the address of either the current or next instruction to
beexecuted.
22. Which registers of the following connects to data and address buses directly?
A. MBR and MAR B. MAR and MBR
C. MBR and PC D. MAR and PC
23. For converting virtual address into physical address, the programs are divided into .
A. Pages B. Frames
C. Segments D. Blocks
Explanation: <numeric> On the physical memory side the memory is divided into pages.
24. The starting address of the page table is stored in .
A. TLB B. R0
C. Page table base register D. None of the others
Explanation: <numeric> The register is used to hold the address which is used to access the table.
25. The area in the main memory that can hold one page is called as .
A. Page entry B. Page frame
C. Frame D. Block
26. The pages size shouldn’t be too small, as this would lead to .
A. Transfer errors B. Increase in operation time
C. Increase in access time D. Decrease in performance
Explanation: <numeric> The access time of the magnetic disk is much longer than the access time of the
memory.
27. The page length shouldn’t be too long because
A. It reduces the program efficiency B. It increases the access time
C. It leads to wastage of memory D. None of the others
Explanation: <numeric> If the size is more than the required size then the extra space gets wasted.
28. is a process in which memory is divided into groups of variable length.
A. Paging B. Overlays
C. Segmentation D. Paging with segmentation
29. - Statement I : When the processor executes a process it automatically converts from logical to
physical address by adding the current starting location of the process, called its base address, to
eachlogical address.
- Statement II : “Demand paging” means that each page of a process is brought in only when it is
needed.
30. - Statement I : TLB is an hardware including some registers. A part of page table is copied to
themin order to increase performance of translating virtual addresses to physical addresses.
- Statement II : The purpose of a TLB is to avoid, most of the time, having to go to disk to
retrievea page table entry.
31. Which addressing mode of the following is most suitable to change the normal sequence of
executionof instructions.
A. Relative B. Indirect
C. Index with Offset D. Immediate
Explanation: The relative addressing mode is used for this since it directly updates the PC.
32. The addressing mode used in PUSH B is .
A. Direct B. Register
C. Register Indirect D. Index
33. What is the content of Stack
Pointer?
A. Address of the current instruction
B. Address of the next instruction
C. Address of the top element of the stack
34. The instructions based on the stack operations are also known as 'zero address' or
'impliedinstructions', because .
A. Address gets updated automatically in stack pointer
B. Processor can refer a memory stack without specifying the address
C. Address gets updated automatically in stack pointer And Processor can refer a memory stack
withoutspecifying the address
35. What is the difference between a compiler and an interpreter?
A. Compilers are used for Special Purpose Languages while interpreters are used for General
PurposeLanguage
B. Compilers are written for translating LLLs and Interpreters for translating HLLs.
C. Compilers are written for translating HLLs and Interpreters for translating LLLs.
D. Compilers translate a whole program before starting execution while interpreters translate
andexecute line by line.
36. Which of the following is/are used in translating HLLs?
A. Compilers only
B. Compilers, Interpreters and Assemblers
C. Compilers and Interpreters
D. Compilers and Assemblers
37. If a HLL program is to be run a number of times, .
A. An interpreter can produce object code that may be saved and run straight away
B. An interpreter would have to translate it each time it is run
C. It is best to use an assembler
D. An interpreter would translate it once and then produce object code that can be saved and
afterwardsrun directly (without needing further translation)
38. What is the advantage of using Assembly language rather than HLLs?
A. Assembly programs are simpler to translate and occupy less storage space
B. Assembly languages are easier to code in
C. Assembly language programs are portable
D. Assembly is simpler to translate and easier to code in
39. Which parameter of computer determines its power to do various operations on data items?
A. Instruction set B. Memory size
C. Assembly language D. Application language
40. Which category in the following architectures, the CPU is designed to perform tasks using a
small,simple computer instruction set.
A. CISC B. RISC
C. RAID D. None of the others
As opposed to CISC (Complex Instruction Set Computer) architecture, in which the hardware has a large set
ofmore complex instructions, RISC (Reduced Instruction Set Computer) architecture includes a more
optimized
set of simple instructions, each requiring fewer transistors and executing in only one clock cycle.
Theseinstructions can be strung together via software to perform more complex operations.
41. What processor design company came to dominate the mobile device market with their low-
powerRISC based architecture?
A. Intel B. AMD
C. ARM D. None of the others
The company Advanced RISC Machines (ARM) developed processors using RISC architecture that allowed
forsmall chips with high-speed performance at low-power, making them ideal for small devices like
smartphones, tablets and wearable devices.
42. The type of processing where multiple instructions are sent to more than one processor to
execute atthe same time is called .
A. Word processing B. Data processing
C. Parallel processing D. None of the others
Many of today's CPUs include multiple processing cores, allowing the divvying up of instructions to speed up
processing. It should be noted that two cores don't double speed, as there are other factors at play.
43. Systems that do not have parallel processing capabilities are .
A. SISD B. SIMD
C. MIMD D. None of the others
44. Which factors of the following led to the development of multicore organizations?
A. The increase of logic density B. The hardware performance
C. The software challenges D. None of the others
45. To control the power density we can use more of the chip area for .
A. Multicore B. Cache memory
C. Silicon D. Resistors
46. The memory, inside the CPU, is used to store the copy of data or instructions stored in
largermemories is called .
A. Level 1 cache B. Level 2 cache
C. Registers D. TLB
Explanation: These memory devices are generally used to map onto the data stored in the larger memories.
47. The larger memory, inside the CPU, placed between the primary cache and the memory is called
.
A. Level 1 cache B. Level 2 cache

C. EEPROM D. TLB
Explanation: This is basically used to provide effective memory mapping.
48. Applications are characterized by having a small number of highly threaded processes called
.
A. Multithreaded native B. Multi-instance

C. Multiprocess D. None of the others
49. Applications are characterized by the presence of many single-threaded processes called .
A. Multi-instance B. Multi-process
C. Multi-threaded native D. None of the others
50. Applications can be run multiple instances of them in parallel called .
A. Multi-threaded native B. Multi-process
C. Multi-instance D. None of the others
51. Which applications of the following are supported effectively by multicore organizations?
A. Multi-threaded native applicationsB. Multi-process applications
C. Multi-instance applications D. All of the others
No. REVIEW KNOWLEDGE
1 The instructions like MOV or ADD are called as ______
a. OP-code b. Operators c. Commands d. None of them
2 The ______ plays a very vital role in case of super scalar processors.
a. Motherboard b. Compilers c. Memory d. Peripherals
3 The two phases of executing an instruction are __________
a. Instruction decoding and storage b. Instruction fetch and instruction execution
c. Instruction execution and storage d. Instruction fetch and Instruction processing
4 The assembler stores the object code in ______
a. RAM b. Cache c. Magnetic disk d. Main memory
5 The time lost due to the branch instruction is often referred to as ____________
a. Latency b. Delay c. Branch penalty d. None of them
6 In super-scalar processors, ________ mode of execution is used.
a. Out of order b. In-order c. Post order d. None of them
7 While using the iterative construct (Branching) in execution _____________ instruction is used to check the
condition.
a. TestCondn b. Branch c. TestAndSet d. None of them
8 To overcome the problems of the assembler in dealing with branching code we use _____
a. Debugger b. Interpreter c. Two-pass assemble d. Op-Assemble
9 The periods of time when the unit is idle is called as ________
a. Stalls b. Hazards c. Bubbles d. Both Stalls and Bubbles
10 The MSYN signal is initiated __________
a. After the slave gets the commands b. Soon after the address and commands are loaded
c. Soon after the decoding of the address d. None of them
11 The directive used to perform initialization before the execution of the code is ______
a. Store b. EQU c. Reserve d. Dataword

12 The situation wherein the data of operands are not available is called ______
a. Data hazard b. Stock c. Deadlock d. Structural hazard
13 Out of the following which is not a CISC machine.
a. VAX 11/780 b. Motorola A567 c. Intel 80486 d. IBM 370/168
14 The alternate way of writing the instruction, ADD #5, R1 is ______
a. There is no other way b. ADDIME 5, [R1]; c. ADDI 5, R1; d. ADD [5], [R1];
15 In CISC architecture most of the complex instructions are stored in _____
a. Diodes b. Register c. CMOS d. Transistors
16 The meter in and out lines are used for __________
a. Monitoring the usage of devices b. Monitoring the amount of data transferred
c. Measure the CPU usage d. None of them
17 The last statement of the source program should be _______
a. OP b. Return c. Stop d. End
18 The algorithm followed in most of the systems to perform out of order execution is __________
a. Score carding b. Tomasulo algorithm
c. Reader-writer algorithm d. None of them
19 Can you perform an addition on three operands simultaneously in ALN using Add instruction?
a. Yes b. Not possible using Add, we’ve to use AddSetCC
c. Not permitted d. None of them
20 The condition flag Z is set to 1 to indicate _______
a. There is no empty register available b. The operation requires an interrupt call
c. The operation has resulted in an error d. The result is zero
21 The commitment unit uses a queue called ______
a. Storage buffer b. Record buffer c. Commitment buffer d. None of them
22 The computer architecture aimed at reducing the time of execution of instructions is ________
a. RISC b. ANNA c. CISC d. ISA
23 The iconic feature of the RISC machine among the following is _______
a. Reduced number of addressing modes b. Increased memory size
c. Having a branch delay slot d. All of them
24 The ________ is responsible for maintaining coherency among L1 data caches.

a. VFP unit b. watchdog
c. distributed interrupt controller d. Snoop control unit
25 _____ directive specifies the end of execution of a program.
a. return b. Terminate c. End d. Stop
26 The assembler stores all the names and their corresponding values in ______
a. Special purpose register b. Value map Set c. Symbol Table d. None of them
27 Which of the architecture is power efficient?
a. IANA b. CISC c. ISA d. RISC
28 The step where in the results stored in the temporary register is transferred into the permanent register is
called as ______
a. Last step b. Commitment step c. Inception step d. Final step
29 The transmission on the asynchronous BUS is also called _____
a. Switch mode transmission b. Bulk transfer
c. Hank-Shake transmission d. Variable transfer
30 The contention for the usage of a hardware device is called______
a. Deadlock b. stalk c. Structural hazard d. None of them
31 ________ is when the processor spends most of its time swapping pages rather than executing instructions.
a. Paging b. Thrashing c. Swapping d. Multitasking
32 The OS maintains a __________ for each process that shows the frame location for each page of the
process.
a. TLB b. kernel c. page table d. logical address
33 A _______ is an electronic circuit that produces an output signal that is a simple Boolean operation on its
input signals.
a. decoder b. counter c. flip-flop d. gate
34 Using a direct mapping method for a memory of 32 blocks and a cache of 4 lines, how many bits are used
for tag field?
a. 5 b. 4 c. 3 d. 2
35 "Memory is organized into records and access must be made in a specific linear sequence" is a description
of __________.
a. Random access b. Direct access c. Associative d. Sequential access
36 Individual blocks or records have a unique address based on physical location with __________.
a. Direct access b. Associative c. Physical address d. Sequential access
37 For random-access memory, __________ is the time from the instant that an address is presented to the
memory to the instant that data have been stored or made available for use.
a. Transfer rate b. Memory cycle time c. Access time d. Direct access
38 Facilities and services provided by the OS that assist the programmer in creating programs are in the form
of _________ programs that are not actually part of the OS but are accessible through the OS.
a. JCL b. logical address c. Multitasking d. utility
39 The ________ consists of the access time plus any additional time required before a second access can
commence.
a. Direct access b. Transfer rate c. Latency d. Memory cycle time
40 Two processors A and B have clock frequencies of 2.2 GHz and 2.3 GHz respectively. Suppose A can
execute an instruction with an average of 4 steps and B can execute with an average of 5 steps. For the
execution of the same instruction, which processor is faster?
a. B b. A
c. Insufficient information d. Both A and B take the same time
41 The address of the instruction following the CALL instructions stored in _____
a. Stack b. Heap c. Program counter d. Static memory
42 The usual BUS structure used to connect the I/O devices is ___________
a. Star BUS structure b. Multiple BUS structure
c. Node to Node BUS structure d. Single BUS structure
43 The advantage of I/O mapped devices to memory mapped is ___________
a. No advantage as such
b. The devices connected using I/O mapping have a bigger buffer space
c. The devices have to deal with fewer address lines
d. The former offers faster transfer of data
44 The system is notified of a read or write operation by ___________
a. Appending an extra bit of the address
b. Sending a special signal along the BUS
c. Enabling the read or write bits of the devices
d. Raising an appropriate interrupt signal
45 To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
a. Buffer spaces b. Interrupt signals c. Status flags d. Exceptions
46 The techniques which move the program blocks to or from the physical memory is called as ______
a. Paging b. Framing c. Overlays d. Virtual memory organization

47 The binary address issued to data or instructions are called as ______
a. Physical address b. Relocatable address c. Logical address d. Location
48 __________ is used to implement virtual memory organization
a. MMU b. Frame table c. Page table d. None of them
49 The virtual memory basically stores the next segment of data to be executed on the _________
a. RAM b. Disks c. ROM d. Secondary storage
50 The associatively mapped virtual memory makes use of _______
a. Frame table b. TLB c. Page table d. None of them
51 Any condition that causes a processor to stall is called as _________
a. Hazard b. System error c. Page fault d. None of them
52 The periods of time when the unit is idle is called as ________
a. Hazard b. Both Bubbles and Hazards
c. Stalls d. Both Stalls and Bubbles
53 The stalling of the processor due to the unavailability of the instructions is called as ___________
a. Input hazard b. Structural hazard c. Control hazard d. None of them
54 ____________ method is used in centralized systems to perform out of order execution.
a. Scorecard b. Score boarding c. Optimizing d. Redundancy
55 The effectiveness of the cache memory is based on the property of ________
a. Locality of reference b. Memory localization c. Memory size d. None of them
56 The bit used to signify that the cache location is updated is ________
a. Flag bit b. Update bit c. Reference bit d. Dirty bit
57 The input devices can send information to the processor when _____
a. When the data arrives regardless of the SIN flag
b. When the SIN status flag is set
c. All of them
d. None of them
58 Which of the register/s of the processor is/are connected to Memory Bus?
a. Both PC and MAR b. PC c. IR d. MAR
59 ____ is used to choose between incrementing the PC or performing ALU operations.
a. Conditional codes b. Control unit c. Multiplexer d. None of them

60 The third generation of computers based on _____
a. Vacuum tubes b. VLSI c. Transistors d. IC
61 What is the maximum addressable memory of a 32-bit microprocessor with 24-bit address?
a. 16 MB b. 16 GB c. 16 Mbits d. 16 Gbits
62 The fetched instruction is loaded into a register in the processor known as the _____
a. Kernel b. Memory c. SSD d. Instruction register
63 If a processor clock is rated as 1.8 GHz then its clock period is _____
a. 5.55*10-9 sec b. 5.55*10-10 sec c. 0.55*10-10 sec d. 55.5*10-9 sec
64 In multiple Bus organization, the registers are collectively placed and referred as ______
a. Register file b. Register Block c. Map register d. Set register

1. The ABI is the boundary between hardware and software.
A. True
B. False
2. Assume an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are What is the maximum
number of one-operand instructions that can be supported?
A. 256
B. 128
C. 32
D. 512
E. 64
3. A number of chips can be grouped together to form a memory bank.

A. False
B. True
4. The cache is capable of handling global as well as local variables.
A. False
B. True
5. Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per is 512 byte. What is
the disk capacity?
4 surfaces = 2 bits
512 tracks = 9 bits
32 sectors = 5 bits
sectors size is 512 bytes = 9 bits
The capacity of disk = 2^(2+9+5+9)=2^25 = 2^5Mb = 32Mb
to specify particular sectors, we do not need sector size, so bits require is 2+9+5 = 16
A. 32 MB
B. 512 KB
C. 64 KB
D.16 GB
E. 64 MB
6. The unary operation inverts the value of its operand.
A. XOR
B. NAND
C. NOT
D. OR
7. Three of the most common uses of stack addressing are relative addressing, base-register a indexing.
A. False
B. True
8. The most important system program is the OS.
A. False
B. True
9. When using graph coloring, nodes that share the same color cannot be assighned to the same.
A. True
B. False
10. With a batch operating system the user does not have direct access to the processor.
A. True
B. False
11. is a principle by which two variables are independent of each other.
A. Autoindexing
B. Opcode
C. Completeness
D. Orthogonality
12. Because data are striped very small strips, RAID 3 cannot achieve very high data transfer.
A. True
B. False
13. The register file employs much shorter addresses than addresses for cache and memory.
A. True
B. False
14. A bus that connects major computer components (processor, memory, I/O) is called a
A. Control bus
B. System bus
C. Data bus
D. Address bus
15. A common example of system interconnection is by means of a _
A. Data transport
B. Contron device
C. Register
D. System bus
16. Second generation computers used .
A . integrated circuits
B. Large-scale integration
C. Transistors
D. Vacuum tubes
17. Architectural attributes include .
A. Memory technology used
B. Interfaces
C. Control signals
D. I/O mechanisms
18. The instruction location immediately following the delayed branch is referred to as the .
A. Delay load
B. Delay file
C. Delay register
D. Delay slot
19. Both batch multiprogramming and time sharing use miltiprogramming.
A. True
B. False
20. The predict-never-taken approach is the most popular of all branch prediction methods.
A. True
B. False
21. The defines the system call interface to the operating system and the hardware services available in a
system through the user instruction set architecture.
A. API
B. ISA
C. ABI
D. HLL
22. registers may be used only to hold data cannot be emloyed in the calculation address.
A. General purpose
B. Condition code
C. Data
D. Address
23. The method of using the same lines for multiple purposes is known as time multiplexing.
A. True
B. False
24. Counters can be designated as .
A. Asynchronous
B. Neither asynchronous or synchronous
C. Synchronous
D. Both asynchronous or synchronous
25. The controls the movement of data and instructions into and out of the processor.
A. Control unit
B. ALU
C. Shifter
D. Branch
26. The routine executed in reponse to an interrupt request is called routine.
A. Interrupt Service
B. Interrupt acknowledge
C. Serial interrupt
D. Vectored interrupt
E. Sub-routine.
27. The correspondence between the main memory blocks and those in the cache is specified.
A. Segmemt funcition
B. Hit rate
C. Replacement algorithm
D. Mapping function
E. Miss penalty
28. is when the disk rotates more slowly for accesses near the outer edge than for center.
A. Seek time
B. Magnetoresistive
C. Constant angular velocity (CAV)
D. Constant linear velocity (CLV)
29. The interprets the instructions in the memory and causes them to be executed.
A. I/O
B. Control unit
C. Main memory
D. arthmetic and logic unit
30. What is stored in the Stack Pointer?
A. Address of next instruction
B. Stack data values
C. Addressing method
D. Operations
E. Address of top item
31. With direct addressing, the length of the address field is usually less than the word length, the address range.
A. True
B. False
32. Cycle stealing is/are used in which concept?
A. Programmed I/O
B. DMA
C. Interrupts
D. Memory mapped I/O
E. All of the above

33. An I/O module must recognize one unique address for each peripheral it controls.
A. True
B. False
34. An I/O device is referred to as a .
A. CPU
B. Control device
C. Register
D. Peropheral
35. The basic function of a computer is to execute programs.
A. False
B. True
36. The data lines provide a path for moving dât among system modules and are collectively .
A. Control bus
B. System bus
C. Address bus
D. Data bus
37. The consists access time plus any additional time required before a second commence.
A. Direct access
B. Transfer rate
C. Memmory cycle time
D. Latency
38. The performance of the cache memory is measured in terms of a quantity called .
A. Hit Ratio
B. Instruction Ratio
C. Miss Ratio
D. Initialization Ratio
E. Address Ratio
39. All DRAMs require a refresh operation.
A. True
B. False
40. I/O channels are commonly seen on microcomputers, where as I/O controllers are used on.
A. False
B. True
41. The determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction
42. A(n) is generated by a failure such as power failure or memory parity error.
A. timer interrupt
B. hardware failure interrupt
C. I/O interrupt
D. program interrupt4
43. A disk is permanently mounted is the disk drive, such as the hard disk in a.
A. removable
B. double sided
C. nonremovable
D. movable-head
44. Which of the following memory types are noncolatile?
A. erasable PROM
B. programmable ROM
C. flash memory
D. all of the above
45. Interfaces between the computer and peripherals is an example of an organization attribute.
A. False
B. True
47. are a set of storage locations.
A. Registers
B. Control unit
C. PSWs
D. Processors
48. The holds the address of the next ins truction to be fetched.
A. MBR
B. IR
C. PC
D. MAR
49. The method of calculating the EA is the same for both base-register addressing and indexing.
A. False
B. True
50. The performs the computer’s data processing functions.
A. system bus
B. Register
C. ALU
D. CPU interconnection
A. System bus
B. Address bus
C. Data bus
D. Control bus
1. Interrupts do not improve processing efficiency
A. True
B. False
2. The is a small cache memory associated with the instruction fetch stage of the pipeline.
A. Dynamic branch
B. Loop table
C. Branch history table
D. Flag
3. Which of the following memory types are nonvolatile?
A. Erasable PROM
B. Programmable ROM
C. Flash memory
D. All of the above
4. Because the 82C55A is programmable via the control registe, it can be used to control variety of simple
peripheral devices.
A. True
B. False
5. Both batch multiprogramming and time sharing use multiprogramming.
A. True
B. False
6.* Both batch multiprogramming and time sharing use multiprogramming.

A. True
B. False
7. A common example of system interconnection is by means of a
A. Register
B. System bus
C. Data transport
D. Control device
8*. A common example of system interconnection is by means of a
A. Register
B. System bus
C. Data transport
D. Control device
A. Register
B. System bus
C. Data transport
D. Control device
10. For the address field references a main memory address and the referenced register contains a
positive displacement from that address
A. indexing
B. Base-register addressing
C. Relative addressing
D. All of the above
11. are a set of storage locations
A. Processors
B. PSWs
C. Registers
D. Control units
A. True
B. False
13*. A number of chips can be grouped together to form a memory bank.
A. True
B. False
B. False
A. True
B. False
15. The system bus is made up of
A. Control bus
B. Address bus
C. Both Control bus and Address bus
D. Control bus, Data bus and Address bus
E. Data bus
16. RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve
performance
A. True
B. False
17*. RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve
performance
A. True
B. False
18. When data are moved over longer distances, to or from a remote device, the process is known as
A. Data communications
B. Registering
C. Structuring
D. Data transport
A. Register
B. CPU interconnection
C. ALU
D. System bus
20. I/O channels are commonly seen on microcomputers, Whereas I/o controllers are used on mainframes.
A. true
B. False
21*. I/O channels are commonly seen on microcomputers, Whereas I/o controllers are used on mainframes.
A. true
B. False
22. determines the control and pipeline organization.
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used
23*. determines the control and pipeline organization.
A. Calculation
D. Operands used
24. Counters can be designated as
A. Asynchronous
B. Synchronous
C. Both asynchronous and synchronous
D. Neither asynchronous and synchronousS
A. Data communication
B. Registering
C. Structuring
D. data transport
26. The performs the computer’s data processsing functions
A. Register
C. ALU
D. system bus
27. I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes
A. True
B.False
A. Calculation
B. Execution
D. Operands used
A. asynchronous
B. synchronous
C. both asynchronous and synchronous
D. Neither asynchronous or synchronous
30. The contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter
31. Internal memory capacity is typically expressed in terms of .
A. Hertz
B. Nanos
C. Bytes
D. LOR
32. The controls the movement of dsata and instructions into and out of the processor.
A. control unit
B. ALU
C. Shifter
D. Branch
33. Cache memory is a much faster memory than the register file.
A. True
B. False
34. The basic element of a semiconductor memory is the memory cell.
A. True
B. False
A. Relative addressing
B. Autoindexing
C. Postindexing
D. Preindexing
36. instructions are used to position quantities in register temporarily for computational operations
A. Load-and-store
B. Window
C. Complex
D. Branch
37. The number ò bits used to represent various data type is an example of an architectural attribute
A. True
B. False
38. Register indirect addressing uses the same number of memory references as indirect addressing
A. True
B. False
39. Privileged instructions are certain instructions that are designated special and can be executed only by the
monitor
A. True
B. False
40. is the standardized scheme for multiple-disk database design
A. RAID
B. CAV
C. CLV
D. SSD
41. The operation yields true if either or both of its operands are true
A. NOT
B. AND
C. NAND
D. OR
42. Designers wrestle with the challenge of balancing processor performance with that of main memory and other
computer components
A. True
B. False
43. The most common means of computer/ user interaction is a
A. keyboard / monitor
B. mouse / printer
C. modem / printer
D. monitor / printer
1. Architectural attributes include
a. I/O mechanisms
b. control signals
c. interfaces
2. Memory is organized into records and access must be made in a specific linear sequence" is a description of
b. direct access
c. random access
d. associative
3. When large volumes of data are to be moved, a more efficient technique is direct memory access (DMA).
a. True
b. False
4. Computers are classified into generations based on the fundamental hardware technology employed.
a. True
b. False
a. I/O interrupt
c. timer interrupt
6. A control hazard occurs when two or more instructions that are already in the pipeline need the same
resource.
a. True
b. False
7. Indexing performed after the indirection is .
b. autoindexing
c. postindexing
d. preindexing
8. Which of the following interrelated factors go into determining the use of the addressing bits?
c. address range
d. all of the above
9. External memory is often equated with main memory.
a. True
b. False
10. The contains a word of data to be written to memory or the word most recently read.
a. MAR
b. PC
c. MBR
d. IR
11. The defines the third generation of computers
b. vacuum tube
c. transistor
d. VLSI
12. Almost all RISC instructions use simple register addressing
a. True
b. False
13. With the microchip is organized so that a section of memory cells are erased in a single action
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
14. The ENIAC is an example of a generation computer
a. first
b. second
c. third
d. fourth
15. The defines the system call interface to the operating system and the hardware resources and
a. HLL
b. API
c. ABI
d. ISA
16. For , the address field references a main memory address and the referenced register contains a
positive displacement from that address.
a. Indexing
d. all of the above
17. The stores data.
a. system bus
b. I/O
c. main memory
d. control unit
18. RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
a. True
b. False
19. The consists of the access time plus any additional time required before a second access can
commence.
a. Latency
c. direct access
d. transfer rate
20. The L1 cache is slower than the L3 cache
a. True
b. False
21. The scheduler determines which programs are admitted to the system for processing
a. long term
b. medium-term
c. short-term
d. I/O
22. A characteristic of ROM is that if is volatile
a. True
b. False
23. 2 The basic function of a computer is to execute programs
a. True
b. False
24. The cycle occurs at the beginning of each instruction cycle and causes an instruction to be fetched
from memory.
a. execute
b. indirect
c. fetch
d. interrupt
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
26. is a pipeline hazard.
a. Control
b. Resource
c. Data
d. All of the above
27. The command is used to activate a peripheral and tell it what to do
a. control
b. test
c. read
d. write
a. True
b. False
29. The disadvantage of the software poll is that it is time consuming
a. True
b. False
30. A architecture is one that makes use of more, and more fine-grained pipeline stages
a. Parallel
b. superpipe lined
c. superscalar
d. hybrid
a. Operations
b. Addressing method
c. Stack data values
d. Address of top item
e. Address of next instruction
32. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage
of advances in device performance
a. True
b. False
33. Because all devices on a synchronous are tied to a faced clock rate, the system cannot take advantage of
advances in device performance.
a. True
b. False
34. RAID is a set of physical disk drives viewed by the operating system as a single logical drive
a. True
b. False
a. Indexing
b. Base – register addressing
c. Relative addressing
d. All of the above
a. HLL
b. API
c. ABI
d. ISA
37. The ENIAC is an example of a generation computers
a. First
b. Second
c. Third
d. Fourth
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
a. True
b. False
40. The defines the third generation of computers.
b. vacuum tube
c. transistor
d. VLSI
41. External memory is often equipped with main memory
a. TRUE
b. FALSE
c. address range
d. All of the above
43. Indexing performed after the indirection is …. ?
a. A relative addressing
b. B. autoindexing
c. C. postindexing
d. D. Preindexing
resource
a. True
b. False
45. A(n) is generated by a failure such as power failure or more memory parity error
a. I/O interrupt
c. Time interrupt
a. True
b. False
a. True
b. False
.
b. direct access
c. random access
d. associative
49. Architect attributes include
a. I/O mechanisms
b. control signals
c. interfaces
1. The predict-never-taken approach is the most popular of all the branch prediction methods.
A. True
B. False
2. A characteristic of ROM is that it is volatile
A. True
B. False
3. The is a program that controls the execution of application programs and acts as an interface between
applications and the computer hardware.
A. Job control language
B. Operating system
C. Batch system
D. Nucleus
A. Main memory
B. Cache
C. Register storage
D. HLL
5. The correspondence between the main memory blocks and those in the cache is specified by
A. Mapping function
B. Replacement algorithm
C. Hit rate
D. Miss penalty
E. Segment function
6. Register addressing is similar to direct addressing with the only difference being that the address field refers to a
register rather than a main memory address.
A. True
B. False
A. True
B. False
8. The sum of the seek time and the rotational delay equals the , which is the time it takes to get into
position to read or write.
A. Access time
B. Gap time
C. Transfer time
D. Constant angular velocity
9. An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations.
A. True
B. False
10. The L1 cache is slower than the L3 cache.
A. True
B. False
11. The routine executed in response to an interrupt request is called routine.
A. Sub-routine
C. Vectored interrupt
D. Serial interrupt
E. Interrupt Service
A. Register
C. ALU
D. System bus
13. The defines the system call interface to the operating system and the hardware resources and services
available in a system through the user instruction set architecture.
A. HLL
B. API
C. ABI
D. ISA
A. True
B. False
A. Operations
B. Addressing method
C. Stack data values
D. Address of top item
E. Addressing of next instruction
16. A instruction can be used to account for data and branch delays.
A. SUB
B. NOOP
C. JUMP
D. All of the above
17. The operand yields true if and only if both of its operands are true.
A. XOR
B. OR
C. AND
D. NOT
18. Data are transferred to and from the disk in .
A. Tracks
B. Gaps
C. Sectors
D. Pits
19. A(n) is generated by some condition that occurs as a result of an instruction execution.
A. Timer interrupt
B. I/O interrupt
C. Program interrupt
D. Hardware failure interrupt
20. With demand paging it is necessary to load an entire process into main memory.
A. True
B. False
A. True
B. False
22. When the magnetizable coating is applied to both sides of the platter the disk is then referred to as .
A. Multiple sided
B. Substrate
C. Double sided
D. All of the above
23. With direct addressing, the length of the address field is usually less than the word length, thus limiting the
address range.
A. True
B. False
A. MAR
B. PC
C. MBR
D. IR
25. No single technology is optimal in satisfying the memory requirements for a computer system.
A. True
B. False
A. Erasable PROM
B. Programmable ROM
C. Flash memory
D. All of the above
27. Magnetic disks are the foundation of external memory on virtually all computer systems.
A. True
B. False
A. Job control language
B. Operating system
C. Batch system
D. Nucleus
A. Processors
B. PSWs
C. Registers
D. Control units
30. The is connected to the address lines of the system bus.
A. MBR
B. MAR
C. PC
D. IR
31. The basic function of computer is to execute programs.
A. True
B. False
32. The interconnection structure must support which transfer?
A. Memory to processor
B. Processor to memory
C. I/O to or from memory
D. All of the above
33. Interfaces between the computer and peripherals is an example of an organizational attribute.
A. True
B. False
34. It is a(n) issue whether the multiply instruction will be implemented by a special multiply unit or by a
mechanism that makes repeated use of add unit of the system.
A. Architectural
B. Memory
C. Mechanical
D. Organizational
A. System bus
B. I/O
C. Main memory
D. Control unit
from memory.
A. Execute
B. Indirect
C. Fetch
D. Interrupt
37. When using technique, all write operations are made to main memory as well as to the cache, ensuring
that main memory is always valid.
A. Write back
B. LRU
C. Write through
D. Unified cache
38. A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.
A. True
B. False
39. The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address
field.
A. True
B. False
40. The operation yields true if either or both of its operands are true.
A. NOT
B. AND
C. NAND
D. OR
41. The major cost in the life cycle of a system is hardware.
A. True
B. False
42. An interrupt is a hardware-generated signal to the processor.
A. True
B. False
43. A hazard occurs when there is a conflict in the access of an operand location.
A. Resource
B. Data
C. Structural
D. Control
44. The I/O function includes a requirement to coordinate the flow of traffic between internal resources
and external devices.
A. Cycle
B. Status reporting
C. Control and timing
D. Data
45. The only form of addressing for branch instructions is addressing.
A. Register
B. Relative
C. Base
D. Immediate
A. True
B. False
47. Register indirect addressing used the same number of memory references as indirect address
A. True
B. False
48. When using technique, all write operations are made to main memory ad well as to cache, ensure that
main memory is always valid.
A. Write back
B. LRU
C. Write though
D. Unified cache
49. Computer refers to those attributes that have a direct impact on the logical execution of a program
A. Organization
B. Specifics
C. Design
D. architecture
50. The contains the -bit opcode instruction being executed.
A. Memory buffer register
B. Instruction buffer register
C. Instruction register
D. Memory address register
51. The System bus is made up of .
A. Control bus
B. Address bus
C. Both A and B
D. Control bus, Data bus, and Address bus
E. Data bus
are a set of storage locations
A. Registers
B. Control units
C. PSWs
D. Processors
The perform the computer's data processing functions
A. sustem bus
B. Register
C. ALU
The hold the address of the next instruction to be fetched
A. MBR
B. IR
C. PC
D. MAR
The method of calculating the EA is the same for both base-register addressing and indexing
A. True
B. False
A disk is permanently mounted in the disk drive, such as the hard disk in a pers
A removable
B. double sided
C. nonremovable
D. movable-head
Which of the following memory types are nonvolatile?
A. erasable PROM
B. programmable ROM
C. flash memory
D. all of the above
Interface between the computer and peripheral is an example of an oganizationals attributes
A. False B. True
I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on
A. True
B. False
The determine the opcode and the operand specifiers
B. fetch operands
A(n) is generated by a failure such as power failure or memory parity error
A. Timer Interrupt
C. I/O interrupt
D. program interrupt
The commence consists of the access time plus any additional time required before a second access can commence
A direct access
B transterrate
C. memory cycle time
D. latency
The performed of the cache memory is measured in terms of a quanlity called ___
A Hit Ratio
C. Miss Ratio
E. Address Ratio
All DRAMs required a refresh operation
A. True
B. False
An I/O device is referred to as a
A. CPU
B. control device
C. register
D. peripheral
The basic function of a computer to execute program
A. False
B. True
The data lines provide a path for moving data among system modules and are collectively
A. control bus
B system bus
C. address bus
D. data bus
With direct addressing, the length of the address field is usually less than the word length, address range.
A. True
B. False
Cycle stealing is/are used in which concept?
A. Programmed I/O
B. DMA
C. Interrupts
E. All of the above
An I/O module recognize one unique address for each peripheral it control
A. True
B. False
is when the disk rotates more slowly for accesses near the outer edge than for the center.
A Seck time
B. Magnetoresistive
The interprets the instruction in memory and causes them to be executed.

(Choose 1 answer)
A. I/O
B control unit
C main memory
D. arithmetic and logic unit
What is stored in the Stack Pointer?
D. Operations
The controls the movement of data and instructions into and out of the processor.
A. control unit
B. ALU
C. shifter
D. branch
The routine executed in response to an interrupt request is called routine.
A Interrunt Service
C. Serial interrupt
E. Sub-routine
The correspondence between the main memory blocks and those in the cache is specified.
A. Segment function
B. Hit rate
D. Mapping function
E. Miss penalty
register may be used only to hold data and cannot be employed in the calculation address.
A General purpose
B. Condition code
C. Data
D. Address
The method of using the same lines for multiple purpose is known as time multiplexing.
A. True
B. False
Counters can be desianated as
A asvnchronous
B neither asvnchronous or synchronous
C. synchronous
D. both asynchronous and synchronous
Both batch multiprogramming and time sharing use multiprogramming.
A. True
B. False
The predict-never-taken approach is the most popular of all the branch prediction method.
A. True
B. False
Second generation computers used _
A. integrated circuits
B. large-scale integration
C. transistors
D. vacuum tubes
Architecture attributes include
A. memory technology used
B intertaces
C. control signals
D. I/O mechanisms
The register file employs much shorter addresses than addresses for cache and memory.
A. True
B. False
A common example of system interconnection is by means of a .
A data transport
B control device
C. register
D. system bus
A number of chips can be grouped together to form a memory bank
A. False
B. True
Assume an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are What is the
maximum number of one-operand instructions that can be supported? @KIZSPY20: (Choose 1 answer) Assume
an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are What is the maximum number
of one-operand instructions that can be supported? A. 256
B. 128
C. 32
D. 512
E. 64
The ABI is the boundary between hardware and software
A. False
B. True
The unary operation ___ inverts the value of its operand.
A. XOR
B. NAND
C. NOT
D. OR
Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per tr is 512 byte. What
is the disk capacity?
A. 32 MB
B. 512 KB
C. 64 KB
D. 16 GB
E. 64 MB
The cache is capable of handling global as well as local variables
A. True
B. False
When using graph coloring. nodes that share the same color cannot be assigned to the same
A. True
B. False
The most important system program is the OS.
A. True
B. False
Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer
A. False
B. True
Three of the most common uses of stack addressing are relative addressing. base-register & indexing.
A. True
B. False
is a principle by which two variable are independent of each other.
A Autondexing
B Opcode
C. Completeness
D. Orthogonality
With a batch operating system the user does not have direct access to the processor.
A. True
B. False
A bus that connects major computer components (processor, memory, I/O) is called a
A. control bus
B system bus
C. data bus
D. address bus
The instruction location immediately following the delayed brand is referred to as the
A. delay load
B. delay file
C. delay register
D. delay slot
The defines the system call interface to the operating system and the hardware r services available in a
A. API
B ISA
C. ABI
D. HLL
1. Bus that connects major computer components (processor, memory, I/O) IS called a
A. address bus
B. control bus
C. data bus
D. system bus
2. The System bus IS made up of
A. Control bus
B. Address bus
E. Data bus
3. Data are transferred to and from the disk in
A. tracks
B. gaps
C. sectors
D. pits
4. The unary operation Inverts the value of Its operand
A. OR
B. NOT
C. NANO
D. XOR
5. In a , binary values are stored using traditional flip-flop logic-gate configurations.
A. ROM
B. SRAM
C. DRAM
D. RAM
6. Timing refers to the way in which events are coordinated on the bus.
A. True
B. False
7. when using technique, all write operations are made to main memory as well as to the cache, ensuring
A. write back
B. LRU
C. write through
D. unified cache
8. The principal advantage of addressing IS that It IS a very simple form of addressing.
A. displacement
B. register
C. stack
D. Direct
A. True
B. False
10. Which properties do all semiconductor memory cells share?
A. they exhibit two stable states which can be used to represent binary 1 and 0
B. they are capable of being written into to set the state
C. they are capable of being read to sense the state
D. all of the above
11. Assume an Instruction set that uses a ftxed 14-blt Instruction length. Operand specifiers are 8 bits in length.
What IS the maxmum number of one-operand instructions that can be supported? 14=x+8=> x= 6=> 2^6=64
A. 32
B. 64
C. 128
D. 256
E. 512
12. Backward compatible means that the programs written for the older machines can be executed on the new
machine.
A. True
B. False
13. The cycle time of an Instruction pipeline IS the time needed to advance a set of Instructions one stage through
the pipeline
A. True
B. False
14. FIth a batch operating system the user does not have direct access to the processor.
A. True
B. False
15. It is common for programs, both system and application, to continue to exhibit new bugs after years of operation.
A. True
B. False
16. Within the processor there IS a set of registers that function as a level of memory above main memory and
cache in the hierarchy.
A. True
B. False
17. Register addressing IS similar to direct addressing With the only difference being that the address field refers to
a register rather than a main memory address.
A. True
B. False
18. The value of the mode field determines which addressing mode is to be used
A. True
B. False
19. The von Neumann architecture is based on which concept?
A. Data and instructions are stored in a single read-write memory
B. The contents of this memory are addressable by location
C. execution occurs in a sequential fashion
D. all of the above
20. Computers are classified into generations based on the fundamental hardware technology employed
A. True
B. False
21. The contains the 8-bit opcode instruction being executed
A. memory buffer register
B. instruction buffer register
C. instruction register
D. memory address register
22. Computer refers to those attributes that have a direct impact on the logical execution of a
program
A. organization
B. specifics
C. design
D. architecture
23. Changes in technology not only influence organization but also result in the introduction of more powerful
and more complex architectures
A. True
B. Fall
24. Cache memory is a much faster memory than the register file
A. True
B. False
25. A computer must be able to process, store, move, and control data
A. True
B. False
26. A(n) is generated by some condition that occurs as a result of an instruction execution
A .timer interrupt
B. I/O interrupt
C. program interrupt
D. hardware failure interrupt
27. A system works only one program at a time
A. batch
B. uniprogramming
C. kernel
D. privileged instruction
A. True
B. False
29. INT 21h/AH=1 is
A. write character from standard input, entry is stored in AL
B. read character from standard input, witch echo, result is stored in AL
C. write character form standard input, entry is stored in AH
D. read character from standard input, witch echo, result is stored in AH
30. Both batch multiprogramming and time sharing use multiprogramming
A. True
B. False
31. A set of I/O modules is a key element of a computer system
A. True
B. False
32. Techniques that automatically move program and data blocks into the physical main memory when the
required for execution are called
A. Associative-Mapping techniques
B. Main Memory techniques
C. Virtual Memory techniques
D. Paging techniques
33. There are typically hundreds of sectors per track and they may be either fixed or variable lengths
A. True
B. False
34. I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.
A. True
B. False
A. Control
B. Resource
C. Data
D. All of the above
36. The ENIAC is an example of a generation computer.
A. first
B. second
C. third
D. fourth
37. A system is a set of interrelated subsystems.
A. secondary
B. hierarchical
C. complex
D. functional
A. Programmed I/O
B. DMA
C. Interrupts
E. All of the above
39. A architecture is one that makes use of more, and more fine-grained pipeline stages.
A. parallel
B. superpipelined
C. superscalar
D. hybrid
40. It is possible to improve pipeline performance by automatically rearranging instructions within a program that
branch instructions occur later than actually desired.
A. True
B. False
41. The disadvantage of the software poll is that it is time consuming.
A. True
B. False
42. In a volatile memory, information decays naturally or is lost when electrical power is switched off.
A. True
B. False
43. When the magnetizable coating is applied to both sides of the platter the disk is then refer to as .
A. multiple sided
B. substrate
C. double sided
D. all of the above
A. number of operands
B. number of register sets
C. address range
D. all of the above
45. A line includes a that identifies which particular block is currently being stored.
A. cache
B. hit
C. tag
D. locality
46. The two traditional forms of RAM used in computers are DRAM and SRAM.
A. True
B. False
47. The end user is concerned mainly with the computer’s architecture.
A. True
B. False
48. A contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new
data written into it.
A. RAM
B. SRAM
C. ROM
D. flash memory
49. Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions
can be serviced and later resumed.
A. True
B. False
A. XOR
B. OR
C. AND
D. NOT
1,The disadvantage of immediate addressing is that the size of the number is restricted to the address field.
A. True
B. False
2,The cycle occurs at the beginning of each instruction cycle and causes an instrution from memory.
A. execute
B. indirect
C. fetch
D. interrupt
3,A system is a set of interrelated subsystems.
A. secondary
B. hierarchical
C. complex
D. functional
4, Interrupt processing allows an application program to be suspended in order that a variety of
conditions can be serviced and later resumed.
A. True
B. False
5, A is a special type of programming language used to provide instructions to the r
A. job control language
B. multiprogram
C. kernel
D. utility
6, Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per tr is 512 byte. What is
the disk capacity?
A. 32 MB
B. 64 MB
C. 64 KB
D. 512 KB
E. 16 GB
7, The ENIAC used
A. vacuum tubes
B. integrated circuits
C. IAS
D. transistors
8, A(n) is generated by a failure such as power failure or memory parity error.
A. I/O interrupt
C. timer interrupt
9, No single technology is optimal in satisfying the memory requirements for a computer syster
A. True
B. False
10, It is possible to improve pipeline performance by automatically rearranging instructions withir that branch
instructions occur later than actually desired.
A. True
B. False
11, The command causes the I/O module to take an item of data from the data bus a transmit that data
item to the peripheral.
A. control
B. test
C. read
D. write
12, The stores data.
A. system bus
B. I/O
C. main memory
D. control unit
13, The ISA defines the repertoire of machine language instructions that a computer can
A AEI
B API
C HLL
D. ISA
14, Register addressing is similar to direct addressing with the only difference being that the add a register rather
than a main memory address.
A. True
B. False
15, Because the 82C55A is programmable via the control register, it can be used to control varie peripheral devices.
A. True
B. False
16, The register file employs much shorter addresses than addresses for cache and memory.
A True
B. False
17, Because data are striped in very small strips. RAID 3 cannot achieve very high data transfer
A. True
B. False
18, A(n) is generated by some condition that occurs as a result of an instruction exec
A. timer interrupt
B. I/O interrupt
19, The scheduler is also known as the dispatcher.
A. long-term
B. medium-term
C. short-term
20, is a principle by which two variables are independent of each other.
A. Opcode
B. Orthogonality
C. Completeness
D. Autoindexing
21 , An error-correcting code enhances the reliability of the memory at the cost of added complex
A. True
B. False
22, An I/O module must recognize one unique address for each peripheral it controls.
A. True
B. False
23, The interconnection structure must support which transfer?
A. memory to processor
B. processor to memory
D. all of the above
24,The cache is capable of handling global as well as local variables.
A. True
В. False
25, One distinguishing characteristic of memory that is designated as is that it is pos
data from the memory and to write new data into the memory easily and rapidly.
A. RAM
B. ROM
C. EPROM
D. EEPROM
26, Which one of the following CPU registers holds the address of the storage location being acc
A. MAR (Memory address register)
B. MBR (Memory Buffer Register)
C. AC (Accumulator)
D. IR (Instruction Register)
27, Microprogramming eases the task of designing and implementing the control unit and provid
family concept.
A. True
B. False
28, With demand paging it is necessary to load an entire process into main memory.
A. True
B. False
29, refers to whether memory is internal or external to the computer.
A. Location
B. Access
C. Hierarchy
D. Tag
30, Instruction register stores
C. Instruction which is currently executed
D. Data of the current instruction
31, The consists of the access time plus any additional time required before a second
commence.
A. latency
B. memory cycle time
C. direct access
D.transfer rate
32, External memory is often equated with main memory
A,True
b,False
33, The IAS operates by repetitively performing an instruction cycle.
A,True
b,False
34, A disk is permanently mounted in the disk drive, such as the hard disk in a pers.
A. nonremovable
B. movable-head
C. double sided
D. removable
35, The two traditional forms of RAM used in computers are DRAM and SRAM.
A. True
B. False
36,
Designers wrestle with the challenge of balancing processor performance with that of main n
computer components.
A. True
B. False
37,
The operand yields true if and only if both of its operands are true.
A. XOR
B. OR
C. AND
D. NOT
38, An interrupt is generated from software and it is provoked by the execution of an instruction.
A. True
B. False
39, is a pipeline hazard.
A, Control
B, Resource
C, Data
D, All of the above
40, the register file is on the same chip as the ALU and control unit.
A. True
B. False
41, The unary operation inverts the value of its operand.
A. OR
B. NOT
C. NAND
D. XOR
42,it is a(n) design issue whether a computer will have a multiply instruction.
A. architectural
B. memory
C. elementary
D. organizational
43,
The memory transfer rate has not kept up with increases in processor speed.
A. True
B. False
44, has the advantage of large address space, however it has the disadvantage of
references.
A. Indirect addressing
B. Direct addressing
C. Immediate addressing
D. Stack addressing
45, One of the major problems in designing an instruction pipeline is assuring a steady flow of in
initial stages of the pipeline.
A. True
B. False
46,
I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on n.
A. True
B. False
47,
With the microchip is organized so that a section of memory cells are erased in a
A. flash memory
B. SDRAM
C. DRAM
D. EEPROM
48, is the standardized scheme for multiple-disk database design.
A. RAID
B. CAV
C. CLV
D. SSD
49, is a program that controls the execution of application programs and acts a between applications and the
conputer hardware.
B. operating system
C. batch system
D, nucleus
50, a society's value, perceptions, preferences, and behaviors are all part of its enviroment.
A, social
B, political
C, cultural
D, natural
E, cultural economic
The use of multiple processors on the same chip is referred to as and provides the potential to increase
performance without increasing the clock rate.
A. Multicore
B. GPU
C. Data channels
D. MPC
When data are moved over longer distances, to or from a remote device, the process is known as .
B. Registering
C. Structuring
D. Data transport
Individual blocks or records have a unique based on physical location with .
A. Associative
B. Physical access
C. Direct access
D. Sequential access
Which properties do all semiconductor memory cells share?
A. They exhibit two stable states which can be used too represent binary 1 to 10
C. They are capable of being read to sense the state
D. All of the above
The operation yields true if either or both of its operands are true.
A. Not
B. And
C. Nand
D. Or
A is an actual location in main memory.
A. Logical address
B. Partition address
C. Base address
D. Physical address
The I/O function includes a requirement to coordinate the flow of traffic between internal resources and
external devices.
A. Cycle
B. Status reporting
C. Control and timing
D. Data
A. CPU
B. Control device
C. Peripheral
D. Register
has the advantage of flexibility, but the disadvantage of complexity.
A. Stack addressing
B. Displacement addressing
C. Direct addressing
D. Register addressing
A sequence of codes or instructions is called
A. Software
B. Memory
C. An interconnect
D. A register
A line includes a that identifies which particular block is currently being stored
A. Cache
B. Hit
C. Tag
D. Locality
A. CPU
B. Control device
C. Peripheral
D. Register
A. Software
B. Memory
C. An interconnect
D. A register
A. Multicore
B. GPU
C. Data channels
D. MPC
When data are moved over longer distances, to or from a remote device, the process is known as
B. Registering
C. Structuring
D. Data transport
A. Logical address
B. Partition address
C. Base address
D. Physical address
has the advantage of flexibility, but the disadvantages of complexity.
A. Stack addressing
B. Displacement addressing
C. Direct addressing
D. Register addressing
A. Software
B. Memory
C. An interconnect
D. A register
**RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve
performace.
A. True
B. False
**Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction
program.
A. True
B. False
**The OS must determine how much processor time is to be devoted to the execution of a particular user program.
A. True
B. False
**The most important system program is the OS.
A. True
B. False
**Which one of the following CPU registers holds the address of the storage location being accessed?
A. MAR ( Memory Address Register )

B. MBR ( Memory Buffer Register )
C. AC ( Accumulator )
D. IR ( Instruction Register )
**Interfaces between the computer and peripherals is an example of an organizational attribute.
A. True
B. False
**Which of the following interrelated factors go into determining the use of the addressing bits?
A. Number of operands
B. Number of register sets
C. Address range
D. All of the above
**A characteristic of ROM is that it is volatile
A. True
B. False
**The major cost in the life cycle of a system is hardware
A. True
B. False
** The is a small cache memory associated with the instruction fetch stage of the pipeline
A. Dynamic branch
B. Loop table
D. Flag
** provide storage internal to the CPU.
A. Controll units
B. ALUs
C. Main memory
D. Registers
** is a principle by which two variables are independent of each other.
A. Opcode
B. Orthogonality
C. Completeness
D. Autoindexing
** registers may be used only to hold data and cannot be employed in the calculation of an operand address.
A. General purpose
B. Data
C. Address
D. Condition code
**A(n) is generated by a failure such as power failure or memory parity error
A. I/O interrupt
B. Hardware failure interrupt
C. Timer interrupt
D. Program interrupt
** are a set of storage locations.
A. Processors
B. PSWs
C. Registers
D. Control Units
**The von Neumann architecture is based on which concept?
A. Data and instruction are stored in a single read- write memory

C. Execution occurs in a sequential fashion
D. All of the above
**For the mode, the operand is included in the instruction
A. Immediate
B. Base
C. Register
D. Displacement
**The IAS operates by repetitively performing an instruction cycle.
A. True.
B. False.
**A line includes a that identifies which particular block is currently being stored.
A. Cache
B. Hit
C. Tag
D. Locality
** With a batch operating system the user does not have direct access to the processor
A. True
B. False
** are used in digital circuits to control signal and data routing
A. Multiplexers
B. Program counters
C. Flip-flops
D. Gates

A. software
B. memory
C. an interconnect
D. a register

A. stack addressing
B. displacement addressing
C. direct addressing
D. register addressing

A. CPU
B. control device
C. peripheral
D. register
A is an actual location in main memory

A. logical address
B. partition address
C. base address
D. Physical address
Individual blocks or records have a unique address based on physical location with
a. associative
b. physical access
c. direct access
d. sequential access
a. data communication
b. registering
c. structuring
d. data transport
a. multicore
b. GPU
c. data channels
d. MPC
a. cache
b. hit
c. tag
d. locality
external devices
A. cycle
B. status reporting
C. control and timing
D. data
The operation yields true if either or both of irs operands are true
a. NOT
b. AND
c. NAND
d. OR

a. they exhibit two stable states which can be used to represent binary 1 and 0
b. they are capable of being written into set the state
c. they are capable of being read to sense the state
d. all of the above
It is possible to improve pipeline performance by automatically rearranging instructions within a program so that
branch instructions occur later than actually desired
a. True
b. False
Cycle stealing is/ are used in which concept?

a. programmed I/O
b. DMA
c. interrupts
d. memory mapped I/O
e. All of the above
is the simplest mapping technique and maps each block of main memory into only one possible cache
line
A. Direct mapping
B. Associative mapping
C. Set associative mapping
The cycle occurs at the beginning of each instruction cycle an instruction to be fetchec from memory
A. execute
B. indirect
C. fetch
D. interrupt

A. True
B. False
Data are transferred to and from the disk in

A. tracks
B. gaps
C. sectors
D. pits
With isolated I/O there is a single address space for memory location and I/O devices
A. True
B. False
The defines the system call interface to the operating system and the hardware resources and services
A. HLL
B. API
C. ABI
D. ISA
1. The ABI is the boundary between hardware and software.

C. True
D. False
2. Assume an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are What is the maximum
number of one-operand instructions that can be supported?
A. 256
B. 128
C. 32
D. 512
E. 64

C. False
D. True
4. The cache is capable of handling global as well as local variables.
C. False
D. True
5. Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per is 512 byte. What is
the disk capacity?
A. 32 MB
B. 512 KB
C. 64 KB
D.16 GB
E. 64 MB
6. The unary operation inverts the value of its operand.
A. XOR
B. NAND
C. NOT
D. OR
7. Three of the most common uses of stack addressing are relative addressing, base-register a indexing.
C. False
D. True
8. The most important system program is the OS.

C. False
D. True
9. When using graph coloring, nodes that share the same color cannot be assighned to the same.
C. True
D. False
10. With a batch operating system the user does not have direct access to the processor.
C. True
D. False
11. is a principle by which two variables are independent of each other.
A. Autoindexing
B. Opcode
C. Completeness
D. Orthogonality
12. Because data are striped very small strips, RAID 3 cannot achieve very high data transfer.
C. True
D. False
C. True
D. False
A. Control bus
B. System bus
C. Data bus
D. Address bus
A. Data transport
B. Contron device
C. Register
D. System bus
16. Second generation computers used .
B. Integrated circuits
C. Large-scale integration
D. Transistors
E. Vacuum tubes
17. Architectural attributes include .
A. Memory technology used
B. Interfaces
C. Control signals
D. I/O mechanisms
18. The instruction location immediately following the delayed branch is referred to as the .
A. Delay load
B. Delay file
C. Delay register
D. Delay slot
19. Both batch multiprogramming and time sharing use miltiprogramming.
C. True
D. False
20. The predict-never-taken approach is the most popular of all branch prediction methods.
C. True
D. False
21. The defines the system call interface to the operating system and the hardware services available in a
A. API
B. ISA
C. ABI
D. HLL
22. registers may be used only to hold data cannot be emloyed in the calculation address.
A. General purpose
B. Condition code
C. Data
D. Address
C. True
D. False
24. Counters can be designated as .
A. Asynchronous
B. Neither asynchronous or synchronous
C. Synchronous
D. Both asynchronous or synchronous
25. The controls the movement of data and instructions into and out of the processor.
A. Control unit
B. ALU
C. Shifter
D. Branch
26. The routine executed in reponse to an interrupt request is called routine.
A. Interrupt Service
C. Serial interrupt
E. Sub-routine.
27. The correspondence between the main memory blocks and those in the cache is specified.
A. Segmemt funcition
B. Hit rate
D. Mapping function
E. Miss penalty
28. is when the disk rotates more slowly for accesses near the outer edge than for center.
A. Seek time
B. Magnetoresistive
29. The interprets the instructions in the memory and causes them to be executed.
A. I/O
B. Control unit
C. Main memory
D. arthmetic and logic unit
D. Operations
31. With direct addressing, the length of the address field is usually less than the word length, the address range.
C. True
D. False
A. Programmed I/O
B. DMA
C. Interrupts
E. All of the above
33. An I/O module must recognize one unique address for each peripheral it controls.
C. True
D. False
34. An I/O device is referred to as a .
A. CPU
B. Control device
C. Register
D. Peropheral
35. The basic function of a computer is to execute programs.
A. False
B. True
36. The data lines provide a path for moving dât among system modules and are collectively .
A. Control bus
B. System bus
C. Address bus
D. Data bus
37. The consists access time plus any additional time required before a second commence.
A. Direct access
B. Transfer rate
C. Memmory cycle time
D. Latency
38. The performance of the cache memory is measured in terms of a quantity called .
A. Hit Ratio
C. Miss Ratio
E. Address Ratio
39. All DRAMs require a refresh operation.
A. True
B. False
40. I/O channels are commonly seen on microcomputers, where as I/O controllers are used on.
A. False
B. True
41. The determines the opcode and the operand specifiers.
B. fetch operands
A. timer interrupt
C. I/O interrupt
D. program interrupt4
43. A disk is permanently mounted is the disk drive, such as the hard disk in a.
A. removable
B. double sided
C. nonremovable
D. movable-head
44. Which of the following memory types are noncolatile?
A. erasable PROM
B. programmable ROM
C. flash memory
D. all of the above
45. Interfaces between the computer and peripherals is an example of an organization attribute.
A. False
B. True
A. Registers
B. Control unit
C. PSWs
D. Processors
48. The holds the address of the next ins truction to be fetched.
A. MBR
B. IR
C. PC
D. MAR
49. The method of calculating the EA is the same for both base-register addressing and indexing.
A. False
B. True
A. system bus
B. Register
C. ALU
A. System bus
B. Address bus
C. Data bus
D. Control bus
1. Interrupts do not improve processing efficiency
A. True
B. False
2. The is a small cache memory associated with the instruction fetch stage of the pipeline.
A. Dynamic branch
B. Loop table
D. Flag
A. Erasable PROM
B. Programmable ROM
C. Flash memory
D. All of the above
4. Because the 82C55A is programmable via the control registe, it can be used to control variety of simple
peripheral devices.
A. True
B. False
5. Both batch multiprogramming and time sharing use multiprogramming.
A. True
B. False
6.* Both batch multiprogramming and time sharing use multiprogramming.
A. True
B. False
A. Register
B. System bus
C. Data transport
D. Control device
A. Register
B. System bus
C. Data transport
D. Control device
A. Register
B. System bus
C. Data transport
D. Control device
10. For the address field references a main memory address and the referenced register contains a
positive displacement from that address
A. indexing
B. Base-register addressing
C. Relative addressing
D. All of the above
11. are a set of storage locations
A. Processors
B. PSWs
C. Registers
D. Control units
A. True
B. False
A. True
B. False
B. False
A. True
B. False
15. The system bus is made up of
A. Control bus
B. Address bus
E. Data bus
16. RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve
performance
A. True
B. False
17*. RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve
performance
A. True
B. False
B. Registering
C. Structuring
D. Data transport
A. Register
C. ALU
D. System bus
20. I/O channels are commonly seen on microcomputers, Whereas I/o controllers are used on mainframes.
A. true
B. False
21*. I/O channels are commonly seen on microcomputers, Whereas I/o controllers are used on mainframes.
A. true
B. False
A. Calculation
D. Operands used
23*. determines the control and pipeline organization.
A. Calculation
D. Operands used
A. Asynchronous
B. Synchronous
C. Both asynchronous and synchronous
D. Neither asynchronous and synchronousS
A. Data communication
B. Registering
C. Structuring
D. data transport
26. The performs the computer’s data processsing functions
A. Register
C. ALU
D. system bus
27. I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes
A. True
B.False
A. Calculation
B. Execution
D. Operands used

A. asynchronous
B. synchronous
C. both asynchronous and synchronous
D. Neither asynchronous or synchronous
30. The contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter
31. Internal memory capacity is typically expressed in terms of .
A. Hertz
B. Nanos
C. Bytes
D. LOR
32. The controls the movement of dsata and instructions into and out of the processor.
A. control unit
B. ALU
C. Shifter
D. Branch
33. Cache memory is a much faster memory than the register file.
A. True
B. False
A. True
B. False
A. Relative addressing
B. Autoindexing
C. Postindexing
D. Preindexing
36. instructions are used to position quantities in register temporarily for computational operations
E. Load-and-store
F. Window
G. Complex
H. Branch
37. The number ò bits used to represent various data type is an example of an architectural attribute
C. True
D. False
38. Register indirect addressing uses the same number of memory references as indirect addressing
C. True
D. False
39. Privileged instructions are certain instructions that are designated special and can be executed only by the
monitor
C. True
D. False
40. is the standardized scheme for multiple-disk database design
E. RAID
F. CAV
G. CLV
H. SSD
41. The operation yields true if either or both of its operands are true
E. NOT
F. AND
G. NAND
H. OR
42. Designers wrestle with the challenge of balancing processor performance with that of main memory and other
computer components
C. True
D. False
43. The most common means of computer/ user interaction is a
E. keyboard / monitor
F. mouse / printer
G. modem / printer
H. monitor / printer
50. Architectural attributes include
a. I/O mechanisms
b. control signals
c. interfaces
b. direct access
c. random access
d. associative
a. True
b. False
a. True
b. False
a. I/O interrupt
c. timer interrupt
resource.
a. True
b. False
56. Indexing performed after the indirection is .
b. autoindexing
c. postindexing
d. preindexing
c. address range
d. all of the above
58. External memory is often equated with main memory.
a. True
b. False
a. MAR
b. PC
c. MBR
d. IR
60. The defines the third generation of computers
b. vacuum tube
c. transistor
d. VLSI
a. True
b. False
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
63. The ENIAC is an example of a generation computer
a. first
b. second
c. third
d. fourth
a. HLL
b. API
c. ABI
d. ISA
a. Indexing
d. all of the above
a. system bus
b. I/O
c. main memory
d. control unit
67. RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
a. True
b. False
68. The consists of the access time plus any additional time required before a second access can
commence.
a. Latency
c. direct access
d. transfer rate
a. True
b. False
70. The scheduler determines which programs are admitted to the system for processing
a. long term
b. medium-term
c. short-term
d. I/O
71. A characteristic of ROM is that if is volatile
a. True
b. False
72. 2 The basic function of a computer is to execute programs
a. True
b. False
from memory.
a. execute
b. indirect
c. fetch
d. interrupt
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
a. Control
b. Resource
c. Data
d. All of the above
76. The command is used to activate a peripheral and tell it what to do
a. control
b. test
c. read
d. write
a. True
b. False
78. The disadvantage of the software poll is that it is time consuming
a. True
b. False
79. A architecture is one that makes use of more, and more fine-grained pipeline stages
a. Parallel
b. superpipe lined
c. superscalar
d. hybrid
a. Operations
b. Addressing method
c. Stack data values
d. Address of top item
e. Address of next instruction
81. Because all devices on a synchronous bus are tied to a fixed clock rate, the system cannot take advantage
of advances in device performance
a. True
b. False
82. Because all devices on a synchronous are tied to a faced clock rate, the system cannot take advantage of
advances in device performance.
a. True
b. False
83. RAID is a set of physical disk drives viewed by the operating system as a single logical drive
a. True
b. False
a. Indexing
b. Base – register addressing
c. Relative addressing
d. All of the above
a. HLL
b. API
c. ABI
d. ISA
86. The ENIAC is an example of a generation computers
a. First
b. Second
c. Third
d. Fourth
a. flash memory
b. SDRAM
c. DRAM
d. EEPROM
a. True
b. False
89. The defines the third generation of computers.
b. vacuum tube
c. transistor
d. VLSI
90. External memory is often equipped with main memory
a. TRUE
b. FALSE
c. address range
d. All of the above
92. Indexing performed after the indirection is …. ?
a. A relative addressing
b. B. autoindexing
c. C. postindexing
d. D. Preindexing
resource
a. True
b. False
94. A(n) is generated by a failure such as power failure or more memory parity error
a. I/O interrupt
c. Time interrupt
a. True
b. False
a. True
b. False
.
b. direct access
c. random access
d. associative
98. Architect attributes include
a. I/O mechanisms
b. control signals
c. interfaces
1. The predict-never-taken approach is the most popular of all the branch prediction methods.
C. True
D. False
2. A characteristic of ROM is that it is volatile
C. True
D. False
E. Job control language
F. Operating system
G. Batch system
H. Nucleus
E. Main memory
F. Cache
G. Register storage
H. HLL
5. The correspondence between the main memory blocks and those in the cache is specified by
F. Mapping function
G. Replacement algorithm
H. Hit rate
I. Miss penalty
J. Segment function
6. Register addressing is similar to direct addressing with the only difference being that the address field refers to a
register rather than a main memory address.
C. True
D. False
C. True
D. False
8. The sum of the seek time and the rotational delay equals the , which is the time it takes to get into
position to read or write.
E. Access time
F. Gap time
G. Transfer time
H. Constant angular velocity
9. An I/O channel has the ability to execute I/O instructions, which gives it complete control over I/O operations.
C. True
D. False
10. The L1 cache is slower than the L3 cache.
C. True
D. False
11. The routine executed in response to an interrupt request is called routine.
F. Sub-routine
G. Interrupt acknowledge
H. Vectored interrupt
I. Serial interrupt
J. Interrupt Service
E. Register
F. CPU interconnection
G. ALU
H. System bus
13. The defines the system call interface to the operating system and the hardware resources and services
E. HLL
F. API
G. ABI
H. ISA
C. True
D. False
F. Operations
G. Addressing method
H. Stack data values
I. Address of top item
J. Addressing of next instruction
16. A instruction can be used to account for data and branch delays.
E. SUB
F. NOOP
G. JUMP
H. All of the above
E. XOR
F. OR
G. AND
H. NOT
18. Data are transferred to and from the disk in .
E. Tracks
F. Gaps
G. Sectors
H. Pits
19. A(n) is generated by some condition that occurs as a result of an instruction execution.
E. Timer interrupt
F. I/O interrupt
G. Program interrupt
H. Hardware failure interrupt
20. With demand paging it is necessary to load an entire process into main memory.
C. True
D. False
C. True
D. False
22. When the magnetizable coating is applied to both sides of the platter the disk is then referred to as .
E. Multiple sided
F. Substrate
G. Double sided
H. All of the above
23. With direct addressing, the length of the address field is usually less than the word length, thus limiting the
address range.
C. True
D. False
A. MAR
B. PC
C. MBR
D. IR
25. No single technology is optimal in satisfying the memory requirements for a computer system.
C. True
D. False
E. Erasable PROM
F. Programmable ROM
G. Flash memory
H. All of the above
C. True
D. False
E. Job control language
F. Operating system
G. Batch system
H. Nucleus
E. Processors
F. PSWs
G. Registers
H. Control units
30. The is connected to the address lines of the system bus.
E. MBR
F. MAR
G. wPC
H. IR
31. The basic function of computer is to execute programs.
C. True
D. False
32. The interconnection structure must support which transfer?
E. Memory to processor
F. Processor to memory
G. I/O to or from memory
H. All of the above
33. Interfaces between the computer and peripherals is an example of an organizational attribute.
C. True
D. False
34. It is a(n) issue whether the multiply instruction will be implemented by a special multiply unit or by a
mechanism that makes repeated use of add unit of the system.
E. Architectural
F. Memory
G. Mechanical
H. Organizational
E. System bus
F. I/O
G. Main memory
H. Control unit
from memory.
E. Execute
F. Indirect
G. Fetch
H. Interrupt
37. When using technique, all write operations are made to main memory as well as to the cache, ensuring
that main memory is always valid.
E. Write back
F. LRU
G. Write through
H. Unified cache
38. A control hazard occurs when two or more instructions that are already in the pipeline need the same resource.
C. True
D. False
39. The disadvantage of immediate addressing is that the size of the number is restricted to the size of the address
field.
C. True
D. False
40. The operation yields true if either or both of its operands are true.
E. NOT
F. AND
G. NAND
H. OR
41. The major cost in the life cycle of a system is hardware.
C. True
D. False
42. An interrupt is a hardware-generated signal to the processor.
C. True
D. False
43. A hazard occurs when there is a conflict in the access of an operand location.
E. Resource
F. Data
G. Structural
H. Control
44. The I/O function includes a requirement to coordinate the flow of traffic between internal resources
and external devices.
E. Cycle
F. Status reporting
G. Control and timing
H. Data
45. The only form of addressing for branch instructions is addressing.
E. Register
F. Relative
G. Base
H. Immediate
C. True
D. False
47. Register indirect addressing used the same number of memory references as indirect address
C. True
D. False
48. When using technique, all write operations are made to main memory ad well as to cache, ensure that
main memory is always valid.
E. Write back
F. LRU
G. Write though
H. Unified cache
program
E. Organization
F. Specifics
G. Design
H. architecture
50. The contains the -bit opcode instruction being executed.
E. Memory buffer register
F. Instruction buffer register
G. Instruction register
H. Memory address register
51. The System bus is made up of .
F. Control bus
G. Address bus
H. Both A and B
I. Control bus, Data bus, and Address bus
J. Data bus
are a set of storage locations
A. Registers
B. Control units
C. PSWs
D. Processors
The perform the computer's data processing functions
A. sustem bus
B. Register
C. ALU
The hold the address of the next instruction to be fetched
A. MBR
B. IR
C. PC
D. MAR
The method of calculating the EA is the same for both base-register addressing and indexing
A. True
B. False
A disk is permanently mounted in the disk drive, such as the hard disk in a pers
A removable
B. double sided
C. nonremovable
D. movable-head
Which of the following memory types are nonvolatile?
A. erasable PROM
B. programmable ROM
C. flash memory
D. all of the above
Interface between the computer and peripheral is an example of an oganizationals attributes
A. False B. True
I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on
A. True
B. False
The determine the opcode and the operand specifiers
B. fetch operands
A(n) is generated by a failure such as power failure or memory parity error
A. Timer Interrupt
C. I/O interrupt
The commence consists of the access time plus any additional time required before a second access can commence
A direct access
B transterrate
C. memory cycle time
D. latency
The performed of the cache memory is measured in terms of a quanlity called
A Hit Ratio
C. Miss Ratio
E. Address Ratio
All DRAMs required a refresh operation
A. True
B. False
A. CPU
B. control device
C. register
D. peripheral
The basic function of a computer to execute program
A. False
B. True
The data lines provide a path for moving data among system modules and are collectively
A. control bus
B system bus
C. address bus
D. data bus
With direct addressing, the length of the address field is usually less than the word length, address range.
A. True
B. False
Cycle stealing is/are used in which concept?
A. Programmed I/O
B. DMA
C. Interrupts
E. All of the above
An I/O module recognize one unique address for each peripheral it control
A. True
B. False
is when the disk rotates more slowly for accesses near the outer edge than for the center.
A Seck time
B. Magnetoresistive
The interprets the instruction in memory and causes them to be executed.

(Choose 1 answer)
A. I/O
B control unit
C main memory
D. arithmetic and logic unit
What is stored in the Stack Pointer?
D. Operations
The controls the movement of data and instructions into and out of the processor.
A. control unit
B. ALU
C. shifter
D. branch
The routine executed in response to an interrupt request is called routine.
A Interrunt Service
C. Serial interrupt
E. Sub-routine
The correspondence between the main memory blocks and those in the cache is specified.
A. Segment function
B. Hit rate
D. Mapping function
E. Miss penalty
register may be used only to hold data and cannot be employed in the calculation address.
A General purpose
B. Condition code
C. Data
D. Address
The method of using the same lines for multiple purpose is known as time multiplexing.
A. True
B. False
Counters can be desianated as
A asvnchronous
B neither asvnchronous or synchronous
C. synchronous
D. both asynchronous and synchronous
Both batch multiprogramming and time sharing use multiprogramming.
A. True
B. False
The predict-never-taken approach is the most popular of all the branch prediction method.
A. True
B. False
Second generation computers used _
E. integrated circuits
F. large-scale integration
G. transistors
H. vacuum tubes
Architecture attributes include
A. memory technology used
B intertaces
C. control signals
D. I/O mechanisms
The register file employs much shorter addresses than addresses for cache and memory.
A. True
B. False
A common example of system interconnection is by means of a .
A data transport
B control device
C. register
D. system bus
A. False
B. True
Assume an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are What is the
maximum number of one-operand instructions that can be supported? @KIZSPY20: (Choose 1 answer) Assume
an instruction set that uses a fixed 14-bit instruction length. Operand specifiers are What is the maximum number
of one-operand instructions that can be supported? A. 256
B. 128
C. 32
D. 512
E. 64
The ABI is the boundary between hardware and software
A. False
B. True
The unary operation ___ inverts the value of its operand.
A. XOR
B. NAND
C. NOT
D. OR
Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per tr is 512 byte. What
is the disk capacity?
A. 32 MB
B. 512 KB
C. 64 KB
D. 16 GB
E. 64 MB
The cache is capable of handling global as well as local variables
A. True
B. False
When using graph coloring. nodes that share the same color cannot be assigned to the same
A. True
B. False
The most important system program is the OS.
A. True
B. False
Because data are striped in very small strips, RAID 3 cannot achieve very high data transfer
A. False
B. True
Three of the most common uses of stack addressing are relative addressing. base-register & indexing.
A. True
B. False
is a principle by which two variable are independent of each other.
A Autondexing
B Opcode
C. Completeness
D. Orthogonality
With a batch operating system the user does not have direct access to the processor.
A. True
B. False
A bus that connects major computer components (processor, memory, I/O) is called a
A. control bus
B system bus
C. data bus
D. address bus
The instruction location immediately following the delayed brand is referred to as the
A. delay load
B. delay file
C. delay register
D. delay slot
The defines the system call interface to the operating system and the hardware r services available in a
A. API
B ISA
C. ABI
D. HLL
1. Bus that connects major computer components (processor, memory, I/O) IS called a
E. address bus
F. control bus
G. data bus
H. system bus
2. The System bus IS made up of
F. Control bus
G. Address bus
H. Both Control bus and Address bus
I. Control bus, Data bus and Address bus
J. Data bus
3. Data are transferred to and from the disk in
E. tracks
F. gaps
G. sectors
H. pits
4. The unary operation Inverts the value of Its operand
E. OR
F. NOT
G. NANO
H. XOR
5. In a , binary values are stored using traditional flip-flop logic-gate configurations.
E. ROM
F. SRAM
G. DRAM
H. RAM
6. Timing refers to the way in which events are coordinated on the bus.
C. True
D. False
7. when using technique, all write operations are made to main memory as well as to the cache, ensuring
E. write back
F. LRU
G. write through
H. unified cache
8. The principal advantage of addressing IS that It IS a very simple form of addressing.
E. displacement
F. register
G. stack
H. Direct
C. True
D. False
10. Which properties do all semiconductor memory cells share?
E. they exhibit two stable states which can be used to represent binary 1 and 0
F. they are capable of being written into to set the state
G. they are capable of being read to sense the state
H. all of the above
11. Assume an Instruction set that uses a ftxed 14-blt Instruction length. Operand specifiers are 8 bits in length.
What IS the maxmum number of one-operand instructions that can be supported?
F. 32
G. 64
H. 128
I. 256
J. 512
12. Backward compatible means that the programs written for the older machines can be executed on the new
machine.
C. True
D. False
13. The cycle time of an Instruction pipeline IS the time needed to advance a set of Instructions one stage through
the pipeline
C. True
D. False
14. FIth a batch operating system the user does not have direct access to the processor.
C. True
D. False
15. It is common for programs, both system and application, to continue to exhibit new bugs after years of operation.
C. True
D. False
16. Within the processor there IS a set of registers that function as a level of memory above main memory and
cache in the hierarchy.
C. True
D. False
17. Register addressing IS similar to direct addressing With the only difference being that the address field refers to
a register rather than a main memory address.
C. True
D. False
18. The value of the mode field determines which addressing mode is to be used
A. True
B. False
19. The von Neumann architecture is based on which concept?
A. Data and instructions are stored in a single read-write memory
C. execution occurs in a sequential fashion
D. all of the above
20. Computers are classified into generations based on the fundamental hardware technology employed
A. True
B. False
21. The contains the 8-bit opcode instruction being executed
A. memory buffer register
B. instruction buffer register
C. instruction register
D. memory address register
program
A. organization
B. specifics
C. design
D. architecture
23. Changes in technology not only influence organization but also result in the introduction of more powerful
and more complex architectures
A. True
B. Fall
24. Cache memory is a much faster memory than the register file
A. True
B. False
25. A computer must be able to process, store, move, and control data
A. True
B. False
26. A(n) is generated by some condition that occurs as a result of an instruction execution
A .timer interrupt
B. I/O interrupt
27. A system works only one program at a time
A. batch
B. uniprogramming
C. kernel
D. privileged instruction
A. True
B. False
29. INT 21h/AH=1 is
A. write character from standard input, entry is stored in AL
B. read character from standard input, witch echo, result is stored in AL
C. write character form standard input, entry is stored in AH
D. read character from standard input, witch echo, result is stored in AH
30. Both batch multiprogramming and time sharing use multiprogramming
A. True
B. False
31. A set of I/O modules is a key element of a computer system
A. True
B. False
32. Techniques that automatically move program and data blocks into the physical main memory when the
required for execution are called
A. Associative-Mapping techniques
B. Main Memory techniques
C. Virtual Memory techniques
D. Paging techniques
33. There are typically hundreds of sectors per track and they may be either fixed or variable lengths
A. True
B. False
34. I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on mainframes.
A. True
B. False
A. Control
B. Resource
C. Data
D. All of the above
36. The ENIAC is an example of a generation computer.
A. first
B. second
C. third
D. fourth
37. A system is a set of interrelated subsystems.
A. secondary
B. hierarchical
C. complex
D. functional
A. Programmed I/O
B. DMA
C. Interrupts
E. All of the above
39. A architecture is one that makes use of more, and more fine-grained pipeline stages.
A. parallel
B. superpipelined
C. superscalar
D. hybrid
40. It is possible to improve pipeline performance by automatically rearranging instructions within a program that
branch instructions occur later than actually desired.
A. True
B. False
41. The disadvantage of the software poll is that it is time consuming.
A. True
B. False
42. In a volatile memory, information decays naturally or is lost when electrical power is switched off.
A. True
B. False
43. When the magnetizable coating is applied to both sides of the platter the disk is then refer to as .
A. multiple sided
B. substrate
C. double sided
D. all of the above
A. number of operands
B. number of register sets
C. address range
D. all of the above
45. A line includes a that identifies which particular block is currently being stored.
A. cache
B. hit
C. tag
D. locality
46. The two traditional forms of RAM used in computers are DRAM and SRAM.
A. True
B. False
47. The end user is concerned mainly with the computer’s architecture.
A. True
B. False
48. A contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new
data written into it.
A. RAM
B. SRAM
C. ROM
D. flash memory
49. Interrupt processing allows an application program to be suspended in order that a variety of interrupt conditions
can be serviced and later resumed.
A. True
B. False
A. XOR
B. OR
C. AND
D. NOT
1,The disadvantage of immediate addressing is that the size of the number is restricted to the address field.
A. True
B. False
2,The cycle occurs at the beginning of each instruction cycle and causes an instrution from memory.
A. execute
B. indirect
C. fetch
D. interrupt
3,A system is a set of interrelated subsystems.
A. secondary
B. hierarchical
C. complex
D. functional
4, Interrupt processing allows an application program to be suspended in order that a variety of
conditions can be serviced and later resumed.
A. True
B. False
5, A is a special type of programming language used to provide instructions to the r
B. multiprogram
C. kernel
D. utility
6, Consider a magnetic disk drive with 4 surfaces, 512 tracks per surface, and 32 sectors per tr is 512 byte. What is
the disk capacity?
A. 32 MB
B. 64 MB
C. 64 KB
D. 512 KB
E. 16 GB
7, The ENIAC used
A. vacuum tubes
B. integrated circuits
C. IAS
D. transistors
8, A(n) is generated by a failure such as power failure or memory parity error.
A. I/O interrupt
C. timer interrupt
9, No single technology is optimal in satisfying the memory requirements for a computer syster
A. True
B. False
10, It is possible to improve pipeline performance by automatically rearranging instructions withir that branch
instructions occur later than actually desired.
A. True
B. False
11, The command causes the I/O module to take an item of data from the data bus a transmit that data
item to the peripheral.
A. control
B. test
C. read
D. write
12, The stores data.
A. system bus
B. I/O
C. main memory
D. control unit
13, The ISA defines the repertoire of machine language instructions that a computer can
A AEI
B API
C HLL
D. ISA
14, Register addressing is similar to direct addressing with the only difference being that the add a register rather
than a main memory address.
A. True
B. False
15, Because the 82C55A is programmable via the control register, it can be used to control varie peripheral devices.
A. True
B. False
16, The register file employs much shorter addresses than addresses for cache and memory.
A True
B. False
17, Because data are striped in very small strips. RAID 3 cannot achieve very high data transfer
A. True
B. False
18, A(n) is generated by some condition that occurs as a result of an instruction exec
A. timer interrupt
B. I/O interrupt
19, The scheduler is also known as the dispatcher.
A. long-term
B. medium-term
C. short-term
20, is a principle by which two variables are independent of each other.
A. Opcode
B. Orthogonality
C. Completeness
D. Autoindexing
21 , An error-correcting code enhances the reliability of the memory at the cost of added complex
A. True
B. False
22, An I/O module must recognize one unique address for each peripheral it controls.
A. True
B. False
23, The interconnection structure must support which transfer?
A. memory to processor
B. processor to memory
D. all of the above
24,The cache is capable of handling global as well as local variables.
A. True
В. False
25, One distinguishing characteristic of memory that is designated as is that it is pos
data from the memory and to write new data into the memory easily and rapidly.
A. RAM
B. ROM
C. EPROM
D. EEPROM
26, Which one of the following CPU registers holds the address of the storage location being acc
A. MAR (Memory address register)
B. MBR (Memory Buffer Register)
C. AC (Accumulator)
D. IR (Instruction Register)
27, Microprogramming eases the task of designing and implementing the control unit and provid
family concept.
A. True
B. False
28, With demand paging it is necessary to load an entire process into main memory.
A. True
B. False
29, refers to whether memory is internal or external to the computer.
A. Location
B. Access
C. Hierarchy
D. Tag
30, Instruction register stores
C. Instruction which is currently executed
D. Data of the current instruction
31, The consists of the access time plus any additional time required before a second
commence.
A. latency
B. memory cycle time
C. direct access
D.transfer rate
32, External memory is often equated with main memory
A,True
b,False
33, The IAS operates by repetitively performing an instruction cycle.
A,True
b,False
34, A disk is permanently mounted in the disk drive, such as the hard disk in a pers.
A. nonremovable
B. movable-head
C. double sided
D. removable
35, The two traditional forms of RAM used in computers are DRAM and SRAM.
A. True
B. False
36,
Designers wrestle with the challenge of balancing processor performance with that of main n
computer components.
A. True
B. False
37,
The operand yields true if and only if both of its operands are true.
A. XOR
B. OR
C. AND
D. NOT
38, An interrupt is generated from software and it is provoked by the execution of an instruction.
A. True
B. False
39, is a pipeline hazard.
A, Control
B, Resource
C, Data
D, All of the above
40, the register file is on the same chip as the ALU and control unit.
A. True
B. False
41, The unary operation inverts the value of its operand.
A. OR
B. NOT
C. NAND
D. XOR
42,it is a(n) design issue whether a computer will have a multiply instruction.
A. architectural
B. memory
C. elementary
D. organizational
43,
The memory transfer rate has not kept up with increases in processor speed.
A. True
B. False
44, has the advantage of large address space, however it has the disadvantage of
references.
A. Indirect addressing
B. Direct addressing
C. Immediate addressing
D. Stack addressing
45, One of the major problems in designing an instruction pipeline is assuring a steady flow of in
initial stages of the pipeline.
A. True
B. False
46,
I/O channels are commonly seen on microcomputers, whereas I/O controllers are used on n.
A. True
B. False
47,
With the microchip is organized so that a section of memory cells are erased in a
A. flash memory
B. SDRAM
C. DRAM
D. EEPROM
48, is the standardized scheme for multiple-disk database design.
A. RAID
B. CAV
C. CLV
D. SSD
49, is a program that controls the execution of application programs and acts a between applications and the
conputer hardware.
B. operating system
C. batch system
D, nucleus
50, a society's value, perceptions, preferences, and behaviors are all part of its enviroment.
A, social
B, political
C, cultural
D, natural
E, cultural economic
E. Multicore
F. GPU
G. Data channels
H. MPC
When data are moved over longer distances, to or from a remote device, the process is known as .
E. Data communications
F. Registering
G. Structuring
H. Data transport
Individual blocks or records have a unique based on physical location with .
E. Associative
F. Physical access
G. Direct access
H. Sequential access
E. They exhibit two stable states which can be used too represent binary 1 to 10
F. They are capable of being written into to set the state
G. They are capable of being read to sense the state
H. All of the above
The operation yields true if either or both of its operands are true.
E. Not
F. And
G. Nand
H. Or
E. Logical address
F. Partition address
G. Base address
H. Physical address
external devices.
E. Cycle
F. Status reporting
G. Control and timing
H. Data
E. CPU
F. Control device
G. Peripheral
H. Register
E. Stack addressing
F. Displacement addressing
G. Direct addressing
H. Register addressing
E. Software
F. Memory
G. An interconnect
H. A register
E. Cache
F. Hit
G. Tag
H. Locality
E. CPU
F. Control device
G. Peripheral
H. Register
E. Software
F. Memory
G. An interconnect
H. A register
E. Multicore
F. GPU
G. Data channels
H. MPC
E. Data communications
F. Registering
G. Structuring
H. Data transport
E. Logical address
F. Partition address
G. Base address
H. Physical address
has the advantage of flexibility, but the disadvantages of complexity.
E. Stack addressing
F. Displacement addressing
G. Direct addressing
H. Register addressing
E. Software
F. Memory
G. An interconnect
H. A register
**RAID level 0 is not a true member of the RAID family because it does not include redundancy to improve
performace.
C. True
D. False
**Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction
program.
C. True
D. False
**The OS must determine how much processor time is to be devoted to the execution of a particular user program.
C. True
D. False
**The most important system program is the OS.
C. True
D. False
**Which one of the following CPU registers holds the address of the storage location being accessed?
E. MAR ( Memory Address Register )

F. MBR ( Memory Buffer Register )
G. AC ( Accumulator )
H. IR ( Instruction Register )
**Interfaces between the computer and peripherals is an example of an organizational attribute.
C. True
D. False
**Which of the following interrelated factors go into determining the use of the addressing bits?
E. Number of operands
F. Number of register sets
G. Address range
H. All of the above
**A characteristic of ROM is that it is volatile
C. True
D. False
**The major cost in the life cycle of a system is hardware
C. True
D. False
** The is a small cache memory associated with the instruction fetch stage of the pipeline
E. Dynamic branch
F. Loop table
G. Branch history table
H. Flag
** provide storage internal to the CPU.
E. Controll units
F. ALUs
G. Main memory
H. Registers
** is a principle by which two variables are independent of each other.
E. Opcode
F. Orthogonality
G. Completeness
H. Autoindexing
** registers may be used only to hold data and cannot be employed in the calculation of an operand address.
E. General purpose
F. Data
G. Address
H. Condition code
**A(n) is generated by a failure such as power failure or memory parity error
E. I/O interrupt
F. Hardware failure interrupt
G. Timer interrupt
H. Program interrupt
** are a set of storage locations.
E. Processors
F. PSWs
G. Registers
H. Control Units
**The von Neumann architecture is based on which concept?
E. Data and instruction are stored in a single read- write memory

F. The contents of this memory are addressable by location
G. Execution occurs in a sequential fashion
H. All of the above
**For the mode, the operand is included in the instruction
E. Immediate
F. Base
G. Register
H. Displacement
**The IAS operates by repetitively performing an instruction cycle.
C. True.
D. False.
**A line includes a that identifies which particular block is currently being stored.
E. Cache
F. Hit
G. Tag
H. Locality
** With a batch operating system the user does not have direct access to the processor
C. True
D. False
** are used in digital circuits to control signal and data routing
E. Multiplexers
F. Program counters
G. Flip-flops
H. Gates

E. software
F. memory
G. an interconnect
H. a register

E. stack addressing
F. displacement addressing
G. direct addressing
H. register addressing

E. CPU
F. control device
G. peripheral
H. register
A is an actual location in main memory

E. logical address
F. partition address
G. base address
H. Physical address
Individual blocks or records have a unique address based on physical location with
e. associative
f. physical access
g. direct access
h. sequential access
e. data communication
f. registering
g. structuring
h. data transport
e. multicore
f. GPU
g. data channels
h. MPC
e. cache
f. hit
g. tag
h. locality
external devices
E. cycle
F. status reporting
G. control and timing
H. data
The operation yields true if either or both of irs operands are true
e. NOT
f. AND
g. NAND
h. OR

e. they exhibit two stable states which can be used to represent binary 1 and 0
f. they are capable of being written into set the state
g. they are capable of being read to sense the state
h. all of the above
It is possible to improve pipeline performance by automatically rearranging instructions within a program so that
branch instructions occur later than actually desired
c. True
d. False
Cycle stealing is/ are used in which concept?

f. programmed I/O
g. DMA
h. interrupts
i. memory mapped I/O
j. All of the above
is the simplest mapping technique and maps each block of main memory into only one possible cache
line
E. Direct mapping
F. Associative mapping
G. Set associative mapping
H. None of the above
The cycle occurs at the beginning of each instruction cycle an instruction to be fetchec from memory
E. execute
F. indirect
G. fetch
H. interrupt

C. True
D. False
Data are transferred to and from the disk in

E. tracks
F. gaps
G. sectors
H. pits
With isolated I/O there is a single address space for memory location and I/O devices
C. True
D. False
The defines the system call interface to the operating system and the hardware resources and services
E. HLL
F. API
G. ABI
G. ISA
Questions & Answers – RAID Structure – 1

This set of Operating System Multiple Choice Questions & Answers (MCQs) focuses on “RAID Structure – 1”.
1. RAID level 3 supports a lower number of I/Os per second, because _______________
a) Every disk has to participate in every I/O request
b) Only one disk participates per I/O request
c) I/O cycle consumes a lot of CPU time
d) All of the mentioned
View Answer
Answer: a
Explanation: None.
2. RAID level _____ is also known as block interleaved parity organisation and uses block level striping and keeps a
parity block on a separate disk.
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: d
Explanation: None.
3. A performance problem with _________ is the expense of computing and writing parity.
a) non-parity based RAID levels
b) parity based RAID levels
c) all RAID levels
d) none of the mentioned
View Answer
Answer: b
Explanation: None.
4. In RAID level 4, one block read, accesses __________
a) only one disk
b) all disks simultaneously
c) all disks sequentially
View Answer
Answer: a
Explanation: Other requests are allowed to be processed by other disks.
5. The overall I/O rate in RAID level 4 is ____________
a) low
b) very low
c) high
View Answer
Answer: c
Explanation: All disks can be read in parallel.
6. A write of a block has to access ____________
a) the disk on which the block is stored
b) parity disk
c) a parity block
d) all of the mentioned
View Answer
Answer: d
Explanation: None.
7. RAID level 5 is also known as ____________
a) bit-interleaved parity organization
b) block-interleaved parity organization
c) block-interleaved distributed parity
d) memory-style ECC organization
View Answer
Answer: c
Explanation: None.
8. RAID level ____ spreads parity and data among all N+1 disks rather than storing data in N disks and parity in 1.
a) 3
b) 4
c) 5
d) 6
View Answer
Answer: c
Explanation: None.
9. The potential overuse of a single parity disk is avoided in RAID level _______
a) 3
b) 4
c) 5
d) all of the mentioned
View Answer
Answer: c
Explanation: None.
10. RAID level 0+1 is used because, RAID level 0 provides ______ whereas RAID level 1 provides ________
a) performance, redundancy
b) performance, reliability
c) redundancy, performance
View Answer
Answer: b
Explanation: None.
11. If a disk fails in RAID level ___________ rebuilding lost data is easiest.
a) 1
b) 2
c) 3
d) 4
View Answer
Answer: a
Explanation: Data can be copied from another disk in raid level 1, for other raid levels all other disks have to be
accessed.
12. Where performance and reliability are both important, RAID level ____ is used.
a) 0
b) 1
c) 2
d) 0+1
View Answer
Answer: d
Explanation: None.

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1 Computer technology is changing at a pace.

3 Architectural attributes include .

4 attributes include hardware details transparent to the programmer.

5 It is a(n) design issue whether a computer will have a multiply instruction.

7 A system is a set of interrelated subsystems.

8 An I/O device is referred to as a .

10 The stores data.

11 A common example of system interconnection is by means of a .

14 provide storage internal to the CPU.

15 The performs the computer's data processing functions.

16 The ALU makes use of to store the immediate results

18 Computer organization refers to (Select all correct answers):

20 When considering the memory technology used, we are referring to:

21 Software compatibility, in point of view of the architecture, want to mention that:

22 Who are interested in computers with architectural look?

23 Who are interested in computers with organizational look?

24 Statement I: Structure is the way in which the components are interrelated.

25 The basic functions of the computer:

26 The basic components of the computer:

28 The memory system of computers include:

29 A common example of system interconnection is by means of a ..........., consisting of a number of

30 In the computer, there are the following types of system interconnections:

31 Another word for the CPU is

1 The was the world's first general-purpose electronic digital computer.

a. the Civil War

3 The ENIAC used .

4 The ENIAC is an example of a generation computer.

5 The interprets the instructions in memory and causes them to be executed.

6 The memory of the IAS consists of 1000 storage locations called .

7 The contains the 8-bit opcode instruction being executed.

9 Second generation computers used .

10 The defines the third generation of computers.

13 The measures the ability of a computer to complete a single task.

14 ARM processors are designed to meet the needs of .

15 One increment, or pulse, of the system clock is referred to as a .

16 In the concept of "stored program", the computer fetches instructions ........

17 The concept of "stored program" allows:

18 Von Neumann is computer: (Select all correct answers)

19 So far, computers have grown through:

A. The first generation uses a vacuum tube

B. The third generation uses transistors

C. The fourth-generation uses SSI and MSI

D. None of the others

22 When did the first transistor be invented?

24 The invention of integrated circuit brought us .......... of computers.

25 A silicon piece with electronic circuits on it is called .......

26 Which parameters in a computer family are similar or identical?

29 What are the main goals of a computer system?

A. To provide the best performance at a low cost

B. To provide speedy operation at low power consumption

C. To provide optimal power operation

D. None of the others

31 In the given figure, black rectangles are ........

32 Balance of performance is to ........

33 Which of the following is not a solution to balance performance?

34 An approach to increase the speed of the processor is ........

35 Which of the following is not a reason for moving to multicore organizations?

a. data and instructions are stored in a single read-write memory

a. Process intra-connectivity circuitry

1 refers to whether memory is internal or external to the computer.

a. RAM and ROM