EEN220

Introduction To Logic Design

CO2: Ability to design CHAPTER 6
and innovate logic
circuit using Boolean COMBINATIONAL
algebra and
combinational logic
LOGIC DESIGN
design techniques.
 Functional Blocks
 A functional block is a combinational circuit
 We will study blocks, such as decoders and multiplexers
 Functional blocks are very common and useful in design
 In the past, functional blocks were integrated circuits
SSI: Small Scale Integration = tens of gates
MSI: Medium Scale Integration = hundreds of gates
LSI: Large Scale Integration = thousands of gates
VLSI: Very Large Scale Integration = millions of gates
 Today, functional blocks are part of a design library
 Tested for correctness and reused in many projects
Combinational Arithmetic Circuits
 Addition:
o Half Adder (HA)
o Full Adder (FA)
o Carry Ripple Adders
 Subtraction:
o Half Subtractor
o Full Subtractor
o Borrow Ripple Subtractors
o Subtraction using adders
 Half Adder (HA)
 Adding two single-bit binary values, A, B produces a sum S bit
and a carry out Cout bit.
 This operation is called half addition and the circuit to realize it
is called a half adder.
Half Adder Truth Table: S = A’B + AB’
Inputs Outputs S = AB
A B S Cout C-out = AB
0 + 0 = 0 0
0 + 1 = 1 0
1 + 0 = 1 0
1 + 1 = 0 1
A Half S
B Adder COUT circuit
Block diagram
 Full Adder A’B(Cin)’
 Adding two single-bit binary Sum S A
AB’(Cin)’
values, A, B with a carry input AB
C-in 00 01 11 10
bit C-in produces a sum bit S 0 2 6 4
and a carry out C-out bit. 0 1 1
1 3 7 5
1 1 1 C-in

Full Adder Truth Table

A’B’(Cin) B
AB(Cin)
Inputs Outputs
A B Cin S Cout
S = A’B’(C-in) + A’B(C-in)’ + AB’(C-in)’ + AB(C-in)
0 + 0 + 0
= 0 0 S = A  B  (C-in)
0 + 0 + 1
= 1 0
0 + 1 =
+ 0 1 0 AB A(C-in)
Carry C-out A
0 + 1 + 1
= 0 1 AB
1 + 0 + 0
= 1 0 C-in 00 01 11 10
1 + 0 + 1
= 0 1 0
0 2 6
1
4

1 + 1 + 0 0 1 B(Cin)
= 1 3 7 5
1 + 1 + 1 1 1 1 `1 1 1 Cin
=
S(A,B,Cin) = Sm(1,2,4,7) B
C-out(A,B,Cin) = Sm(3,5,6,7) C-out = AB + A(Cin) + B(Cin)
 Full Adder
 Full Adder Circuit Using X-OR:

A B

Full
C-out C-in
Adder

Block diagram

Circuit
 Full Adder
 Design Full Adder by using Half Adder

S
A
S
B
Cout
Cin

Symbol
 n-bit Carry Ripple Adder
A single full adder is capable of adding 1 bit numbers and an input
carry.
 An n-bit adder expansion used to add binary numbers with
more than one bit(2 bit, 3 bit, 4 bit…n bit)
 If there are 2-bit numbers, two adders are needed; for 4-bit
numbers, four adders are used and so on.
 It can built by cascading all the adders.
o Carry input of full adder for least significant position is 0
(grounded).
o The carry output of each adder is connected to the carry
input of the next higher-order adder.

MSB LSB
 4-bit Carry Ripple Adder
Inputs to be added
Adds two 4-bit numbers:
A3A2A1A0 B3B2B1B0
A = A3 A2 A1 A0
B= B3 B2 B1 B0
producing the sum S = S3 S2 S1 S0 ,
C-out = C4 from the most significant 4-bit
C4 C-out C-in C0 =0
position j=3 Adder

Total Propagation delay = 2 nD = 8D

or 8 gate delays S3 S2 S1 S0

Sum Output

Data inputs to be added

A3 B3 A2 B2 A1 B1 A0 B0

Full C3 Full C2 Full C1 Full

C4 C-out C-in C-out C-in C-out C-in C-out C-in C0 =0
Adder Adder Adder Adder

S3 S2 S1 S0
Sum output
 An example of 4-bit addition
• Let’s try our initial example: A=1011 (eleven), B=1110 (fourteen).

1 1 1 0 1 1 0 1

0
1 1 0

1 1 0 0 1

1. Fill in all the inputs, including CI=0

2. The circuit produces C1 and S0 (1 + 0 + 0 = 01)
3. Use C1 to find C2 and S1 (1 + 1 + 0 = 10)
4. Use C2 to compute C3 and S2 (0 + 1 + 1 = 10)
5. Use C3 to compute CO and S3 (1 + 1 + 1 = 11)
Woohoo! The final answer is 11001 (twenty-five).
Combinational Arithmetic Circuits
 Comparator
 Encoder
 Decoder
 Multiplexer
 Demultiplexer
 Comparator
 To compare the values of two binary strings (or binary
words) to determine if they are exactly equal, greater than
or less than.
 Truth table for a comparator:

What is the Boolean expression

for this truth table?
Can you draw the circuit for basic
comparator?
 Comparator
 Example: Determine the A=B, A>B, and A<B outputs for
the input numbers shown on the comparator as below:

 The number on the A inputs is 01102=610 and the

number on the B inputs is 00112=310 . Therefore, the A>B
output is HIGH and the other outputs are LOW
 Comparator
 Another example, to design a comparator to evaluate
two 4 bit numbers, we need 4 Ex-NORs and a 4 input
AND gates
 8 bit magnitude comparator:
 Multiplexers
 Selecting data is an essential function in digital systems

 Functional blocks that perform selecting are called multiplexers

 A Multiplexer (or Mux) is a combinational circuit that has:

◦ Multiple data inputs (typically 2n) to select from d0

d1

2n Inputs
◦ An n-bit select input S used for control d2

Mux
. Y
.
.
◦ One output Y d2n–1
n

 S
The n-bit select input directs one of the data inputs to the output
 Multiplexer
 Data selector
 SELECT input code determines
which input is transmitted to
output Z.

2 inputs multiplexer
Multiplexer

4 inputs multiplexer
Multiplexer

Block diagram 4-to-1 MUX

 Multiplexer
 Larger multiplexers can be constructed from smaller ones.
 An 8-to-1 multiplexer can be constructed from smaller
multiplexers as shown:
 Building Larger Multiplexers
• Large multiplexers can be made by cascading smaller ones

Alternative Implementation

S1 S0
S2
control signals B and C simultaneously choose
one of I0, I1, I2, I3 and one of I4, I5, I6, I7
S2 S0
S1
control signal A chooses which of the upper or
lower mux's output to gate to Z
 Building Larger Multiplexers
Larger multiplexers can be built hierarchically using smaller ones

d0 0 d0 0
d0 0 d1 1 d1 1

Mux
Mux

d2 2

8-to-1 Mux
d1 1 d2 2
0 d3 3
d3 3
Mux

S0 Y Y
1 0 d4 4

Mux
d2 0 S1S0 Y d5 5
Mux

S1 1
d3 1 d6 6
d4 0
S2 d7 7
d5 1
Mux
S0
d6 2 S2S1S0
d7 3

Building 4-to-1 S1S0 Building 8-to-1 Mux

Mux using three using two 4-to-1 Muxes
2-to-1 Muxes and a 2-to-1 Mux
Implementing a Function with a Multiplexer
 A Multiplexer can be used to implement any logic function
 The function must be expressed using its minterms
 Example: Implement F(a, b, c) = ∑(1, 2, 6, 7) using a Mux
 Solution:
Inputs Output
0 0
a b c F 1
1
The inputs are 0 0 0 0
1 2

8-to-1 Mux
used as select 0 0 1 1
0 3
lines to a Mux. 0 1 0 1 F
0 4
0 1 1 0
An 8-to-1 1 0 0 0 0 5
Mux is used 1 0 1 0 1 6

because there 1 1 0 1 1 7 1
0
2
1 1 1 1
are 3 variables
S2 S1 S0 = a b c
Better Solution with a Smaller Multiplexer
 Re-implement F(a, b, c) = ∑(1, 2, 6, 7) using a 4-to-1 Mux
 We will use the two select lines for variables a and b
 Variable c and its complement are used as inputs to the Mux

Inputs Output Comment

a b c F F
0 0 0 0
F=c c 0
0 0 1 1

4-to-1 Mux
0 1 0 1
F = c' c' 1
0 1 1 0 F
1 0 0 0 0 2
F=0
1 0 1 0
0
1 1 0 1 1 3 1
F=1
1 1 1 1
S1 S0 = a b
 Implementing Functions: Example 2
Implement F(a, b, c, d) = ∑(1,3,4,11,12,13,14,15) using 8-to-1 Mux
Inputs Output Comment
a b c d F F
0 0 0 0 0 d 0
0 0 0 1 1
F=d
0 0 1 0 0 1
0 0 1 1 1
F=d
0 1 0 0 1
2

8-to-1 Mux
0 1 0 1 0
F = d'
0 3
0 1 1 0 0 F
0 1 1 1 0
F=0 4
1 0 0 0 0 5
1 0 0 1 0
F=0
1 0 1 0 0 1 6
1 0 1 1 1
F=d
0
1 1 0 0 1
7 1
2
1 1 0 1 1
F=1
1 1 1 0 1
1 1 1 1 1
F=1 S2 S1 S0 = a b c
 Multiplexers as general logic purpose
A 2n:1 multiplexer can implement any function of n variables
-with the variables used as control inputs and
-the data inputs tied to 0 or 1

Example
F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC’ + ABC
= A'B'C‘(1) + A’B’C(0) + A'BC‘(1) + A’BC(0)
+ AB’C‘(0) + AB’C(0) + ABC’(1) + ABC(1)

We know that the output of the multiplexer is:

Z = A'B'C‘I0 + A’B’CI1 + A'BC‘I2 + A’BCI3
+ AB’C‘I4 + AB’CI5 + ABC’I6 + ABCI7
So when we compare Z with F, we can indicate
The inputs of the multiplexer
 Multiplexers as general logic purpose
• Muxes can be used to implement arbitrary functions.
• One way to implement a function of n variables is to use an n-to-1 mux:

– For each minterm mi of the function, connect 1 to mux data input Di.
Each data input corresponds to one row of the truth table.
– Connect the function’s input variables to the mux select inputs. These
are used to indicate a particular input combination.

For example, let’s look at f(x,y,z) = Sm(1,2,6,7).

x y z f
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
 Multiplexers as general logic purpose
• We can actually implement f(x,y,z) = Sm(1,2,6,7) with x y z f
just a 4-to-1 mux, instead of an 8-to-1. 0 0 0 0
• Step 1: Find the truth table for the function, and 0 0 1 1
group the rows into pairs. Within each pair of rows, x 0 1 0 1
and y are the same, so f is a function of z only. 0 1 1 0
– When xy = 00, f=z 1 0 0 0
– When xy = 01, f=z’ 1 0 1 0
– When xy = 10, f=0 1 1 0 1
– When xy = 11, f=1 1 1 1 1

• Step 2: Connect the first two input variables of the

truth table (here, x and y) to the select bits S1 S0 of
the 4-to-1 mux.

• Step 3: Connect the equations above for f(z) to the

data inputs D0-D3.
 Multiplexers as general logic purpose

F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'(C') + A'B(C') + AB'(0) + AB(1)
 Examples of Multiplexers
 2-to-1 Multiplexer Inputs Output
d0 0
if (S == 0) Y = d0 ; S d0 d 1 Y

Mux
Y
else Y = d1; d1 1
0 0 X 0 = d0
0 1 X 1 = d0
Logic expression: 1 X 0 0 = d1
′
S 1 X 1 1 = d1
𝑌 = 𝑑0 𝑆 + 𝑑1 𝑆

 4-to-1 Multiplexer d0 0 Inputs Output

if (S1S0 == 00) Y = d0 ; d1 1 S1 S0 d 0 d 1 d 2 d 3 Y

Mux
𝑌
else if (S1S0 == 01) Y = d1; d2 2 0 0 0 X X X 0 = d0
3 0 0 1 X X X 1 = d0
else if (S1S0 == 10) Y = d2; d3
0 1 X 0 X X 0 = d1
else Y = d3; S1S0 0 1 X 1 X X 1 = d1
1 0 X X 0 X 0 = d2
Logic expression: 1 0 X X 1 X 1 = d2
𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆2 1 1 X X X 0 0 = d3
1 1 X X X 1 1 = d3
 Implementing Multiplexers
d0
d0 0
Mux

𝑌 = 𝑑0 𝑆 ′ + 𝑑1 𝑆 Y
d1
d1 1
Enabling
S AND Gates
S

d0
d0 0
d1
d1 1
Mux

𝑌 = 𝑑0 𝑆1′ 𝑆0′ + 𝑑1 𝑆1′ 𝑆0 d2 Y

d2 2
d3 3 + 𝑑2 𝑆1 𝑆0′ + 𝑑3 𝑆1 𝑆0
d3
S1S0
Enabling
S1 AND Gates
S0
 3-State Gate
 Logic gates studied so far have two outputs: 0 and 1
 Three-State gate has three possible outputs: 0, 1, Z
◦ Z is the Hi-Impedance output
◦ Z means that the output is disconnected from the input
◦ Gate behaves as an open switch between input and output

 Input c connects input to output c x f

◦ c is the control (enable) input 𝑐 0 0 Z

0 1 Z
◦ If c is 0 then f = Z 𝑥 𝑓 1 0 0
◦ If c is 1 then f = input x 3-state gate 1 1 1
 Variations of the 3-State Gate
 Control input c and output f can be inverted
 A bubble is inserted at the input c or output f
𝑐 𝑐 𝑐

𝑥 𝑓 𝑥 𝑓 𝑥 𝑓
inverted c inverted f inverted c, f
c x f c x f c x f
0 0 0 0 0 Z 0 0 1
0 1 1 0 1 Z 0 1 0
1 0 Z 1 0 1 1 0 Z
1 1 Z 1 1 0 1 1 Z
 Wired Output
Logic gates with 0 and 1
outputs cannot have their
outputs wired together
𝑎 This will result in a
𝑏
𝑓 short circuit that
𝑐
𝑑 will burn the gates

𝑐1 c1 c2 c3 f
3-state gates can wire 0 0 0 Z
their outputs together 𝑥1 1 0 0 x1
𝑐2 0 1 0 x2
At most one 3-state gate 𝑓
0 0 1 x3
𝑥2
can be enabled at a time 0 1 1 Burn
𝑐3 1 0 1 Burn
Otherwise, conflicting 1 1 0 Burn
𝑥3
outputs will burn the circuit 1 1 1 Burn
 Implementing Multiplexers with 3-State Gates
A Multiplexer can also d0 0

be implemented using: d1 1

Mux
2
𝑌
1. A decoder d2 3-State
d3 3 Gates
2. Three-state gates
d0
S1S0

3-State
d1
Gates Y
d0 0 d0 d2
Mux

Y Y
d1 1 d1 d3

S 0 1 2 3
S S1 1 2-to-4
1-to-2
Decoder S0 0 Decoder
 Demultiplexer
 Performs the inverse operation of a Multiplexer

 A Demultiplexer (or Demux) is a combinational circuit that has:

1. One data input I d0

d1

2n Outputs
Demux
2. An n-bit select input S I d2
.
.
.
3. A maximum of 2n data outputs d2n–1
n
S
 The Demux directs the data input to one of the outputs

According to the select input S

 Demultiplexer
 Data input is transmitted to only one of the outputs
as determined by select input code
Demultiplexer

1-line-to-8-line demultiplexer
 Demultiplexer
 Example: 1- to -4 Demultiplexer
 Mux-Demux Application: Example

 This enables sharing a single communication line among a

number of devices.
 At any time, only one source and one destination can use the
communication line.
 Examples of Demultiplexers
 1-to-2 Demultiplexer

2 Outputs
if (S == 0) { d0 = I ; d1 = 0; } 0 d0

Demux
I
else { d1 = I ; d0 = 0 ; }
1 d1
Output expressions:
𝑑0 = 𝐼 𝑆 ′ ; 𝑑1 = 𝐼 𝑆 S
 1-to-4 Demultiplexer
if (S1S0 == 00) { d0 = I ; d1 = d2 = d3 = 0; } 0 d0

4 Outputs
Demux
else if (S1S0 == 01) { d1 = I ; d0 = d2 = d3 = 0; } I 1 d1
else if (S1S0 == 10) { d2 = I ; d0 = d1 = d3 = 0; } 2 d2
10
else { d3 = I ; d0 = d1 = d2 = 0; } 3 d3

Output expressions: S1S0

𝑑0 = 𝐼 𝑆1′ 𝑆0′ ; 𝑑1 = 𝐼 𝑆1′ 𝑆0 ; 𝑑2 = 𝐼 𝑆1 𝑆0′ ; 𝑑3 = 𝐼𝑆1 𝑆0
 Demultiplexer = Decoder with Enable
 A 1-to-4 demux is equivalent to a 2-to-4 decoder with enable
Demux select input S1 is equivalent to Decoder input a1
Demux select input S0 is equivalent to Decoder input a0
Demux Input I is equivalent to Decoder Enable EN

0 d0
0 d0 S1 = a1 1
2-to-4 1 d1
4 Outputs

S0 = a0 0
Demux

1 d1 Decoder 2 d2
I
2 d2 I = EN 3 d3
10
3 d3
Think of a decoder as directing the
S1S0 Enable signal to one output

 In general, a demux with n select inputs and 2n outputs is equivalent

to a n-to-2n decoder with enable input
 2-by-2 Crossbar Switch
 A 2×2 crossbar switch is a combinational circuit that has:
Two m-bit Inputs: A and B
if (S == 0) { X = A; Y = B; }
Two m-bit outputs: X and Y
else { X = B; Y = A; }
1-bit select input S
 Implement the 2×2 crossbar switch using multiplexers
 Solution: Two 2-input multiplexers are used

m m A[m–1:0] 0 m

Mux
A[m-1:0] 2×2 X [m-1:0] m X [m-1:0]
B[m–1:0] 1
Crossbar m
m m S
B[m-1:0] Switch Y [m-1:0]
0 m

Mux
Y [m-1:0]
1
S
 Sorting Two Unsigned Integers
 Design a circuit that sorts two m-bit unsigned integers A and B
Inputs: Two m-bit unsigned integers A and B
Outputs: X = min(A, B) and Y = max(A, B)
 Solution:
We will use a magnitude comparator to compare A with B, and
2×2 crossbar switch implemented using two 2-input multiplexers

B[m–1:0] 0 m

Mux
m X [m-1:0] = min(A, B)
A[m–1:0] m-bit A<B A[m–1:0] 1
m m
Magnitude A=B S
B[m–1:0] Comparator 0 m

Mux
m A>B Y [m-1:0] = max(A, B)
1
 Binary Decoders
 Given a n-bit binary code, there are 2n possible code values
 The decoder has an output for each possible code value
 The n-to-2n decoder has n inputs and 2n outputs
 Depending on the input code, only one output is set to
logic 1
 The conversion of input to output is called decoding

A decoder can have less

2n Outputs
n Inputs

n to 2n
than 2n outputs if some




Decoder
input codes are unused
 Decoder
 A decoder is a circuit that
creates an output based
on the binary states of a
given input
 Do the opposite of
encoder
 Decoder
Example: 3 to 8 Binary Decoder
 Examples of Binary Decoders
Inputs Outputs
0 d0 a1 a0 d0 d1 d2 d3

4 Outputs
2 Inputs

a1 1 2-to-4 1 d1 0 0 1 0 0 0 Truth
a0 0 Decoder 2 d2 0 1 0 1 0 0
d3 1 0 0 0 1 0 Tables
3
1 1 0 0 0 1

Inputs Outputs
0 d0
a2 a1 a0 d0 d1 d2 d3 d4 d5 d6 d7
1 d1
0 0 0 1 0 0 0 0 0 0 0
2 d2 0 0 1 0 1 0 0 0 0 0 0
a2 2
8 Outputs
3 Inputs

3-to-8 3 d3 0 1 0 0 0 1 0 0 0 0 0
a1 1
Decoder 4 d4 0 1 1 0 0 0 1 0 0 0 0
a0 0
5 d5 1 0 0 0 0 0 0 1 0 0 0
6 d6 1 0 1 0 0 0 0 0 1 0 0
7 d7 1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
 Decoder Implementation
Inputs Outputs 𝑎2
a1 a0 d0 d1 d2 d3 3-to-8 Decoder
0 0 1 0 0 0 𝑎1
0 1 0 1 0 0 𝑎0 𝑑0 = 𝑎2′ 𝑎1′ 𝑎0′
1 0 0 0 1 0
1 1 0 0 0 1
𝑑1 = 𝑎2′ 𝑎1′ 𝑎0
2-to-4
Decoder 𝑑2 = 𝑎2′ 𝑎1 𝑎0′
𝑎1
𝑎0 𝑑0 = 𝑎1′ 𝑎0′ 𝑑3 = 𝑎2′ 𝑎1 𝑎0
𝑑1 = 𝑎1′ 𝑎0 𝑑4 = 𝑎2 𝑎1′ 𝑎0′
𝑑2 = 𝑎1 𝑎0′ 𝑑5 = 𝑎2 𝑎1′ 𝑎0
𝑑3 = 𝑎1 𝑎0 𝑑6 = 𝑎2 𝑎1 𝑎0′
𝑑7 = 𝑎2 𝑎1 𝑎0
Each decoder output is a minterm
Using Decoders to Implement Functions
 A decoder generates all the minterms
 A Boolean function can be expressed as a sum of minterms
 Any function can be implemented using a decoder + OR gate
Note: the function must not be minimized
 Example: Full Adder sum = ∑(1, 2, 4, 7), cout = ∑(3, 5, 6, 7)

Inputs Outputs
d0
a b c cout sum
d1
0 0 0 0 0
d2 sum
0 0 1 0 1 a 2
0 1 0 0 1 3-to-8 d3
b 1
0 1 1 1 0 d
1 0 0 0 1 c 0 Decoder 4 cout
d5
1 0 1 1 0 d6
1 1 0 1 0
1 1 1 1 1
d7
Using Decoders to Implement Functions
 Good if many output functions of the same input variables
 If number of minterms is large  Wider OR gate is needed
 Use NOR gate if number of maxterms is less than minterms
 Example: f = ∑(2, 5, 6), g = ∏(3, 6)  g' = ∑(3, 6), h = ∑(0, 5)

Inputs Outputs
a b c f g h d0
0 0 0 0 1 1 d1 f
d2
0 0 1 0 1 0 a 2
0 1 0 1 1 0 3-to-8 d3
b 1 g
0 1 1 0 0 0
c 0 Decoder d4
1 0 0 0 1 0 d5
1 0 1 1 1 1 d6 h
1 1 0 1 0 0 d7
1 1 1 0 1 0
 2-to-4 Decoder with Enable Input
Truth Table
0 d0
a1 1
Inputs Outputs 2-to-4 1 d1
a0 0
d2
EN a1 a0 d0 d1 d2 d3 Decoder 2
EN 3 d3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0 𝑎1
1 1 0 0 0 1 0
𝑎0 𝑑0 = 𝐸𝑁 𝑎1′ 𝑎0′
1 1 1 0 0 0 1
𝑑1 = 𝐸𝑁 𝑎1′ 𝑎0

If EN input is zero then all 𝑑2 = 𝐸𝑁 𝑎1 𝑎0′

outputs are zeros, 𝑑3 = 𝐸𝑁 𝑎1 𝑎0
regardless of a1 and a0 𝐸𝑁
 Building Larger Decoders
 Larger decoders can be build using smaller ones
 A 3-to-8 decoder can be built using:
Two 2-to-4 decoders with Enable and an inverter (1-to-2
decoder)
Inputs Outputs
a2
0 d0
a2 a1 a0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 a1 1 Top
1 d1
0 0 0 1 0 0 0 0 0 0 0 a0 0 2-to-4
Decoder
2 d2
0 0 1 0 1 0 0 0 0 0 0 EN 3 d3
0 1 0 0 0 1 0 0 0 0 0

1-to-2 Decoder
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
0 d4
1 Bottom
1 d5
1 0 1 0 0 0 0 0 1 0 0 0 2-to-4
Decoder
2 d6
1 1 0 0 0 0 0 0 0 1 0
EN 3 d7
1 1 1 0 0 0 0 0 0 0 1
 Building Larger Decoders
a1 1 0 d0
2-to-4
1 d1
a0 0 Decoder
2 d2
A 4-to-16 0
EN 3 d3
decoder with
enable can be 1 2-to-4 0 d4
1 d5
built using five 2- 0 Decoder
2 d6
1
to-4 decoders a3 1 0
EN 3 d7
2-to-4 1
with enables a2 0 Decoder 2
1 0 d8
2-to-4
EN EN 3 1 d9
0 Decoder
2 d10
2
EN 3 d11

Larger decoders can be built 1 2-to-4 0 d12

1 d13
hierarchically in a similar way 0 Decoder
2 d14
3
EN 3 d15
 BCD to 7-Segment Decoder
 Seven-Segment Display:
◦ Made of Seven segments: light-emitting diodes (LED)
◦ Found in electronic devices: such as clocks, calculators, etc.

a
I3 BCD to b
I2 c
 BCD to 7-Segment Decoder I1
7-Segment d
e
 Called also a decoder, but not a binary decoder I0 Decoder f
g
 Accepts as input a BCD decimal digit (0 to 9)
 Generates output to the seven LED segments to display the BCD digit
 Each segment can be turned on or off separately
 BCD to 7-Segment Decoder
Specification: Truth Table
◦ Input: 4-bit BCD (I3, I2, I1, I0) BCD input 7-Segment Output
I3 I2 I1 I0 a b c d e f g
◦ Output: 7-bit (a, b, c, d, e, f, g) 0 0 0 0 1 1 1 1 1 1 0
◦ Display should be OFF for Non- 0 0 0 1 0 1 1 0 0 0 0

BCD input codes. 0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1
Implementation can use:
0 1 0 0 0 1 1 0 0 1 1
◦ A binary decoder 0 1 0 1 1 0 1 1 0 1 1
◦ Additional gates 0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
1010 to 0 0 0 0 0 0 0
1111
Implementing a BCD to 7-Segment Decoder
Truth Table
a
I3 I2 I1 I0 a b c d e f g
0
b 0 0 0 0 1 1 1 1 1 1 0
1
2 0 0 0 1 0 1 1 0 0 0 0
c
I3 3 0 0 1 0 1 1 0 1 1 0 1
4-to-10
I2 4 d 0 0 1 1 1 1 1 1 0 0 1
Binary
I1 5 0 1 0 0 0 1 1 0 0 1 1
I0 Decoder 6 e 0 1 0 1 1 0 1 1 0 1 1
7 0 1 1 0 1 0 1 1 1 1 1
8 0 1 1 1 1 1 1 0 0 0 0
9 f 1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
𝐼3 (𝐼2 + 𝐼1 ) g
1010 – 1111 0 0 0 0 0 0 0
Input > 9
NOR gate is used for 0's
 NAND Decoders with Inverted Outputs
Truth Table
0 d0
a1 1
Inputs Outputs 2-to-4 1 d1
a0 0
d2
EN a1 a0 d0 d1 d2 d3 Decoder 2
EN 3 d3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1 𝑎1
0 1 0 1 1 0 1
𝑎0 𝑑0 = (𝐸𝑁 ′ 𝑎1′ 𝑎0′ )′
0 1 1 1 1 1 0
𝑑1 = (𝐸𝑁 ′ 𝑎1′ 𝑎0 )′

Some decoders are constructed 𝑑2 = (𝐸𝑁 ′ 𝑎1 𝑎0′ )′

with NAND gates. Their outputs are
inverted. The Enable input is also
𝑑3 = (𝐸𝑁 ′ 𝑎1 𝑎0 )′
active low (Enable if zero) 𝐸𝑁
 Using NAND Decoders
 NAND decoders can be used to implement functions
 Use NAND gates to output the minterms (if fewer ones)
 Use AND gates to output the maxterms (if fewer zeros)
 Example: f = ∑(2, 5, 6), g = ∏(3, 6), h = ∑(0, 5)
Inputs Outputs
a b c f g h d0
0 0 0 0 1 1 3-to-8 d1 f
0 0 1 0 1 0 a 2 Decoder d2
0 1 0 1 1 0 d3
b 1 Inverted g
0 1 1 0 0 0 d4
c 0
1 0 0 0 1 0 Outputs d5
1 0 1 1 1 1 (NAND) d6 h
1 1 0 1 0 0 d7
1 1 1 0 1 0
 Example: Decoder Active Low
• We can use active-low decoders to implement arbitrary functions
too, but as a product of maxterms.
• For example, here is an implementation of the function,
f(x,y,z) = M(4,5,7), using an active-low decoder.

• The “ground” symbol connected to EN represents logical 0, so this

decoder is always enabled.
• Remember that you need an AND gate for a product of sums.
 Encoders
 An encoder performs the opposite operation of a decoder
 It converts a 2n input to an n-bit output code
 The output indicates which input is active (logic 1)
 Typically, one input should be 1 and all others must be 0's
 The conversion of input to output is called encoding

A encoder can have less

n Outputs
2n Inputs 2n to n
than 2n inputs if some



Encoder
input lines are unused
 Encoder
 Encoder converts information such as decimal number or
an alphabetical character into some binary coded form
 Encoder is usually used for:
oData representation
oData security
oData compression
 Example of an 8-to-3 Binary Encoder
 8 inputs, 3 outputs, only one input is 1, all others are 0's
 Encoder generates the output binary code for the active input
 Output is not specified if more than one input is 1

Inputs Outputs
d0 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a2 a1 a0
d1 1
0 0 0 0 0 0 0 1 0 0 0
d2 2 0 0 0 0 0 0 1 0 0 0 1
8-to-3 2 a2 3 Outputs
8 Inputs

d3 3 0 0 0 0 0 1 0 0 0 1 0
Binary 1 a1
d4 4 0 0 0 0 1 0 0 0 0 1 1
0 a0
d5 5 Encoder 0 0 0 1 0 0 0 0 1 0 0
d6 6 0 0 1 0 0 0 0 0 1 0 1
d7 7 0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 8-to-3 Binary Encoder Implementation
Inputs Outputs d0 0
d1 1
d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a2 a1 a0 d2 2 8-to-3 2 a2
0 0 0 0 0 0 0 1 0 0 0 d3 3
Binary 1 a1
0 0 0 0 0 0 1 0 0 0 1 d4 4
0 a0
0 0 0 0 0 1 0 0 0 1 0 d5 5 Encoder
d6 6
0 0 0 0 1 0 0 0 0 1 1
d7 7
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1 d4
d5
0 1 0 0 0 0 0 0 1 1 0 d6 a2
1 0 0 0 0 0 0 0 1 1 1 d7
d2
a2 = d4 + d5 + d6 + d7 8-to-3 binary d3
d6 a1
encoder d7
a1 = d2 + d3 + d6 + d7 implemented using
d1
three d3
a0
a0 = d1 + d3 + d5 + d7 4-input OR gates
d5
d7
 Binary Encoder Limitations
 Exactly one input must be 1 at a time (all others must be 0's)
 If more than one input is 1 then the output will be incorrect
 For example, if d3 = d6 = 1 a2 = d4 + d5 + d6 + d7
Then a2 a1 a0 = 111 (incorrect) a1 = d2 + d3 + d6 + d7
 Two problems to resolve: a0 = d1 + d3 + d5 + d7
1. If two inputs are 1 at the same time, what should be the output?
2. If all inputs are 0's, what should be the output?
 Output a2 a1 a0 = 000 if d0 = 1 or all inputs are 0's
How to resolve this ambiguity?
 Priority Encoder
 Eliminates the two problems of the binary encoder
 Inputs are ranked from highest priority to lowest priority
 If more than one input is active (logic 1) then priority is used
Output encodes the active input with higher priority
 If all inputs are zeros then the V (Valid) output is zero
Indicates that all inputs are zeros
Inputs Outputs
d 3 d 2 d 1 d 0 a1 a0 V
d3 0 0 0 0 X X 0
3 = highest priority
1 a1 Condensed
d2 0 0 0 1 0 0 1
2 4-to-2 Priority Truth Table
0 a0 0 0 1 X 0 1 1
d1 1 Encoder All 16 cases
0 1 X X 1 0 1
d0 0 = lowest priority V are listed 1 X X X 1 1 1
Implementing a 4-to-2 Priority Encoder
𝑑1 𝑑0
K-Map of 𝑎1 𝑑1 𝑑0
K-Map of 𝑎0
Inputs Outputs
𝑑3 𝑑2 00 01 11 10 𝑑3 𝑑2 00 01 11 10
d 3 d 2 d 1 d 0 a1 a0 V
00 X 00 X 1 1
0 0 0 0 X X 0
0 0 0 1 0 0 1 01 1 1 1 1 01
0 0 1 X 0 1 1
11 1 1 1 1 11 1 1 1 1
0 1 X X 1 0 1
1 X X X 1 1 1 10 1 1 1 1 10 1 1 1 1

d3
a1
Output Expressions: d2

𝑎1 = 𝑑3 + 𝑑2 a0
𝑎0 = 𝑑3 + 𝑑1 𝑑2′ d1

𝑉 = 𝑑3 + 𝑑2 + 𝑑1 + 𝑑0 V
d0
Encoder - Example: 8-to-3 Binary Encoder